From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 24C17AC142A for ; Wed, 31 Jan 2024 12:05:30 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=raFjiM85/+7kJMMyLi1+jtDmR09YwUPx512r+8rvWRY=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1706702729; v=1; b=OJlNnDiNJgyjY+Gi0YTgvTDgd3BDv6lN+1EtmYidKNyfJq7jiYXVxCiQBjh6y2HNvKyf2uCY xOrflRlppvY39Twkcp6AfIKvN4ixo4/aQ96WS8r5q8cU1fDe+d2LQsfHYt4K7O5VgRUPHSB4EFs EtdosQ8t4CiMHjNRH23MET6A= X-Received: by 127.0.0.2 with SMTP id atOBYY7687511xu3p7BRRNVC; Wed, 31 Jan 2024 04:05:29 -0800 X-Received: from sgoci-sdnproxy-4.icoremail.net (sgoci-sdnproxy-4.icoremail.net [129.150.39.64]) by mx.groups.io with SMTP id smtpd.web10.12342.1706702726853402785 for ; Wed, 31 Jan 2024 04:05:27 -0800 X-Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-6 (Coremail) with SMTP id AQAAfwC3vMiEN7plYUL3BA--.12943S2; Wed, 31 Jan 2024 20:05:24 +0800 (CST) X-Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAfwAXA2l4N7pl8_MCAA--.2280S9; Wed, 31 Jan 2024 20:05:21 +0800 (CST) From: "Xiong Yining" To: devel@edk2.groups.io Cc: quic_llindhol@quicinc.com, ardb+tianocore@kernel.org, graeme@xora.org.uk, marcin.juszkiewicz@linaro.org, chenbaozi@phytium.com.cn, Xiong Yining Subject: [edk2-devel] [PATCH v5 6/7] Platform/SbsaQemu: get the information of memory via SMC calls Date: Wed, 31 Jan 2024 12:05:06 +0000 Message-Id: <20240131120507.2829117-7-xiongyining1480@phytium.com.cn> In-Reply-To: <20240131120507.2829117-1-xiongyining1480@phytium.com.cn> References: <20240131120507.2829117-1-xiongyining1480@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAfwAXA2l4N7pl8_MCAA--.2280S9 X-CM-SenderInfo: x0lr0wp1lqx0bjrumio6sk53xlxphulrpou0/1tbiAQABBmW5T2UIKQACsT X-Coremail-Antispam: 1Uk129KBjvJXoW3Ww1kXw4xXr1DKFWrurW7Arb_yoWxKr45pF n7AFZ5Cr4UJr9Iyr4xJayFqry5Ga43K3yDGFZFvr1Yyr47J3WrZrWUtr97J3WUXr98WayD WFW8XayUuFn8GaDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj DUYxn0WfASr-VFAU7a7-sFnT9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUU UUUUU Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,xiongyining1480@phytium.com.cn List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: rNbTi2LAX1a7eoWjg3txcRkxx7686176AA= Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=OJlNnDiN; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Provide functions to check for memory information: - amount of memory nodes - memory address - NUMA node id for memory Values are read from TF-A using platform specific SMC calls. Signed-off-by: Xiong Yining Signed-off-by: Chen Baozi --- .../Library/SbsaQemuLib/SbsaQemuLib.inf | 2 +- .../Include/IndustryStandard/SbsaQemuSmc.h | 2 + .../Include/Library/SbsaQemuHardwareInfoLib.h | 28 ++++++++++ .../SbsaQemuHardwareInfoLib.c | 47 ++++++++++++++++ .../Library/SbsaQemuLib/SbsaQemuMem.c | 54 +++++-------------- 5 files changed, 91 insertions(+), 42 deletions(-) diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf index c067a80cc715..fb856efe4c27 100644 --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf @@ -32,9 +32,9 @@ ArmLib BaseMemoryLib DebugLib - FdtLib MemoryAllocationLib PcdLib + SbsaQemuHardwareInfoLib [Pcd] gArmTokenSpaceGuid.PcdSystemMemoryBase diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h index d9faee7fa5b2..e7bf54978d4e 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h @@ -16,6 +16,8 @@ #define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101) #define SIP_SVC_GET_CPU_COUNT SMC_SIP_FUNCTION_ID(200) #define SIP_SVC_GET_CPU_NODE SMC_SIP_FUNCTION_ID(201) +#define SIP_SVC_GET_MEMORY_NODE_COUNT SMC_SIP_FUNCTION_ID(300) +#define SIP_SVC_GET_MEMORY_NODE SMC_SIP_FUNCTION_ID(301) /* * SMCC does not define return codes for SiP functions. diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuHardwareInfoLib.h b/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuHardwareInfoLib.h index ca52c6b27093..0b71a3f7e6eb 100644 --- a/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuHardwareInfoLib.h +++ b/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuHardwareInfoLib.h @@ -9,6 +9,12 @@ #ifndef SBSA_QEMU_HARDWARE_INFO_ #define SBSA_QEMU_HARDWARE_INFO_ +typedef struct{ + UINT32 NodeId; + UINT64 AddressBase; + UINT64 AddressSize; +} MemoryInfo; + /** Get CPU count from information passed by Qemu. @@ -42,4 +48,26 @@ SbsaQemuGetCpuNumaNode ( IN UINTN CpuId ); +/** + Get the number of memory node from device tree passed by Qemu. + + @retval the number of memory nodes. +**/ +UINT32 +SbsaQemuGetMemNodeCount ( + VOID + ); + +/** + Get memory infomation(node-id, addressbase, addresssize) for a given memory node from device tree passed by Qemu. + + @param [in] MemoryId Index of memory to retrieve memory information. + + @retval memory infomation for given memory node. +**/ +MemoryInfo +SbsaQemuGetMemInfo ( + IN UINTN MemoryId + ); + #endif /* SBSA_QEMU_HARDWARE_INFO_ */ diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c index 923997edb2f1..d6d242253f33 100644 --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c @@ -203,3 +203,50 @@ SbsaQemuGetCpuNumaNode ( return Arg0; } + +UINT32 +SbsaQemuGetMemNodeCount ( + VOID + ) +{ + UINTN SmcResult; + UINTN Arg0; + + SmcResult = ArmCallSmc0 (SIP_SVC_GET_MEMORY_NODE_COUNT, &Arg0, NULL, NULL); + if (SmcResult != SMC_SIP_CALL_SUCCESS) { + DEBUG ((DEBUG_ERROR, "SIP_SVC_GET_MEMORY_NODE_COUNT call failed.\n")); + } + + DEBUG(( DEBUG_INFO, "The number of the memory nodes is %ld\n", Arg0)); + return (UINT32)Arg0; +} + +MemoryInfo +SbsaQemuGetMemInfo ( + IN UINTN MemoryId + ) +{ + UINTN SmcResult; + UINTN Arg0; + UINTN Arg1; + UINTN Arg2; + MemoryInfo MemInfo; + + Arg0 = MemoryId; + + SmcResult = ArmCallSmc1 (SIP_SVC_GET_MEMORY_NODE, &Arg0, &Arg1, &Arg2); + if (SmcResult != SMC_SIP_CALL_SUCCESS) { + DEBUG ((DEBUG_ERROR, "SIP_SVC_GET_MEMORY_NODE call failed.\n")); + } else { + MemInfo.NodeId = Arg0; + MemInfo.AddressBase = Arg1; + MemInfo.AddressSize = Arg2; + } + + DEBUG(( DEBUG_INFO, "NUMA node for System RAM:%d = 0x%lx - 0x%lx\n", + MemInfo.NodeId, + MemInfo.AddressBase, + MemInfo.AddressBase + MemInfo.AddressSize -1 )); + + return MemInfo; +} diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c index 8c2eb0b6a028..5a418a461174 100644 --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include // Number of Virtual Memory Map Descriptors #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 4 @@ -23,53 +23,25 @@ SbsaQemuLibConstructor ( VOID ) { - VOID *DeviceTreeBase; - INT32 Node, Prev; UINT64 NewBase, CurBase; UINT64 NewSize, CurSize; - CONST CHAR8 *Type; - INT32 Len; - CONST UINT64 *RegProp; + UINT32 NumMemNodes; + UINT32 Index; + MemoryInfo MemInfo; RETURN_STATUS PcdStatus; NewBase = 0; NewSize = 0; - DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress); - ASSERT (DeviceTreeBase != NULL); - - // Make sure we have a valid device tree blob - ASSERT (fdt_check_header (DeviceTreeBase) == 0); - - // Look for the lowest memory node - for (Prev = 0;; Prev = Node) { - Node = fdt_next_node (DeviceTreeBase, Prev, NULL); - if (Node < 0) { - break; - } - - // Check for memory node - Type = fdt_getprop (DeviceTreeBase, Node, "device_type", &Len); - if (Type && AsciiStrnCmp (Type, "memory", Len) == 0) { - // Get the 'reg' property of this node. For now, we will assume - // two 8 byte quantities for base and size, respectively. - RegProp = fdt_getprop (DeviceTreeBase, Node, "reg", &Len); - if (RegProp != 0 && Len == (2 * sizeof (UINT64))) { - - CurBase = fdt64_to_cpu (ReadUnaligned64 (RegProp)); - CurSize = fdt64_to_cpu (ReadUnaligned64 (RegProp + 1)); - - DEBUG ((DEBUG_INFO, "%a: System RAM @ 0x%lx - 0x%lx\n", - __FUNCTION__, CurBase, CurBase + CurSize - 1)); - - if (NewBase > CurBase || NewBase == 0) { - NewBase = CurBase; - NewSize = CurSize; - } - } else { - DEBUG ((DEBUG_ERROR, "%a: Failed to parse FDT memory node\n", - __FUNCTION__)); - } + NumMemNodes = SbsaQemuGetMemNodeCount(); + for(Index = 0; Index < NumMemNodes; Index++){ + MemInfo = SbsaQemuGetMemInfo(Index); + CurBase = MemInfo.AddressBase; + CurSize = MemInfo.AddressSize; + + if (NewBase > CurBase || NewBase == 0) { + NewBase = CurBase; + NewSize = CurSize; } } -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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