* [edk2-devel] [PATCH v1 01/19] MdePkg: Add the header file named Csr.h for LoongArch64
2024-02-02 2:26 [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Chao Li
@ 2024-02-02 2:27 ` Chao Li
2024-02-02 2:27 ` [edk2-devel] [PATCH v1 02/19] MdePkg: Add LoongArch64 FPU function set into BaseCpuLib Chao Li
` (18 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Chao Li @ 2024-02-02 2:27 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu
Adding Csr.h for LoongArch64, it is use for accessing the CSR registers.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Acked-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
---
MdePkg/Include/Register/LoongArch64/Csr.h | 263 ++++++++++++++++++++++
1 file changed, 263 insertions(+)
create mode 100644 MdePkg/Include/Register/LoongArch64/Csr.h
diff --git a/MdePkg/Include/Register/LoongArch64/Csr.h b/MdePkg/Include/Register/LoongArch64/Csr.h
new file mode 100644
index 0000000000..aa22a26564
--- /dev/null
+++ b/MdePkg/Include/Register/LoongArch64/Csr.h
@@ -0,0 +1,263 @@
+/** @file
+
+ Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+ - EXC - Exception
+ - CSR - CPU Status Register
+**/
+
+#ifndef LOONGARCH_CSR_H_
+#define LOONGARCH_CSR_H_
+
+#include <Base.h>
+
+//
+// CSR register numbers
+//
+
+//
+// Basic CSR registers
+//
+#define LOONGARCH_CSR_CRMD 0x0
+#define LOONGARCH_CSR_PRMD 0x1
+#define LOONGARCH_CSR_EUEN 0x2
+#define CSR_EUEN_LBTEN_SHIFT 3
+#define CSR_EUEN_LBTEN (0x1ULL << CSR_EUEN_LBTEN_SHIFT)
+#define CSR_EUEN_LASXEN_SHIFT 2
+#define CSR_EUEN_LASXEN (0x1ULL << CSR_EUEN_LASXEN_SHIFT)
+#define CSR_EUEN_LSXEN_SHIFT 1
+#define CSR_EUEN_LSXEN (0x1ULL << CSR_EUEN_LSXEN_SHIFT)
+#define CSR_EUEN_FPEN_SHIFT 0
+#define CSR_EUEN_FPEN (0x1ULL << CSR_EUEN_FPEN_SHIFT)
+#define LOONGARCH_CSR_MISC 0x3
+#define LOONGARCH_CSR_ECFG 0x4
+
+#define LOONGARCH_CSR_ESTAT 0x5
+#define CSR_ESTAT_ESUBCODE_SHIFT 22
+#define CSR_ESTAT_ESUBCODE_WIDTH 9
+#define CSR_ESTAT_ESUBCODE (0x1ffULL << CSR_ESTAT_ESUBCODE_SHIFT)
+#define CSR_ESTAT_EXC_SHIFT 16
+#define CSR_ESTAT_EXC_WIDTH 6
+#define CSR_ESTAT_EXC (0x3FULL << CSR_ESTAT_EXC_SHIFT)
+#define CSR_ESTAT_IS_SHIFT 0
+#define CSR_ESTAT_IS_WIDTH 15
+#define CSR_ESTAT_IS (0x7FFFULL << CSR_ESTAT_IS_SHIFT)
+
+#define LOONGARCH_CSR_ERA 0x6
+#define LOONGARCH_CSR_BADV 0x7
+#define LOONGARCH_CSR_BADI 0x8
+#define LOONGARCH_CSR_EBASE 0xC // Exception entry base address
+
+//
+// TLB related CSR registers
+//
+#define LOONGARCH_CSR_TLBIDX 0x10 // TLB Index, EHINV, PageSize, NP
+#define LOONGARCH_CSR_TLBEHI 0x11 // TLB EntryHi
+#define LOONGARCH_CSR_TLBELO0 0x12 // TLB EntryLo0
+#define LOONGARCH_CSR_TLBELO1 0x13 // TLB EntryLo1
+#define LOONGARCH_CSR_ASID 0x18 // ASID
+#define LOONGARCH_CSR_PGDL 0x19 // Page table base address when VA[47] = 0
+#define LOONGARCH_CSR_PGDH 0x1A // Page table base address when VA[47] = 1
+#define LOONGARCH_CSR_PGD 0x1B // Page table base
+#define LOONGARCH_CSR_PWCTL0 0x1C // PWCtl0
+#define LOONGARCH_CSR_PWCTL1 0x1D // PWCtl1
+#define LOONGARCH_CSR_STLBPGSIZE 0x1E
+#define LOONGARCH_CSR_RVACFG 0x1F
+
+///
+/// Page table property definitions
+///
+#define PAGE_VALID_SHIFT 0
+#define PAGE_DIRTY_SHIFT 1
+#define PAGE_PLV_SHIFT 2 // 2~3, two bits
+#define CACHE_SHIFT 4 // 4~5, two bits
+#define PAGE_GLOBAL_SHIFT 6
+#define PAGE_HUGE_SHIFT 6 // HUGE is a PMD bit
+
+#define PAGE_HGLOBAL_SHIFT 12 // HGlobal is a PMD bit
+#define PAGE_PFN_SHIFT 12
+#define PAGE_PFN_END_SHIFT 48
+#define PAGE_NO_READ_SHIFT 61
+#define PAGE_NO_EXEC_SHIFT 62
+#define PAGE_RPLV_SHIFT 63
+
+///
+/// Used by TLB hardware (placed in EntryLo*)
+///
+#define PAGE_VALID ((UINTN)(1) << PAGE_VALID_SHIFT)
+#define PAGE_DIRTY ((UINTN)(1) << PAGE_DIRTY_SHIFT)
+#define PAGE_PLV ((UINTN)(3) << PAGE_PLV_SHIFT)
+#define PAGE_GLOBAL ((UINTN)(1) << PAGE_GLOBAL_SHIFT)
+#define PAGE_HUGE ((UINTN)(1) << PAGE_HUGE_SHIFT)
+#define PAGE_HGLOBAL ((UINTN)(1) << PAGE_HGLOBAL_SHIFT)
+#define PAGE_NO_READ ((UINTN)(1) << PAGE_NO_READ_SHIFT)
+#define PAGE_NO_EXEC ((UINTN)(1) << PAGE_NO_EXEC_SHIFT)
+#define PAGE_RPLV ((UINTN)(1) << PAGE_RPLV_SHIFT)
+#define CACHE_MASK ((UINTN)(3) << CACHE_SHIFT)
+#define PFN_SHIFT (EFI_PAGE_SHIFT - 12 + PAGE_PFN_SHIFT)
+
+#define PLV_KERNEL 0
+#define PLV_USER 3
+
+#define PAGE_USER (PLV_USER << PAGE_PLV_SHIFT)
+#define PAGE_KERNEL (PLV_KERN << PAGE_PLV_SHIFT)
+
+#define CACHE_SUC (0 << CACHE_SHIFT) // Strong-ordered UnCached
+#define CACHE_CC (1 << CACHE_SHIFT) // Coherent Cached
+#define CACHE_WUC (2 << CACHE_SHIFT) // Weak-ordered UnCached
+
+//
+// Config CSR registers
+//
+#define LOONGARCH_CSR_CPUNUM 0x20 // CPU core number
+#define LOONGARCH_CSR_PRCFG1 0x21 // Config1
+#define LOONGARCH_CSR_PRCFG2 0x22 // Config2
+#define LOONGARCH_CSR_PRCFG3 0x23 // Config3
+
+//
+// Kscratch registers
+//
+#define LOONGARCH_CSR_KS0 0x30
+#define LOONGARCH_CSR_KS1 0x31
+#define LOONGARCH_CSR_KS2 0x32
+#define LOONGARCH_CSR_KS3 0x33
+#define LOONGARCH_CSR_KS4 0x34
+#define LOONGARCH_CSR_KS5 0x35
+#define LOONGARCH_CSR_KS6 0x36
+#define LOONGARCH_CSR_KS7 0x37
+#define LOONGARCH_CSR_KS8 0x38
+
+//
+// Stable timer registers
+//
+#define LOONGARCH_CSR_TMID 0x40 // Timer ID
+#define LOONGARCH_CSR_TMCFG 0x41
+#define LOONGARCH_CSR_TMCFG_EN (1ULL << 0)
+#define LOONGARCH_CSR_TMCFG_PERIOD (1ULL << 1)
+#define LOONGARCH_CSR_TMCFG_TIMEVAL (0x3FFFFFFFFFFFULL << 2)
+#define LOONGARCH_CSR_TVAL 0x42 // Timer value
+#define LOONGARCH_CSR_CNTC 0x43 // Timer offset
+#define LOONGARCH_CSR_TINTCLR 0x44 // Timer interrupt clear
+
+//
+// TLB refill exception base address
+//
+#define LOONGARCH_CSR_TLBREBASE 0x88 // TLB refill exception entry
+#define LOONGARCH_CSR_TLBRBADV 0x89 // TLB refill badvaddr
+#define LOONGARCH_CSR_TLBRERA 0x8a // TLB refill ERA
+#define LOONGARCH_CSR_TLBRSAVE 0x8b // KScratch for TLB refill exception
+#define LOONGARCH_CSR_TLBRELO0 0x8c // TLB refill entrylo0
+#define LOONGARCH_CSR_TLBRELO1 0x8d // TLB refill entrylo1
+#define LOONGARCH_CSR_TLBREHI 0x8e // TLB refill entryhi
+
+//
+// Direct map windows registers
+//
+#define LOONGARCH_CSR_DMWIN0 0x180 // 64 direct map win0: MEM & IF
+#define LOONGARCH_CSR_DMWIN1 0x181 // 64 direct map win1: MEM & IF
+#define LOONGARCH_CSR_DMWIN2 0x182 // 64 direct map win2: MEM
+#define LOONGARCH_CSR_DMWIN3 0x183 // 64 direct map win3: MEM
+//
+// CSR register numbers end
+//
+
+//
+// IOCSR register numbers
+//
+#define LOONGARCH_IOCSR_FEATURES 0x8
+#define IOCSRF_TEMP (1ULL << 0)
+#define IOCSRF_NODECNT (1ULL << 1)
+#define IOCSRF_MSI (1ULL << 2)
+#define IOCSRF_EXTIOI (1ULL << 3)
+#define IOCSRF_CSRIPI (1ULL << 4)
+#define IOCSRF_FREQCSR (1ULL << 5)
+#define IOCSRF_FREQSCALE (1ULL << 6)
+#define IOCSRF_DVFSV1 (1ULL << 7)
+#define IOCSRF_EXTIOI_DECODE (1ULL << 9)
+#define IOCSRF_FLATMODE (1ULL << 10)
+#define IOCSRF_VM (1ULL << 11)
+
+#define LOONGARCH_IOCSR_VENDOR 0x10
+
+#define LOONGARCH_IOCSR_CPUNAME 0x20
+
+#define LOONGARCH_IOCSR_NODECNT 0x408
+
+#define LOONGARCH_IOCSR_MISC_FUNC 0x420
+#define IOCSR_MISC_FUNC_TIMER_RESET (1ULL << 21)
+#define IOCSR_MISC_FUNC_EXT_IOI_EN (1ULL << 48)
+
+#define LOONGARCH_IOCSR_CPUTEMP 0x428
+
+//
+// PerCore CSR, only accessable by local cores
+//
+#define LOONGARCH_IOCSR_IPI_STATUS 0x1000
+#define LOONGARCH_IOCSR_IPI_EN 0x1004
+#define LOONGARCH_IOCSR_IPI_SET 0x1008
+#define LOONGARCH_IOCSR_IPI_CLEAR 0x100c
+#define LOONGARCH_IOCSR_MBUF0 0x1020
+#define LOONGARCH_IOCSR_MBUF1 0x1028
+#define LOONGARCH_IOCSR_MBUF2 0x1030
+#define LOONGARCH_IOCSR_MBUF3 0x1038
+
+#define LOONGARCH_IOCSR_IPI_SEND 0x1040
+#define IOCSR_IPI_SEND_IP_SHIFT 0
+#define IOCSR_IPI_SEND_CPU_SHIFT 16
+#define IOCSR_IPI_SEND_BLOCKING (1ULL << 31)
+
+#define LOONGARCH_IOCSR_MBUF_SEND 0x1048
+#define IOCSR_MBUF_SEND_BLOCKING (1ULL << 31)
+#define IOCSR_MBUF_SEND_BOX_SHIFT 2
+#define IOCSR_MBUF_SEND_BOX_LO(box) (box << 1)
+#define IOCSR_MBUF_SEND_BOX_HI(box) ((box << 1) + 1)
+#define IOCSR_MBUF_SEND_CPU_SHIFT 16
+#define IOCSR_MBUF_SEND_BUF_SHIFT 32
+#define IOCSR_MBUF_SEND_H32_MASK 0xFFFFFFFF00000000ULL
+
+#define LOONGARCH_IOCSR_ANY_SEND 0x1158
+#define IOCSR_ANY_SEND_BLOCKING (1ULL << 31)
+#define IOCSR_ANY_SEND_CPU_SHIFT 16
+#define IOCSR_ANY_SEND_MASK_SHIFT 27
+#define IOCSR_ANY_SEND_BUF_SHIFT 32
+#define IOCSR_ANY_SEND_H32_MASK 0xFFFFFFFF00000000ULL
+
+//
+// Register offset and bit definition for CSR access
+//
+#define LOONGARCH_IOCSR_TIMER_CFG 0x1060
+#define LOONGARCH_IOCSR_TIMER_TICK 0x1070
+#define IOCSR_TIMER_CFG_RESERVED BIT63
+#define IOCSR_TIMER_CFG_PERIODIC BIT62
+#define IOCSR_TIMER_CFG_EN BIT61
+#define IOCSR_TIMER_MASK 0x0FFFFFFFFFFFFULL
+#define IOCSR_TIMER_INITVAL_RST (0xFFFFULL << 48)
+//
+// IOCSR register numbers end
+//
+
+//
+// Invalid addr with global=1 or matched asid in current TLB
+//
+#define INVTLB_ADDR_GTRUE_OR_ASID 0x6
+
+//
+// Bits 8 and 9 of FPU Status Register specify the rounding mode
+//
+#define FPU_CSR_RM 0x300
+#define FPU_CSR_RN 0x000 // nearest
+#define FPU_CSR_RZ 0x100 // towards zero
+#define FPU_CSR_RU 0x200 // towards +Infinity
+#define FPU_CSR_RD 0x300 // towards -Infinity
+
+#define DEFAULT_PAGE_SIZE 0x0c
+#define CSR_TLBIDX_SIZE_MASK 0x3f000000
+#define CSR_TLBIDX_PS_SHIFT 24
+#define CSR_TLBIDX_SIZE CSR_TLBIDX_PS_SHIFT
+#define CSR_TLBREHI_PS_SHIFT 0x0
+#define CSR_TLBREHI_PS 0x3f
+
+#endif
--
2.27.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [edk2-devel] [PATCH v1 02/19] MdePkg: Add LoongArch64 FPU function set into BaseCpuLib
2024-02-02 2:26 [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Chao Li
2024-02-02 2:27 ` [edk2-devel] [PATCH v1 01/19] MdePkg: Add the header file named Csr.h for LoongArch64 Chao Li
@ 2024-02-02 2:27 ` Chao Li
2024-02-02 2:27 ` [edk2-devel] [PATCH v1 03/19] MdePkg: Add LoongArch64 exception function set into BaseLib Chao Li
` (17 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Chao Li @ 2024-02-02 2:27 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu
Adding InitializeFloatingPointUnits, EnableFloatingPointUnits and
DisableFloatingPointUnits functions for LoongArch64.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Acked-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
---
MdePkg/Include/Library/CpuLib.h | 43 ++++++++++++++--
MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 7 ++-
.../Library/BaseCpuLib/LoongArch/DisableFpu.S | 17 +++++++
.../Library/BaseCpuLib/LoongArch/EnableFpu.S | 17 +++++++
.../BaseCpuLib/LoongArch/InitializeFpu.S | 51 +++++++++++++++++++
5 files changed, 128 insertions(+), 7 deletions(-)
create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/DisableFpu.S
create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/EnableFpu.S
create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/InitializeFpu.S
diff --git a/MdePkg/Include/Library/CpuLib.h b/MdePkg/Include/Library/CpuLib.h
index 3f29937dc7..27f3f82ab9 100644
--- a/MdePkg/Include/Library/CpuLib.h
+++ b/MdePkg/Include/Library/CpuLib.h
@@ -8,6 +8,7 @@
As a result, these services could not be defined in the Base Library.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -41,14 +42,16 @@ CpuFlushTlb (
VOID
);
-#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
+#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) || defined (MDE_CPU_LOONGARCH64)
/**
+ Initialize the CPU floating point units.
+
Initializes floating point units for requirement of UEFI specification.
- This function initializes floating-point control word to 0x027F (all exceptions
- masked,double-precision, round-to-nearest) and multimedia-extensions control word
- (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
- for masked underflow).
+ For IA32 and X64, this function initializes floating-point control word to 0x027F
+ (all exceptions masked,double-precision, round-to-nearest) and multimedia-extensions
+ control word (if supported) to 0x1F80 (all exceptions masked, round-to-nearest,
+ flush to zero for masked underflow).
**/
VOID
EFIAPI
@@ -56,6 +59,10 @@ InitializeFloatingPointUnits (
VOID
);
+#endif
+
+#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
+
/**
Determine if the standard CPU signature is "AuthenticAMD".
@retval TRUE The CPU signature matches.
@@ -89,4 +96,30 @@ GetCpuSteppingId (
#endif
+#if defined (MDE_CPU_LOONGARCH64)
+
+/**
+ Enable the CPU floating point units.
+
+ Enable the CPU floating point units.
+**/
+VOID
+EFIAPI
+EnableFloatingPointUnits (
+ VOID
+ );
+
+/**
+ Disable the CPU floating point units.
+
+ Disable the CPU floating point units.
+**/
+VOID
+EFIAPI
+DisableFloatingPointUnits (
+ VOID
+ );
+
+#endif
+
#endif
diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
index 9a162afe6d..89f6272f11 100644
--- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
@@ -65,8 +65,11 @@ [Sources.RISCV64]
RiscV/Cpu.S
[Sources.LOONGARCH64]
- LoongArch/CpuFlushTlb.S | GCC
- LoongArch/CpuSleep.S | GCC
+ LoongArch/CpuFlushTlb.S | GCC
+ LoongArch/CpuSleep.S | GCC
+ LoongArch/InitializeFpu.S | GCC
+ LoongArch/EnableFpu.S | GCC
+ LoongArch/DisableFpu.S | GCC
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseCpuLib/LoongArch/DisableFpu.S b/MdePkg/Library/BaseCpuLib/LoongArch/DisableFpu.S
new file mode 100644
index 0000000000..33c6bf3411
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/LoongArch/DisableFpu.S
@@ -0,0 +1,17 @@
+#------------------------------------------------------------------------------
+#
+# DisableFloatingPointUnits() for LoongArch64
+#
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+ASM_GLOBAL ASM_PFX(DisableFloatingPointUnits)
+
+ASM_PFX(DisableFloatingPointUnits):
+ li.w $t0, 0x1
+ csrxchg $zero, $t0, 0x2
+
+ jirl $zero, $ra, 0
+ .end
diff --git a/MdePkg/Library/BaseCpuLib/LoongArch/EnableFpu.S b/MdePkg/Library/BaseCpuLib/LoongArch/EnableFpu.S
new file mode 100644
index 0000000000..3e4f7411f1
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/LoongArch/EnableFpu.S
@@ -0,0 +1,17 @@
+#------------------------------------------------------------------------------
+#
+# EnableFloatingPointUnits() for LoongArch64
+#
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+ASM_GLOBAL ASM_PFX(EnableFloatingPointUnits)
+
+ASM_PFX(EnableFloatingPointUnits):
+ li.w $t0, 0x1
+ csrxchg $t0, $t0, 0x2
+
+ jirl $zero, $ra, 0
+ .end
diff --git a/MdePkg/Library/BaseCpuLib/LoongArch/InitializeFpu.S b/MdePkg/Library/BaseCpuLib/LoongArch/InitializeFpu.S
new file mode 100644
index 0000000000..2cea5558a6
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/LoongArch/InitializeFpu.S
@@ -0,0 +1,51 @@
+#------------------------------------------------------------------------------
+#
+# InitializeFloatingPointUnits() for LoongArch64
+#
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)
+
+ASM_PFX(InitializeFloatingPointUnits):
+ li.d $t0, 0x0 // RNE mode
+ movgr2fcsr $r0, $t0
+ li.d $t1, -1 // SNaN
+
+ movgr2fr.d $f0, $t1
+ movgr2fr.d $f1, $t1
+ movgr2fr.d $f2, $t1
+ movgr2fr.d $f3, $t1
+ movgr2fr.d $f4, $t1
+ movgr2fr.d $f5, $t1
+ movgr2fr.d $f6, $t1
+ movgr2fr.d $f7, $t1
+ movgr2fr.d $f8, $t1
+ movgr2fr.d $f9, $t1
+ movgr2fr.d $f10, $t1
+ movgr2fr.d $f11, $t1
+ movgr2fr.d $f12, $t1
+ movgr2fr.d $f13, $t1
+ movgr2fr.d $f14, $t1
+ movgr2fr.d $f15, $t1
+ movgr2fr.d $f16, $t1
+ movgr2fr.d $f17, $t1
+ movgr2fr.d $f18, $t1
+ movgr2fr.d $f19, $t1
+ movgr2fr.d $f20, $t1
+ movgr2fr.d $f21, $t1
+ movgr2fr.d $f22, $t1
+ movgr2fr.d $f23, $t1
+ movgr2fr.d $f24, $t1
+ movgr2fr.d $f25, $t1
+ movgr2fr.d $f26, $t1
+ movgr2fr.d $f27, $t1
+ movgr2fr.d $f28, $t1
+ movgr2fr.d $f29, $t1
+ movgr2fr.d $f30, $t1
+ movgr2fr.d $f31, $t1
+
+ jirl $zero, $ra, 0
+ .end
--
2.27.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [edk2-devel] [PATCH v1 03/19] MdePkg: Add LoongArch64 exception function set into BaseLib
2024-02-02 2:26 [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Chao Li
2024-02-02 2:27 ` [edk2-devel] [PATCH v1 01/19] MdePkg: Add the header file named Csr.h for LoongArch64 Chao Li
2024-02-02 2:27 ` [edk2-devel] [PATCH v1 02/19] MdePkg: Add LoongArch64 FPU function set into BaseCpuLib Chao Li
@ 2024-02-02 2:27 ` Chao Li
2024-02-02 2:27 ` [edk2-devel] [PATCH v1 04/19] MdePkg: Add LoongArch64 local interrupt " Chao Li
` (16 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Chao Li @ 2024-02-02 2:27 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu
Adding SetExceptionBaseAddress and SetTlbRebaseAddress functions
for LoongArch64.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Acked-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
---
MdePkg/Include/Library/BaseLib.h | 20 +++++++++
MdePkg/Library/BaseLib/BaseLib.inf | 1 +
.../BaseLib/LoongArch64/ExceptionBase.S | 41 +++++++++++++++++++
3 files changed, 62 insertions(+)
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/ExceptionBase.S
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index ca0d06c7f3..7117c4288f 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -287,6 +287,26 @@ typedef struct {
#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+/*
+ * Set the exception base address for LoongArch.
+ *
+ * @param ExceptionBaseAddress The exception base address, must be aligned greater than or qeual to 4K .
+ */
+VOID
+SetExceptionBaseAddress (
+ IN UINT64
+ );
+
+/*
+ * Set the TlbRebase address for LoongArch.
+ *
+ * @param TlbRebaseAddress The TlbRebase address, must be aligned greater than or qeual to 4K .
+ */
+VOID
+SetTlbRebaseAddress (
+ IN UINT64
+ );
+
#endif // defined (MDE_CPU_LOONGARCH64)
//
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 6b46949be3..22b38b59e7 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -420,6 +420,7 @@ [Sources.LOONGARCH64]
LoongArch64/CpuPause.S | GCC
LoongArch64/SetJumpLongJump.S | GCC
LoongArch64/SwitchStack.S | GCC
+ LoongArch64/ExceptionBase.S | GCC
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseLib/LoongArch64/ExceptionBase.S b/MdePkg/Library/BaseLib/LoongArch64/ExceptionBase.S
new file mode 100644
index 0000000000..b6e90a8f28
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/ExceptionBase.S
@@ -0,0 +1,41 @@
+#------------------------------------------------------------------------------
+#
+# LoongArch set exception base address operations
+#
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <Base.h>
+#include <Register/LoongArch64/Csr.h>
+
+ASM_GLOBAL ASM_PFX(SetExceptionBaseAddress)
+ASM_GLOBAL ASM_PFX(SetTlbRebaseAddress)
+
+#/**
+# Set the exception base address for LoongArch.
+#
+# @param ExceptionBaseAddress The exception base address, must be aligned greater than or qeual to 4K .
+#**/
+ASM_PFX(SetExceptionBaseAddress):
+ csrrd $t0, LOONGARCH_CSR_ECFG
+ li.d $t1, ~(BIT16 | BIT17 | BIT18)
+ and $t0, $t0, $t1
+ csrwr $t0, LOONGARCH_CSR_ECFG
+
+ move $t0, $a0
+ csrwr $t0, LOONGARCH_CSR_EBASE
+ jirl $zero, $ra, 0
+
+#/**
+# Set the TlbRebase address for LoongArch.
+#
+# @param TlbRebaseAddress The TlbRebase address, must be aligned greater than or qeual to 4K .
+#**/
+ASM_PFX(SetTlbRebaseAddress):
+ move $t0, $a0
+ csrwr $t0, LOONGARCH_CSR_TLBREBASE
+ jirl $zero, $ra, 0
+.end
--
2.27.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [edk2-devel] [PATCH v1 04/19] MdePkg: Add LoongArch64 local interrupt function set into BaseLib
2024-02-02 2:26 [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Chao Li
` (2 preceding siblings ...)
2024-02-02 2:27 ` [edk2-devel] [PATCH v1 03/19] MdePkg: Add LoongArch64 exception function set into BaseLib Chao Li
@ 2024-02-02 2:27 ` Chao Li
2024-02-02 2:27 ` [edk2-devel] [PATCH v1 05/19] MdePkg: Add LoongArch Cpucfg function Chao Li
` (15 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Chao Li @ 2024-02-02 2:27 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu
Adding LoongArch local interrupt function set, which is used to control
the opening or closing of the local interrupt when the global interrupt
is enabled.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Acked-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
---
MdePkg/Include/Library/BaseLib.h | 20 +++++++++++++++++
.../BaseLib/LoongArch64/DisableInterrupts.S | 22 ++++++++++++++-----
.../BaseLib/LoongArch64/EnableInterrupts.S | 22 ++++++++++++++-----
3 files changed, 54 insertions(+), 10 deletions(-)
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 7117c4288f..91322d2dfa 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -307,6 +307,26 @@ SetTlbRebaseAddress (
IN UINT64
);
+/**
+ Enables local CPU interrupts.
+
+ @param Needs to enable local interrupt bit.
+**/
+VOID
+EnableLocalInterrupts (
+ IN UINT16
+ );
+
+/**
+ Disables local CPU interrupts.
+
+ @param Needs to disable local interrupt bit.
+**/
+VOID
+DisableLocalInterrupts (
+ IN UINT16
+ );
+
#endif // defined (MDE_CPU_LOONGARCH64)
//
diff --git a/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S b/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S
index 0f228339af..8f9ee888b1 100644
--- a/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S
+++ b/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S
@@ -1,21 +1,33 @@
#------------------------------------------------------------------------------
#
-# LoongArch interrupt disable
+# LoongArch interrupt disable operations
#
-# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#------------------------------------------------------------------------------
+#include <Base.h>
+#include <Register/LoongArch64/Csr.h>
+
+ASM_GLOBAL ASM_PFX(DisableLocalInterrupts)
ASM_GLOBAL ASM_PFX(DisableInterrupts)
#/**
-# Disables CPU interrupts.
+# Disables local CPU interrupts.
+#
+# @param Needs to disable local interrupt bit.
#**/
+ASM_PFX(DisableLocalInterrupts):
+ csrxchg $zero, $a0, LOONGARCH_CSR_ECFG
+ jirl $zero, $ra, 0
+#/**
+# Disables global CPU interrupts.
+#**/
ASM_PFX(DisableInterrupts):
- li.w $t0, 0x4
- csrxchg $zero, $t0, 0x0
+ li.w $t0, BIT2
+ csrxchg $zero, $t0, LOONGARCH_CSR_CRMD
jirl $zero, $ra, 0
.end
diff --git a/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S b/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S
index 3c34fb2cdd..126c7b49b3 100644
--- a/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S
+++ b/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S
@@ -1,21 +1,33 @@
#------------------------------------------------------------------------------
#
-# LoongArch interrupt enable
+# LoongArch interrupt enable operations
#
-# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#------------------------------------------------------------------------------
+#include <Base.h>
+#include <Register/LoongArch64/Csr.h>
+
+ASM_GLOBAL ASM_PFX(EnableLocalInterrupts)
ASM_GLOBAL ASM_PFX(EnableInterrupts)
#/**
-# Enables CPU interrupts.
+# Enables local CPU interrupts.
+#
+# @param Needs to enable local interrupt bit.
#**/
+ASM_PFX(EnableLocalInterrupts):
+ csrxchg $a0, $a0, LOONGARCH_CSR_ECFG
+ jirl $zero, $ra, 0
+#/**
+# Enables global CPU interrupts.
+#**/
ASM_PFX(EnableInterrupts):
- li.w $t0, 0x4
- csrxchg $t0, $t0, 0x0
+ li.w $t0, BIT2
+ csrxchg $t0, $t0, LOONGARCH_CSR_CRMD
jirl $zero, $ra, 0
.end
--
2.27.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [edk2-devel] [PATCH v1 05/19] MdePkg: Add LoongArch Cpucfg function
2024-02-02 2:26 [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Chao Li
` (3 preceding siblings ...)
2024-02-02 2:27 ` [edk2-devel] [PATCH v1 04/19] MdePkg: Add LoongArch64 local interrupt " Chao Li
@ 2024-02-02 2:27 ` Chao Li
2024-02-02 2:27 ` [edk2-devel] [PATCH v1 06/19] MdePkg: Add read stable counter operation for LoongArch Chao Li
` (14 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Chao Li @ 2024-02-02 2:27 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu
Add LoongArch AsmCpucfg function and Cpucfg definitions.
Also added Include/Register/LoongArch64/Cpucfg.h to IgnoreFiles of
EccCheck.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Acked-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
---
MdePkg/Include/Library/BaseLib.h | 12 +
MdePkg/Include/Register/LoongArch64/Cpucfg.h | 565 +++++++++++++++++++
MdePkg/Library/BaseLib/BaseLib.inf | 1 +
MdePkg/Library/BaseLib/LoongArch64/Cpucfg.S | 26 +
MdePkg/MdePkg.ci.yaml | 3 +-
5 files changed, 606 insertions(+), 1 deletion(-)
create mode 100644 MdePkg/Include/Register/LoongArch64/Cpucfg.h
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/Cpucfg.S
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 91322d2dfa..d64e406b7c 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -327,6 +327,18 @@ DisableLocalInterrupts (
IN UINT16
);
+/**
+ Read CPUCFG register.
+
+ @param Index Specifies the register number of the CPUCFG to read the data.
+ @param Data A pointer to the variable used to store the CPUCFG register value.
+**/
+VOID
+AsmCpucfg (
+ IN UINT32 Index,
+ OUT UINT32 *Data
+ );
+
#endif // defined (MDE_CPU_LOONGARCH64)
//
diff --git a/MdePkg/Include/Register/LoongArch64/Cpucfg.h b/MdePkg/Include/Register/LoongArch64/Cpucfg.h
new file mode 100644
index 0000000000..570748b194
--- /dev/null
+++ b/MdePkg/Include/Register/LoongArch64/Cpucfg.h
@@ -0,0 +1,565 @@
+/** @file
+ CPUCFG definitions.
+
+ Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef CPUCFG_H_
+#define CPUCFG_H_
+
+/**
+ CPUCFG REG0 Information
+
+ @code
+ CPUCFG_REG0_INFO_DATA
+ **/
+#define CPUCFG_REG0_INFO 0x0
+
+/**
+ CPUCFG REG0 Information returned data.
+ #CPUCFG_REG0_INFO
+ **/
+typedef union {
+ struct {
+ ///
+ /// [Bit 31:0] Processor Identity.
+ ///
+ UINT32 PRID : 32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUCFG_REG0_INFO_DATA;
+
+/**
+ CPUCFG REG1 Information
+
+ @code
+ CPUCFG_REG1_INFO_DATA
+ **/
+#define CPUCFG_REG1_INFO 0x1
+
+/**
+ CPUCFG REG1 Information returned data.
+ #CPUCFG_REG1_INFO
+ **/
+typedef union {
+ struct {
+ ///
+ /// [Bit 1:0] Architecture:
+ /// 2'b00 indicates the implementation of simplified LoongAarch32;
+ /// 2'b01 indicates the implementation of LoongAarch32;
+ /// 2'b10 indicates the implementation of LoongAarch64;
+ /// 2'b11 reserved;
+ ///
+ UINT32 ARCH : 2;
+ ///
+ /// [Bit 2] Paging mapping mode. A value of 1 indicates the processor MMU supports
+ /// page mapping mode.
+ ///
+ UINT32 PGMMU : 1;
+ ///
+ /// [Bit 3] A value of 1 indicates the processor supports the IOCSR instruction.
+ ///
+ UINT32 IOCSR : 1;
+ ///
+ /// [Bit 11:4] Physical address bits. The supported physical address bits PALEN value
+ /// minus 1.
+ ///
+ UINT32 PALEN : 8;
+ ///
+ /// [Bit 19:12] Virtual address bits. The supported virtual address bits VALEN value
+ /// minus 1.
+ ///
+ UINT32 VALEN : 8;
+ ///
+ /// [Bit 20] Non-aligned Memory Access. A value of 1 indicates the processor supports
+ /// non-aligned memory access.
+ ///
+ UINT32 UAL : 1;
+ ///
+ /// [Bit 21] Page Read Inhibit. A value of 1 indicates the processor supports page
+ /// attribute of "Read Inhibit".
+ ///
+ UINT32 RI : 1;
+ ///
+ /// [Bit 22] Page Execution Protection. A value of 1 indicates the processor supports
+ /// page attribute of "Execution Protection".
+ ///
+ UINT32 EP : 1;
+ ///
+ /// [Bit 23] A value of 1 indicates the processor supports for page attributes of RPLV.
+ ///
+ UINT32 RPLV : 1;
+ ///
+ /// [Bit 24] Huge Page. A value of 1 indicates the processor supports page attribute
+ /// of huge page.
+ ///
+ UINT32 HP : 1;
+ ///
+ /// [Bit 25] A value of 1 indicates that the string of processor product information
+ /// is recorded at address 0 of the IOCSR access space.
+ ///
+ UINT32 IOCSR_BRD : 1;
+ ///
+ /// [Bit 26] A value of 1 indicates that the external interrupt uses the message
+ /// interrupt mode, otherwise it is the level interrupt line mode.
+ ///
+ UINT32 MSG_INT : 1;
+ ///
+ /// [Bit 31:27] Reserved.
+ ///
+ UINT32 Reserved : 5;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUCFG_REG1_INFO_DATA;
+
+/**
+ CPUCFG REG2 Information
+
+ @code
+ CPUCFG_REG2_INFO_DATA
+ **/
+#define CPUCFG_REG2_INFO 0x2
+
+/**
+ CPUCFG REG2 Information returned data.
+ #CPUCFG_REG2_INFO
+ **/
+typedef union {
+ struct {
+ ///
+ /// [Bit 0] Basic Floating-Point. A value of 1 indicates the processor supports basic
+ /// floating-point instructions.
+ ///
+ UINT32 FP : 1;
+ ///
+ /// [Bit 1] Sigle-Precision. A value of 1 indicates the processor supports sigle-precision
+ /// floating-point numbers.
+ ///
+ UINT32 FP_SP : 1;
+ ///
+ /// [Bit 2] Double-Precision. A value of 1 indicates the processor supports double-precision
+ /// floating-point numbers.
+ ///
+ UINT32 FP_DP : 1;
+ ///
+ /// [Bit 5:3] The version number of the floating-point arithmetic standard. 1 is the initial
+ /// version number, indicating that it is compatible with the IEEE 754-2008 standard.
+ ///
+ UINT32 FP_ver : 3;
+ ///
+ /// [Bit 6] 128-bit Vector Extension. A value of 1 indicates the processor supports 128-bit
+ /// vector extension.
+ ///
+ UINT32 LSX : 1;
+ ///
+ /// [Bit 7] 256-bit Vector Extension. A value of 1 indicates the processor supports 256-bit
+ /// vector extension.
+ ///
+ UINT32 LASX : 1;
+ ///
+ /// [Bit 8] Complex Vector Operation Instructions. A value of 1 indicates the processor supports
+ /// complex vector operation instructions.
+ ///
+ UINT32 COMPLEX : 1;
+ ///
+ /// [Bit 9] Encryption And Decryption Vector Instructions. A value of 1 indicates the processor
+ /// supports encryption and decryption vector instructions.
+ ///
+ UINT32 CRYPTO : 1;
+ ///
+ /// [Bit 10] Virtualization Expansion. A value of 1 indicates the processor supports
+ /// virtualization expansion.
+ ///
+ UINT32 LVZ : 1;
+ ///
+ /// [Bit 13:11] The version number of the virtualization hardware acceleration specification.
+ /// 1 is the initial version number.
+ ///
+ UINT32 LVZ_ver : 3;
+ ///
+ /// [Bit 14] Constant Frequency Counter And Timer. A value of 1 indicates the processor supports
+ /// constant frequency counter and timer.
+ ///
+ UINT32 LLFTP : 1;
+ ///
+ /// [Bit 17:15] Constant frequency counter and timer version number. 1 is the initial version.
+ ///
+ UINT32 LLTP_ver : 3;
+ ///
+ /// [Bit 18] X86 Binary Translation Extension. A value of 1 indicates the processor supports
+ /// X86 binary translation extension.
+ ///
+ UINT32 LBT_X86 : 1;
+ ///
+ /// [Bit 19] ARM Binary Translation Extension. A value of 1 indicates the processor supports
+ /// ARM binary translation extension.
+ ///
+ UINT32 LBT_ARM : 1;
+ ///
+ /// [Bit 20] MIPS Binary Translation Extension. A value of 1 indicates the processor supports
+ /// MIPS binary translation extension.
+ ///
+ UINT32 LBT_MIPS : 1;
+ ///
+ /// [Bit 21] Software Page Table Walking Instruction. A value of 1 indicates the processor
+ /// supports software page table walking instruction.
+ ///
+ UINT32 LSPW : 1;
+ ///
+ /// [Bit 22] Atomic Memory Access Instruction. A value of 1 indicates the processor supports
+ /// AM* atomic memory access instruction.
+ ///
+ UINT32 LAM : 1;
+ ///
+ /// [Bit 31:23] Reserved.
+ ///
+ UINT32 Reserved : 9;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUCFG_REG2_INFO_DATA;
+
+/**
+ CPUCFG REG3 Information
+
+ @code
+ CPUCFG_REG3_INFO_DATA
+ **/
+#define CPUCFG_REG3_INFO 0x3
+
+/**
+ CPUCFG REG3 Information returned data.
+ #CPUCFG_REG3_INFO
+ **/
+typedef union {
+ struct {
+ ///
+ /// [Bit 0] Hardware Cache Coherent DMA. A value of 1 indicates the processor supports
+ /// hardware cache coherent DMA.
+ ///
+ UINT32 CCDMA : 1;
+ ///
+ /// [Bit 1] Store Fill Buffer. A value of 1 indicates the processor supports store fill
+ /// buffer (SFB).
+ ///
+ UINT32 SFB : 1;
+ ///
+ /// [Bit 2] Uncache Accelerate. A value of 1 indicates the processor supports uncache
+ /// accelerate.
+ ///
+ UINT32 UCACC : 1;
+ ///
+ /// [Bit 3] A value of 1 indicates the processor supports LL instruction to fetch exclusive
+ /// block function.
+ ///
+ UINT32 LLEXC : 1;
+ ///
+ /// [Bit 4] A value of 1 indicates the processor supports random delay function after SC
+ /// instruction.
+ ///
+ UINT32 SCDLY : 1;
+ ///
+ /// [Bit 5] A value of 1 indicates the processor supports LL automatic with dbar function.
+ ///
+ UINT32 LLDBAR : 1;
+ ///
+ /// [Bit 6] A value of 1 indicates the processor supports the hardware maintains the
+ /// consistency between ITLB and TLB.
+ ///
+ UINT32 ITLBT : 1;
+ ///
+ /// [Bit 7] A value of 1 indicates the processor supports the hardware maintains the data
+ /// consistency between ICache and DCache in one processor core.
+ ///
+ UINT32 ICACHET : 1;
+ ///
+ /// [Bit 10:8] The maximum number of directory levels supported by the page walk instruction.
+ ///
+ UINT32 SPW_LVL : 3;
+ ///
+ /// [Bit 11] A value of 1 indicates the processor supports the page walk instruction fills
+ /// the TLB in half when it encounters a large page.
+ ///
+ UINT32 SPW_HP_HF : 1;
+ ///
+ /// [Bit 12] Virtual Address Range. A value of 1 indicates the processor supports the software
+ /// configuration can be used to shorten the virtual address range.
+ ///
+ UINT32 RVA : 1;
+ ///
+ /// [Bit 16:13] The maximum configurable virtual address is shortened by -1.
+ ///
+ UINT32 RVAMAX_1 : 4;
+ ///
+ /// [Bit 31:17] Reserved.
+ ///
+ UINT32 Reserved : 15;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUCFG_REG3_INFO_DATA;
+
+/**
+ CPUCFG REG4 Information
+
+ @code
+ CPUCFG_REG4_INFO_DATA
+ **/
+#define CPUCFG_REG4_INFO 0x4
+
+/**
+ CPUCFG REG4 Information returned data.
+ #CPUCFG_REG4_INFO
+ **/
+typedef union {
+ struct {
+ ///
+ /// [Bit 31:0] Constant frequency timer and the crystal frequency corresponding to the clock
+ /// used by the timer.
+ ///
+ UINT32 CC_FREQ : 32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUCFG_REG4_INFO_DATA;
+
+/**
+ CPUCFG REG5 Information
+
+ @code
+ CPUCFG_REG5_INFO_DATA
+ **/
+#define CPUCFG_REG5_INFO 0x5
+
+/**
+ CPUCFG REG5 Information returned data.
+ #CPUCFG_REG5_INFO
+ **/
+typedef union {
+ struct {
+ ///
+ /// [Bit 15:0] Constant frequency timer and the corresponding multiplication factor of the
+ /// clock used by the timer.
+ ///
+ UINT32 CC_MUL : 16;
+ ///
+ /// [Bit 31:16] Constant frequency timer and the division coefficient corresponding to the
+ /// clock used by the timer
+ ///
+ UINT32 CC_DIV : 16;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUCFG_REG5_INFO_DATA;
+
+/**
+ CPUCFG REG6 Information
+
+ @code
+ CPUCFG_REG6_INFO_DATA
+ **/
+#define CPUCFG_REG6_INFO 0x6
+
+/**
+ CPUCFG REG6 Information returned data.
+ #CPUCFG_REG6_INFO
+ **/
+typedef union {
+ struct {
+ ///
+ /// [Bit 0] Performance Counter. A value of 1 indicates the processor supports performance
+ /// counter.
+ ///
+ UINT32 PMP : 1;
+ ///
+ /// [Bit 3:1] In the performance monitor, the architecture defines the version number of the
+ /// event, and 1 is the initial version
+ ///
+ UINT32 PMVER : 3;
+ ///
+ /// [Bit 7:4] Number of performance monitors minus 1.
+ ///
+ UINT32 PMNUM : 4;
+ ///
+ /// [Bit 13:8] Number of bits of a performance monitor minus 1.
+ ///
+ UINT32 PMBITS : 6;
+ ///
+ /// [Bit 14] A value of 1 indicates the processor supports reading performance counter in user mode.
+ ///
+ UINT32 UPM : 1;
+ ///
+ /// [Bit 31:15] Reserved.
+ ///
+ UINT32 Reserved : 17;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUCFG_REG6_INFO_DATA;
+
+/**
+ CPUCFG REG16 Information
+
+ @code
+ CPUCFG_REG16_INFO_DATA
+ **/
+#define CPUCFG_REG16_INFO 0x10
+
+/**
+ CPUCFG REG16 Information returned data.
+ #CPUCFG_REG16_INFO
+ **/
+typedef union {
+ struct {
+ ///
+ /// [Bit 0] A value of 1 indicates the processor has a first-level instruction cache
+ /// or a first-level unified cache
+ ///
+ UINT32 L1_IU_Present : 1;
+ ///
+ /// [Bit 1] A value of 1 indicates that the cache shown by L1 IU_Present is the
+ /// unified cache.
+ ///
+ UINT32 L1_IU_Unify : 1;
+ ///
+ /// [Bit 2] A value of 1 indicates the processor has a first-level data cache.
+ ///
+ UINT32 L1_D_Present : 1;
+ ///
+ /// [Bit 3] A value of 1 indicates the processor has a second-level instruction cache
+ /// or a second-level unified cache.
+ ///
+ UINT32 L2_IU_Present : 1;
+ ///
+ /// [Bit 4] A value of 1 indicates that the cache shown by L2 IU_Present is the
+ /// unified cache.
+ ///
+ UINT32 L2_IU_Unify : 1;
+ ///
+ /// [Bit 5] A value of 1 indicates that the cache shown by L2 IU_Present is private
+ /// to each core.
+ ///
+ UINT32 L2_IU_Private : 1;
+ ///
+ /// [Bit 6] A value of 1 indicates that the cache shown by L2 IU_Present has an inclusive
+ /// relationship to the lower levels (L1).
+ ///
+ UINT32 L2_IU_Inclusive : 1;
+ ///
+ /// [Bit 7] A value of 1 indicates the processor has a second-level data cache.
+ ///
+ UINT32 L2_D_Present : 1;
+ ///
+ /// [Bit 8] A value of 1 indicates that the second-level data cache is private to each core.
+ ///
+ UINT32 L2_D_Private : 1;
+ ///
+ /// [Bit 9] A value of 1 indicates that the second-level data cache has a containment
+ /// relationship to the lower level (L1).
+ ///
+ UINT32 L2_D_Inclusive : 1;
+ ///
+ /// [Bit 10] A value of 1 indicates the processor has a three-level instruction cache
+ /// or a second-level unified Cache.
+ ///
+ UINT32 L3_IU_Present : 1;
+ ///
+ /// [Bit 11] A value of 1 indicates that the cache shown by L3 IU_Present is the
+ /// unified cache.
+ ///
+ UINT32 L3_IU_Unify : 1;
+ ///
+ /// [Bit 12] A value of 1 indicates that the cache shown by L3 IU_Present is private
+ /// to each core.
+ ///
+ UINT32 L3_IU_Private : 1;
+ ///
+ /// [Bit 13] A value of 1 indicates that the cache shown by L3 IU_Present has an inclusive
+ /// relationship to the lower levels (L1 and L2).
+ ///
+ UINT32 L3_IU_Inclusive : 1;
+ ///
+ /// [Bit 14] A value of 1 indicates the processor has a three-level data cache.
+ ///
+ UINT32 L3_D_Present : 1;
+ ///
+ /// [Bit 15] A value of 1 indicates that the three-level data cache is private to each core.
+ ///
+ UINT32 L3_D_Private : 1;
+ ///
+ /// [Bit 16] A value of 1 indicates that the three-level data cache has a containment
+ /// relationship to the lower level (L1 and L2).
+ ///
+ UINT32 L3_D_Inclusive : 1;
+ ///
+ /// [Bit 31:17] Reserved.
+ ///
+ UINT32 Reserved : 15;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUCFG_REG16_INFO_DATA;
+
+/**
+ CPUCFG REG17, REG18, REG19 and REG20 Information
+
+ @code
+ CPUCFG_CACHE_INFO_DATA
+ **/
+#define CPUCFG_REG17_INFO 0x11 /// L1 unified cache.
+#define CPUCFG_REG18_INFO 0x12 /// L1 data cache.
+#define CPUCFG_REG19_INFO 0x13 /// L2 unified cache.
+#define CPUCFG_REG20_INFO 0x14 /// L3 unified cache.
+
+/**
+ CPUCFG CACHE Information returned data.
+ #CPUCFG_REG17_INFO
+ #CPUCFG_REG18_INFO
+ #CPUCFG_REG19_INFO
+ #CPUCFG_REG20_INFO
+ **/
+typedef union {
+ struct {
+ ///
+ /// [Bit 15:0] Number of channels minus 1.
+ ///
+ UINT32 Way_1 : 16;
+ ///
+ /// [Bit 23:16] Log2 (number of cache rows per channel).
+ ///
+ UINT32 Index_log2 : 8;
+ ///
+ /// [Bit 30:24] Log2 (cache row bytes).
+ ///
+ UINT32 Linesize_log2 : 7;
+ ///
+ /// [Bit 31] Reserved.
+ ///
+ UINT32 Reserved : 1;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUCFG_CACHE_INFO_DATA;
+#endif
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 22b38b59e7..2f1e3b3d91 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -421,6 +421,7 @@ [Sources.LOONGARCH64]
LoongArch64/SetJumpLongJump.S | GCC
LoongArch64/SwitchStack.S | GCC
LoongArch64/ExceptionBase.S | GCC
+ LoongArch64/Cpucfg.S | GCC
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseLib/LoongArch64/Cpucfg.S b/MdePkg/Library/BaseLib/LoongArch64/Cpucfg.S
new file mode 100644
index 0000000000..8b3f842f9e
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/Cpucfg.S
@@ -0,0 +1,26 @@
+#------------------------------------------------------------------------------
+#
+# AsmCpucfg for LoongArch
+#
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(AsmCpucfg)
+
+#/**
+# Read CPUCFG register.
+#
+# @param a0 Specifies the register number of the CPUCFG to read the data.
+# @param a1 Pointer to the variable used to store the CPUCFG register value.
+#
+#**/
+
+ASM_PFX(AsmCpucfg):
+ cpucfg $t0, $a0
+ stptr.d $t0, $a1, 0
+
+ jirl $zero, $ra, 0
+ .end
diff --git a/MdePkg/MdePkg.ci.yaml b/MdePkg/MdePkg.ci.yaml
index 1d3d8327b1..f2d81af080 100644
--- a/MdePkg/MdePkg.ci.yaml
+++ b/MdePkg/MdePkg.ci.yaml
@@ -80,7 +80,8 @@
"Include/Register/Amd/SmramSaveStateMap.h",
"Test/UnitTest/Library/DevicePathLib/TestDevicePathLib.c",
"Test/UnitTest/Library/DevicePathLib/TestDevicePathLib.h",
- "Test/UnitTest/Library/DevicePathLib/TestDevicePathStringConversions.c"
+ "Test/UnitTest/Library/DevicePathLib/TestDevicePathStringConversions.c",
+ "Include/Register/LoongArch64/Cpucfg.h"
]
},
## options defined ci/Plugin/CompilerPlugin
--
2.27.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [edk2-devel] [PATCH v1 06/19] MdePkg: Add read stable counter operation for LoongArch
2024-02-02 2:26 [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Chao Li
` (4 preceding siblings ...)
2024-02-02 2:27 ` [edk2-devel] [PATCH v1 05/19] MdePkg: Add LoongArch Cpucfg function Chao Li
@ 2024-02-02 2:27 ` Chao Li
2024-02-02 2:27 ` [edk2-devel] [PATCH v1 07/19] MdePkg: Add CSR " Chao Li
` (13 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Chao Li @ 2024-02-02 2:27 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu
Add LoongArch gets stable counter ASM function.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Acked-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
---
MdePkg/Include/Library/BaseLib.h | 12 ++++++++++
MdePkg/Library/BaseLib/BaseLib.inf | 1 +
.../BaseLib/LoongArch64/ReadStableCounter.S | 24 +++++++++++++++++++
3 files changed, 37 insertions(+)
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/ReadStableCounter.S
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index d64e406b7c..29009adbc9 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -339,6 +339,18 @@ AsmCpucfg (
OUT UINT32 *Data
);
+/**
+ Gets the timer count value.
+
+ @param[] VOID
+ @retval timer count value.
+
+**/
+UINTN
+AsmReadStableCounter (
+ VOID
+ );
+
#endif // defined (MDE_CPU_LOONGARCH64)
//
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 2f1e3b3d91..1dad587b0c 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -422,6 +422,7 @@ [Sources.LOONGARCH64]
LoongArch64/SwitchStack.S | GCC
LoongArch64/ExceptionBase.S | GCC
LoongArch64/Cpucfg.S | GCC
+ LoongArch64/ReadStableCounter.S | GCC
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseLib/LoongArch64/ReadStableCounter.S b/MdePkg/Library/BaseLib/LoongArch64/ReadStableCounter.S
new file mode 100644
index 0000000000..aa74ff603e
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/ReadStableCounter.S
@@ -0,0 +1,24 @@
+#------------------------------------------------------------------------------
+#
+# LoongArch Read Stable Counter
+#
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(AsmReadStableCounter)
+
+#/**
+# Gets the timer count value.
+#
+# @param[] VOID
+# @retval timer count value.
+#
+#**/
+
+ASM_PFX(AsmReadStableCounter):
+ rdtime.d $a0, $zero
+ jirl $zero, $ra, 0
+ .end
--
2.27.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [edk2-devel] [PATCH v1 07/19] MdePkg: Add CSR operation for LoongArch
2024-02-02 2:26 [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Chao Li
` (5 preceding siblings ...)
2024-02-02 2:27 ` [edk2-devel] [PATCH v1 06/19] MdePkg: Add read stable counter operation for LoongArch Chao Li
@ 2024-02-02 2:27 ` Chao Li
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 08/19] MdePkg: Add IOCSR " Chao Li
` (12 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Chao Li @ 2024-02-02 2:27 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu, Bibo Mao
Add CsrRead, CsrWrite and CsrXChg functions for LoongArch, and use them
to operate the CSR register of LoongArch architecture.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Co-authored-by: Bibo Mao <maobibo@loongson.cn>
Acked-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
---
MdePkg/Include/Library/BaseLib.h | 45 +++
MdePkg/Library/BaseLib/BaseLib.inf | 2 +
MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S | 422 ++++++++++++++++++++
MdePkg/Library/BaseLib/LoongArch64/Csr.c | 81 ++++
4 files changed, 550 insertions(+)
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/Csr.c
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 29009adbc9..4e97368ae2 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -351,6 +351,51 @@ AsmReadStableCounter (
VOID
);
+/**
+ CSR read operation.
+
+ @param[in] Select CSR read instruction select values.
+
+ @return The return value of csrrd instruction, return -1 means no CSR instruction
+ is found.
+**/
+UINTN
+CsrRead (
+ IN UINT16 Select
+ );
+
+/**
+ CSR write operation.
+
+ @param[in] Select CSR write instruction select values.
+ @param[in] Value The csrwr will write the value.
+
+ @return The return value of csrwr instruction, that is, store the old value of
+ the register, return -1 means no CSR instruction is found.
+**/
+UINTN
+CsrWrite (
+ IN UINT16 Select,
+ IN UINTN Value
+ );
+
+/**
+ CSR exchange operation.
+
+ @param[in] Select CSR exchange instruction select values.
+ @param[in] Value The csrxchg will write the value.
+ @param[in] Mask The csrxchg mask value.
+
+ @return The return value of csrxchg instruction, that is, store the old value of
+ the register, return -1 means no CSR instruction is found.
+**/
+UINTN
+CsrXChg (
+ IN UINT16 Select,
+ IN UINTN Value,
+ IN UINTN Mask
+ );
+
#endif // defined (MDE_CPU_LOONGARCH64)
//
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 1dad587b0c..7c46306883 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -410,7 +410,9 @@ [Sources.RISCV64]
[Sources.LOONGARCH64]
Math64.c
Unaligned.c
+ LoongArch64/Csr.c
LoongArch64/InternalSwitchStack.c
+ LoongArch64/AsmCsr.S | GCC
LoongArch64/GetInterruptState.S | GCC
LoongArch64/EnableInterrupts.S | GCC
LoongArch64/DisableInterrupts.S | GCC
diff --git a/MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S b/MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S
new file mode 100644
index 0000000000..3a879411f5
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S
@@ -0,0 +1,422 @@
+#------------------------------------------------------------------------------
+#
+# LoongArch ASM CSR operation functions
+#
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <Register/LoongArch64/Csr.h>
+
+ASM_GLOBAL ASM_PFX (AsmCsrRead)
+ASM_GLOBAL ASM_PFX (AsmCsrWrite)
+ASM_GLOBAL ASM_PFX (AsmCsrXChg)
+
+.macro AsmCsrRd Sel
+ csrrd $a0, \Sel
+ jirl $zero, $ra, 0
+.endm
+
+.macro AsmCsrWr Sel
+ csrwr $a0, \Sel
+ jirl $zero, $ra, 0
+.endm
+
+.macro AsmCsrXChange Sel
+ csrxchg $a0, $a1, \Sel
+ jirl $zero, $ra, 0
+.endm
+
+ASM_PFX(AsmCsrRead):
+ blt $a0, $zero, ReadSelNumErr
+ li.w $t0, LOONGARCH_CSR_EBASE
+ bltu $t0, $a0, TlbCsrRd
+
+BasicCsrRd:
+ la.pcrel $t0, BasicCsrRead
+ alsl.d $t0, $a0, $t0, 3
+ jirl $zero, $t0, 0
+
+TlbCsrRd:
+ li.w $t0, LOONGARCH_CSR_TLBIDX
+ bltu $a0, $t0, ReadSelNumErr
+ li.w $t0, LOONGARCH_CSR_RVACFG
+ bltu $t0, $a0, CfgCsrRd
+ la.pcrel $t0, TlbCsrRead
+ addi.w $t1, $a0, -LOONGARCH_CSR_TLBIDX
+ alsl.d $t0, $t1, $t0, 3
+ jirl $zero, $t0, 0
+
+CfgCsrRd:
+ li.w $t0, LOONGARCH_CSR_CPUNUM
+ bltu $a0, $t0, ReadSelNumErr
+ li.w $t0, LOONGARCH_CSR_PRCFG3
+ bltu $t0, $a0, KcsCsrRd
+ la.pcrel $t0, CfgCsrRead
+ addi.w $t1, $a0, -LOONGARCH_CSR_CPUNUM
+ alsl.d $t0, $t1, $t0, 3
+ jirl $zero, $t0, 0
+
+KcsCsrRd:
+ li.w $t0, LOONGARCH_CSR_KS0
+ bltu $a0, $t0, ReadSelNumErr
+ li.w $t0, LOONGARCH_CSR_KS8
+ bltu $t0, $a0, StableTimerCsrRd
+ la.pcrel $t0, KcsCsrRead
+ addi.w $t1, $a0, -LOONGARCH_CSR_KS0
+ alsl.d $t0, $t1, $t0, 3
+ jirl $zero, $t0, 0
+
+StableTimerCsrRd:
+ li.w $t0, LOONGARCH_CSR_TMID
+ bltu $a0, $t0, ReadSelNumErr
+ li.w $t0, LOONGARCH_CSR_TINTCLR
+ bltu $t0, $a0, TlbRefillCsrRd
+ la.pcrel $t0, StableTimerCsrRead
+ addi.w $t1, $a0, -LOONGARCH_CSR_TMID
+ alsl.d $t0, $t1, $t0, 3
+ jirl $zero, $t0, 0
+
+TlbRefillCsrRd:
+ li.w $t0, LOONGARCH_CSR_TLBREBASE
+ bltu $a0, $t0, ReadSelNumErr
+ li.w $t0, LOONGARCH_CSR_TLBREHI
+ bltu $t0, $a0, DirMapCsrRd
+ la.pcrel $t0, TlbRefillCsrRead
+ addi.w $t1, $a0, -LOONGARCH_CSR_TLBREBASE
+ alsl.d $t0, $t1, $t0, 3
+ jirl $zero, $t0, 0
+
+DirMapCsrRd:
+ li.w $t0, LOONGARCH_CSR_DMWIN0
+ bltu $a0, $t0, ReadSelNumErr
+ li.w $t0, LOONGARCH_CSR_DMWIN3
+ bltu $t0, $a0, ReadSelNumErr
+ la.pcrel $t0, DirMapCsrRead
+ addi.w $t1, $a0, -LOONGARCH_CSR_DMWIN0
+ alsl.d $t0, $t1, $t0, 3
+ jirl $zero, $t0, 0
+
+ReadSelNumErr:
+ addi.d $a0, $zero, -1
+ jirl $zero, $ra, 0
+
+BasicCsrRead:
+ CsrSel = LOONGARCH_CSR_CRMD
+ .rept LOONGARCH_CSR_EBASE - LOONGARCH_CSR_CRMD + 1
+ AsmCsrRd CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+TlbCsrRead:
+ CsrSel = LOONGARCH_CSR_TLBIDX
+ .rept LOONGARCH_CSR_RVACFG - LOONGARCH_CSR_TLBIDX + 1
+ AsmCsrRd CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+CfgCsrRead:
+ CsrSel = LOONGARCH_CSR_CPUNUM
+ .rept LOONGARCH_CSR_PRCFG3 - LOONGARCH_CSR_CPUNUM + 1
+ AsmCsrRd CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+KcsCsrRead:
+ CsrSel = LOONGARCH_CSR_KS0
+ .rept LOONGARCH_CSR_KS8 - LOONGARCH_CSR_KS0 + 1
+ AsmCsrRd CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+StableTimerCsrRead:
+ CsrSel = LOONGARCH_CSR_TMID
+ .rept LOONGARCH_CSR_TINTCLR - LOONGARCH_CSR_TMID + 1
+ AsmCsrRd CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+TlbRefillCsrRead:
+ CsrSel = LOONGARCH_CSR_TLBREBASE
+ .rept LOONGARCH_CSR_TLBREHI - LOONGARCH_CSR_TLBREBASE + 1
+ AsmCsrRd CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+DirMapCsrRead:
+ CsrSel = LOONGARCH_CSR_DMWIN0
+ .rept LOONGARCH_CSR_DMWIN3 - LOONGARCH_CSR_DMWIN0 + 1
+ AsmCsrRd CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+ASM_PFX(AsmCsrWrite):
+ blt $a0, $zero, WriteSelNumErr
+ li.w $t0, LOONGARCH_CSR_EBASE
+ bltu $t0, $a0, TlbCsrWr
+
+BasicCsrWr:
+ la.pcrel $t0, BasicCsrWrite
+ alsl.d $t0, $a0, $t0, 3
+ move $a0, $a1
+ jirl $zero, $t0, 0
+
+TlbCsrWr:
+ li.w $t0, LOONGARCH_CSR_TLBIDX
+ bltu $a0, $t0, WriteSelNumErr
+ li.w $t0, LOONGARCH_CSR_RVACFG
+ bltu $t0, $a0, CfgCsrWr
+ la.pcrel $t0, TlbCsrWrite
+ addi.w $t1, $a0, -LOONGARCH_CSR_TLBIDX
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ jirl $zero, $t0, 0
+
+CfgCsrWr:
+ li.w $t0, LOONGARCH_CSR_CPUNUM
+ bltu $a0, $t0, WriteSelNumErr
+ li.w $t0, LOONGARCH_CSR_PRCFG3
+ bltu $t0, $a0, KcsCsrWr
+ la.pcrel $t0, CfgCsrWrite
+ addi.w $t1, $a0, -LOONGARCH_CSR_CPUNUM
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ jirl $zero, $t0, 0
+
+KcsCsrWr:
+ li.w $t0, LOONGARCH_CSR_KS0
+ bltu $a0, $t0, WriteSelNumErr
+ li.w $t0, LOONGARCH_CSR_KS8
+ bltu $t0, $a0, StableTimerCsrWr
+ la.pcrel $t0, KcsCsrWrite
+ addi.w $t1, $a0, -LOONGARCH_CSR_KS0
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ jirl $zero, $t0, 0
+
+StableTimerCsrWr:
+ li.w $t0, LOONGARCH_CSR_TMID
+ bltu $a0, $t0, WriteSelNumErr
+ li.w $t0, LOONGARCH_CSR_TINTCLR
+ bltu $t0, $a0, TlbRefillCsrWr
+ la.pcrel $t0, StableTimerCsrWrite
+ addi.w $t1, $a0, -LOONGARCH_CSR_TMID
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ jirl $zero, $t0, 0
+
+TlbRefillCsrWr:
+ li.w $t0, LOONGARCH_CSR_TLBREBASE
+ bltu $a0, $t0, WriteSelNumErr
+ li.w $t0, LOONGARCH_CSR_TLBREHI
+ bltu $t0, $a0, DirMapCsrWr
+ la.pcrel $t0, TlbRefillCsrWrite
+ addi.w $t1, $a0, -LOONGARCH_CSR_TLBREBASE
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ jirl $zero, $t0, 0
+
+DirMapCsrWr:
+ li.w $t0, LOONGARCH_CSR_DMWIN0
+ bltu $a0, $t0, WriteSelNumErr
+ li.w $t0, LOONGARCH_CSR_DMWIN3
+ bltu $t0, $a0, WriteSelNumErr
+ la.pcrel $t0, DirMapCsrWrite
+ addi.w $t1, $a0, -LOONGARCH_CSR_DMWIN0
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ jirl $zero, $t0, 0
+
+WriteSelNumErr:
+ addi.d $a0, $zero, -1
+ jirl $zero, $ra, 0
+
+BasicCsrWrite:
+ CsrSel = LOONGARCH_CSR_CRMD
+ .rept LOONGARCH_CSR_EBASE - LOONGARCH_CSR_CRMD + 1
+ AsmCsrWr CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+TlbCsrWrite:
+ CsrSel = LOONGARCH_CSR_TLBIDX
+ .rept LOONGARCH_CSR_RVACFG - LOONGARCH_CSR_TLBIDX + 1
+ AsmCsrWr CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+CfgCsrWrite:
+ CsrSel = LOONGARCH_CSR_CPUNUM
+ .rept LOONGARCH_CSR_PRCFG3 - LOONGARCH_CSR_CPUNUM + 1
+ AsmCsrWr CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+KcsCsrWrite:
+ CsrSel = LOONGARCH_CSR_KS0
+ .rept LOONGARCH_CSR_KS8 - LOONGARCH_CSR_KS0 + 1
+ AsmCsrWr CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+StableTimerCsrWrite:
+ CsrSel = LOONGARCH_CSR_TMID
+ .rept LOONGARCH_CSR_TINTCLR - LOONGARCH_CSR_TMID + 1
+ AsmCsrWr CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+TlbRefillCsrWrite:
+ CsrSel = LOONGARCH_CSR_TLBREBASE
+ .rept LOONGARCH_CSR_TLBREHI - LOONGARCH_CSR_TLBREBASE + 1
+ AsmCsrWr CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+DirMapCsrWrite:
+ CsrSel = LOONGARCH_CSR_DMWIN0
+ .rept LOONGARCH_CSR_DMWIN3 - LOONGARCH_CSR_DMWIN0 + 1
+ AsmCsrWr CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+
+ASM_PFX(AsmCsrXChg):
+ blt $a0, $zero, XchgSelNumErr
+ li.w $t0, LOONGARCH_CSR_EBASE
+ bltu $t0, $a0, TlbCsrXchg
+
+BasicCsrXchg:
+ la.pcrel $t0, BasicCsrXchange
+ alsl.d $t0, $a0, $t0, 3
+ move $a0, $a1
+ move $a1, $a2
+ jirl $zero, $t0, 0
+
+TlbCsrXchg:
+ li.w $t0, LOONGARCH_CSR_TLBIDX
+ bltu $a0, $t0, XchgSelNumErr
+ li.w $t0, LOONGARCH_CSR_RVACFG
+ bltu $t0, $a0, CfgCsrXchg
+ la.pcrel $t0, TlbCsrXchange
+ addi.w $t1, $a0, -LOONGARCH_CSR_TLBIDX
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ move $a1, $a2
+ jirl $zero, $t0, 0
+
+CfgCsrXchg:
+ li.w $t0, LOONGARCH_CSR_CPUNUM
+ bltu $a0, $t0, XchgSelNumErr
+ li.w $t0, LOONGARCH_CSR_PRCFG3
+ bltu $t0, $a0, KcsCsrXchg
+ la.pcrel $t0, CfgCsrXchange
+ addi.w $t1, $a0, -LOONGARCH_CSR_CPUNUM
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ move $a1, $a2
+ jirl $zero, $t0, 0
+
+KcsCsrXchg:
+ li.w $t0, LOONGARCH_CSR_KS0
+ bltu $a0, $t0, XchgSelNumErr
+ li.w $t0, LOONGARCH_CSR_KS8
+ bltu $t0, $a0, StableTimerCsrXchg
+ la.pcrel $t0, KcsCsrXchange
+ addi.w $t1, $a0, -LOONGARCH_CSR_KS0
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ move $a1, $a2
+ jirl $zero, $t0, 0
+
+StableTimerCsrXchg:
+ li.w $t0, LOONGARCH_CSR_TMID
+ bltu $a0, $t0, XchgSelNumErr
+ li.w $t0, LOONGARCH_CSR_TINTCLR
+ bltu $t0, $a0, TlbRefillCsrXchg
+ la.pcrel $t0, StableTimerCsrXchange
+ addi.w $t1, $a0, -LOONGARCH_CSR_TMID
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ move $a1, $a2
+ jirl $zero, $t0, 0
+
+TlbRefillCsrXchg:
+ li.w $t0, LOONGARCH_CSR_TLBREBASE
+ bltu $a0, $t0, XchgSelNumErr
+ li.w $t0, LOONGARCH_CSR_TLBREHI
+ bltu $t0, $a0, DirMapCsrXchg
+ la.pcrel $t0, TlbRefillCsrXchange
+ addi.w $t1, $a0, -LOONGARCH_CSR_TLBREBASE
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ move $a1, $a2
+ jirl $zero, $t0, 0
+
+DirMapCsrXchg:
+ li.w $t0, LOONGARCH_CSR_DMWIN0
+ bltu $a0, $t0, XchgSelNumErr
+ li.w $t0, LOONGARCH_CSR_DMWIN3
+ bltu $t0, $a0, XchgSelNumErr
+ la.pcrel $t0, DirMapCsrXchange
+ addi.w $t1, $a0, -LOONGARCH_CSR_DMWIN0
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ move $a1, $a2
+ jirl $zero, $t0, 0
+
+XchgSelNumErr:
+ addi.d $a0, $zero, -1
+ jirl $zero, $ra, 0
+
+BasicCsrXchange:
+ CsrSel = LOONGARCH_CSR_CRMD
+ .rept LOONGARCH_CSR_EBASE - LOONGARCH_CSR_CRMD + 1
+ AsmCsrXChange CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+TlbCsrXchange:
+ CsrSel = LOONGARCH_CSR_TLBIDX
+ .rept LOONGARCH_CSR_RVACFG - LOONGARCH_CSR_TLBIDX + 1
+ AsmCsrXChange CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+CfgCsrXchange:
+ CsrSel = LOONGARCH_CSR_CPUNUM
+ .rept LOONGARCH_CSR_PRCFG3 - LOONGARCH_CSR_CPUNUM + 1
+ AsmCsrXChange CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+KcsCsrXchange:
+ CsrSel = LOONGARCH_CSR_KS0
+ .rept LOONGARCH_CSR_KS8 - LOONGARCH_CSR_KS0 + 1
+ AsmCsrXChange CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+StableTimerCsrXchange:
+ CsrSel = LOONGARCH_CSR_TMID
+ .rept LOONGARCH_CSR_TINTCLR - LOONGARCH_CSR_TMID + 1
+ AsmCsrXChange CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+TlbRefillCsrXchange:
+ CsrSel = LOONGARCH_CSR_TLBREBASE
+ .rept LOONGARCH_CSR_TLBREHI - LOONGARCH_CSR_TLBREBASE + 1
+ AsmCsrXChange CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+DirMapCsrXchange:
+ CsrSel = LOONGARCH_CSR_DMWIN0
+ .rept LOONGARCH_CSR_DMWIN3 - LOONGARCH_CSR_DMWIN0 + 1
+ AsmCsrXChange CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+.end
diff --git a/MdePkg/Library/BaseLib/LoongArch64/Csr.c b/MdePkg/Library/BaseLib/LoongArch64/Csr.c
new file mode 100644
index 0000000000..f2ec80b38d
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/Csr.c
@@ -0,0 +1,81 @@
+/** @file
+ LoongArch CSR operation functions.
+
+ Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+UINTN
+AsmCsrRead (
+ IN UINT16 Select
+ );
+
+UINTN
+AsmCsrWrite (
+ IN UINT16 Select,
+ IN UINTN Value
+ );
+
+UINTN
+AsmCsrXChg (
+ IN UINT16 Select,
+ IN UINTN Value,
+ IN UINTN Mask
+ );
+
+/**
+ CSR read operation.
+
+ @param[in] Select CSR read instruction select values.
+
+ @return The return value of csrrd instruction, return -1 means Select is out of support.
+**/
+UINTN
+EFIAPI
+CsrRead (
+ IN UINT16 Select
+ )
+{
+ return AsmCsrRead (Select);
+}
+
+/**
+ CSR write operation.
+
+ @param[in] Select CSR write instruction select values.
+ @param[in, out] Value The csrwr will write the value.
+
+ @return The return value of csrwr instruction, that is, store the old value of
+ the register, return -1 means Select is out of support.
+**/
+UINTN
+EFIAPI
+CsrWrite (
+ IN UINT16 Select,
+ IN OUT UINTN Value
+ )
+{
+ return AsmCsrWrite (Select, Value);
+}
+
+/**
+ CSR exchange operation.
+
+ @param[in] Select CSR exchange instruction select values.
+ @param[in, out] Value The csrxchg will write the value.
+ @param[in] Mask The csrxchg mask value.
+
+ @return The return value of csrxchg instruction, that is, store the old value of
+ the register, return -1 means Select is out of support.
+**/
+UINTN
+EFIAPI
+CsrXChg (
+ IN UINT16 Select,
+ IN OUT UINTN Value,
+ IN UINTN Mask
+ )
+{
+ return AsmCsrXChg (Select, Value, Mask);
+}
--
2.27.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [edk2-devel] [PATCH v1 08/19] MdePkg: Add IOCSR operation for LoongArch
2024-02-02 2:26 [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Chao Li
` (6 preceding siblings ...)
2024-02-02 2:27 ` [edk2-devel] [PATCH v1 07/19] MdePkg: Add CSR " Chao Li
@ 2024-02-02 2:28 ` Chao Li
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 09/19] MdePkg: Add a new library named PeiServicesTablePointerLibKs0 Chao Li
` (11 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Chao Li @ 2024-02-02 2:28 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu
Add IoCsrRead8, IoCsrRead16, IoCsrRead32, IoCsrRead64, IoCsrWrite8,
IoCsrWrite16, IoCsrWrite32, IoCsrWrite64 to operate the IOCSR registers
of LoongArch architecture.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Acked-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
---
MdePkg/Include/Library/BaseLib.h | 112 +++++++++++++++++++
MdePkg/Library/BaseLib/BaseLib.inf | 1 +
MdePkg/Library/BaseLib/LoongArch64/IoCsr.S | 120 +++++++++++++++++++++
3 files changed, 233 insertions(+)
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/IoCsr.S
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 4e97368ae2..1fff0fb224 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -396,6 +396,118 @@ CsrXChg (
IN UINTN Mask
);
+/**
+ IO CSR read byte operation.
+
+ @param[in] Select IO CSR read instruction select values.
+
+ @return The return value of iocsrrd.b instruction.
+
+**/
+UINT8
+IoCsrRead8 (
+ IN UINTN Select
+ );
+
+/**
+ IO CSR read half word operation.
+
+ @param[in] Select IO CSR read instruction select values.
+
+ @return The return value of iocsrrd.h instruction.
+
+**/
+UINT16
+IoCsrRead16 (
+ IN UINTN Select
+ );
+
+/**
+ IO CSR read word operation.
+
+ @param[in] Select IO CSR read instruction select values.
+
+ @return The return value of iocsrrd.w instruction.
+
+**/
+UINT32
+IoCsrRead32 (
+ IN UINTN Select
+ );
+
+/**
+ IO CSR read double word operation. Only for LoongArch64.
+
+ @param[in] Select IO CSR read instruction select values.
+
+ @return The return value of iocsrrd.d instruction.
+
+**/
+UINT64
+IoCsrRead64 (
+ IN UINTN Select
+ );
+
+/**
+ IO CSR write byte operation.
+
+ @param[in] Select IO CSR write instruction select values.
+ @param[in] Value The iocsrwr.b will write the value.
+
+ @return VOID.
+
+**/
+VOID
+IoCsrWrite8 (
+ IN UINTN Select,
+ IN UINT8 Value
+ );
+
+/**
+ IO CSR write half word operation.
+
+ @param[in] Select IO CSR write instruction select values.
+ @param[in] Value The iocsrwr.h will write the value.
+
+ @return VOID.
+
+**/
+VOID
+IoCsrWrite16 (
+ IN UINTN Select,
+ IN UINT16 Value
+ );
+
+/**
+ IO CSR write word operation.
+
+ @param[in] Select IO CSR write instruction select values.
+ @param[in] Value The iocsrwr.w will write the value.
+
+ @return VOID.
+
+**/
+VOID
+IoCsrWrite32 (
+ IN UINTN Select,
+ IN UINT32 Value
+ );
+
+/**
+ IO CSR write double word operation. Only for LoongArch64.
+
+ @param[in] Select IO CSR write instruction select values.
+ @param[in] Value The iocsrwr.d will write the value.
+
+ @return VOID.
+
+**/
+VOID
+IoCsrWrite64 (
+ IN UINTN Select,
+ IN UINT64 Value
+ );
+
#endif // defined (MDE_CPU_LOONGARCH64)
//
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 7c46306883..4dbe94be71 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -413,6 +413,7 @@ [Sources.LOONGARCH64]
LoongArch64/Csr.c
LoongArch64/InternalSwitchStack.c
LoongArch64/AsmCsr.S | GCC
+ LoongArch64/IoCsr.S | GCC
LoongArch64/GetInterruptState.S | GCC
LoongArch64/EnableInterrupts.S | GCC
LoongArch64/DisableInterrupts.S | GCC
diff --git a/MdePkg/Library/BaseLib/LoongArch64/IoCsr.S b/MdePkg/Library/BaseLib/LoongArch64/IoCsr.S
new file mode 100644
index 0000000000..a659908bc4
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/IoCsr.S
@@ -0,0 +1,120 @@
+#------------------------------------------------------------------------------
+#
+# LoongArch ASM IO CSR operation functions
+#
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX (IoCsrRead8)
+ASM_GLOBAL ASM_PFX (IoCsrRead16)
+ASM_GLOBAL ASM_PFX (IoCsrRead32)
+ASM_GLOBAL ASM_PFX (IoCsrRead64)
+
+ASM_GLOBAL ASM_PFX (IoCsrWrite8)
+ASM_GLOBAL ASM_PFX (IoCsrWrite16)
+ASM_GLOBAL ASM_PFX (IoCsrWrite32)
+ASM_GLOBAL ASM_PFX (IoCsrWrite64)
+
+#/**
+# IO CSR read byte operation.
+#
+# @param[in] Select IO CSR read instruction select values.
+#
+# @return The return value of iocsrrd.b instruction.
+#
+#**/
+ASM_PFX (IoCsrRead8):
+ iocsrrd.b $a0, $a0
+ jirl $zero, $ra, 0
+
+#/**
+# IO CSR read half word operation.
+#
+# @param[in] Select IO CSR read instruction select values.
+#
+# @return The return value of iocsrrd.h instruction.
+#
+#**/
+ASM_PFX (IoCsrRead16):
+ iocsrrd.h $a0, $a0
+ jirl $zero, $ra, 0
+
+#/**
+# IO CSR read word operation.
+#
+# @param[in] Select IO CSR read instruction select values.
+#
+# @return The return value of iocsrrd.w instruction.
+#
+#**/
+ASM_PFX (IoCsrRead32):
+ iocsrrd.w $a0, $a0
+ jirl $zero, $ra, 0
+
+#/**
+# IO CSR read double word operation. Only for LoongArch64.
+#
+# @param[in] Select IO CSR read instruction select values.
+#
+# @return The return value of iocsrrd.d instruction.
+#
+#**/
+ASM_PFX (IoCsrRead64):
+ iocsrrd.d $a0, $a0
+ jirl $zero, $ra, 0
+
+#/**
+# IO CSR write byte operation.
+#
+# @param[in] Select IO CSR write instruction select values.
+# @param[in] Value The iocsrwr.b will write the value.
+#
+# @return VOID.
+#
+#**/
+ASM_PFX (IoCsrWrite8):
+ iocsrwr.b $a1, $a0
+ jirl $zero, $ra, 0
+
+#/**
+# IO CSR write half word operation.
+#
+# @param[in] Select IO CSR write instruction select values.
+# @param[in] Value The iocsrwr.h will write the value.
+#
+# @return VOID.
+#
+#**/
+ASM_PFX (IoCsrWrite16):
+ iocsrwr.h $a1, $a0
+ jirl $zero, $ra, 0
+
+#/**
+# IO CSR write word operation.
+#
+# @param[in] Select IO CSR write instruction select values.
+# @param[in] Value The iocsrwr.w will write the value.
+#
+# @return VOID.
+#
+#**/
+ASM_PFX (IoCsrWrite32):
+ iocsrwr.w $a1, $a0
+ jirl $zero, $ra, 0
+
+#/**
+# IO CSR write double word operation. Only for LoongArch64.
+#
+# @param[in] Select IO CSR write instruction select values.
+# @param[in] Value The iocsrwr.d will write the value.
+#
+# @return VOID.
+#
+#**/
+ASM_PFX (IoCsrWrite64):
+ iocsrwr.d $a1, $a0
+ jirl $zero, $ra, 0
+ .end
--
2.27.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [edk2-devel] [PATCH v1 09/19] MdePkg: Add a new library named PeiServicesTablePointerLibKs0
2024-02-02 2:26 [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Chao Li
` (7 preceding siblings ...)
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 08/19] MdePkg: Add IOCSR " Chao Li
@ 2024-02-02 2:28 ` Chao Li
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 10/19] MdePkg: Add some comments for LoongArch exceptions Chao Li
` (10 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Chao Li @ 2024-02-02 2:28 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu, Laszlo Ersek
Adding PeiServicesTablePointerLibKs0 for LoongArch64, which provides
setting and getting the PEI service table pointer through the CSR KS0
register.
The idea of this library is derived from
ArmPkg/Library/PeiServicesTablePointerLib/
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
---
.../Library/PeiServicesTablePointerLib.h | 9 +-
.../PeiServicesTablePointer.c | 87 +++++++++++++++++++
.../PeiServicesTablePointerLibKs0.inf | 37 ++++++++
.../PeiServicesTablePointerLibKs0.uni | 20 +++++
MdePkg/MdePkg.dsc | 3 +
5 files changed, 152 insertions(+), 4 deletions(-)
create mode 100644 MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointer.c
create mode 100644 MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointerLibKs0.inf
create mode 100644 MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointerLibKs0.uni
diff --git a/MdePkg/Include/Library/PeiServicesTablePointerLib.h b/MdePkg/Include/Library/PeiServicesTablePointerLib.h
index 61635eff00..f85c38363c 100644
--- a/MdePkg/Include/Library/PeiServicesTablePointerLib.h
+++ b/MdePkg/Include/Library/PeiServicesTablePointerLib.h
@@ -52,10 +52,11 @@ SetPeiServicesTablePointer (
immediately preceding the Interrupt Descriptor Table (IDT) in memory.
For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
immediately preceding the Interrupt Descriptor Table (IDT) in memory.
- For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in
- a dedicated CPU register. This means that there is no memory storage
- associated with storing the PEI Services Table pointer, so no additional
- migration actions are required for Itanium or ARM CPUs.
+ For Itanium, ARM and LoongArch CPUs, a the PEI Services Table Pointer
+ is stored in a dedicated CPU register. This means that there is no
+ memory storage associated with storing the PEI Services Table pointer,
+ so no additional migration actions are required for Itanium, ARM and
+ LoongArch CPUs.
**/
VOID
diff --git a/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointer.c b/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointer.c
new file mode 100644
index 0000000000..f9800936b2
--- /dev/null
+++ b/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointer.c
@@ -0,0 +1,87 @@
+/** @file
+ PEI Services Table Pointer Library For Reigseter Mechanism.
+
+ This library is used for PEIM which does executed from flash device directly but
+ executed in memory.
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2011 Hewlett-Packard Corporation. All rights reserved.<BR>
+ Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Register/LoongArch64/Csr.h>
+
+/**
+ Caches a pointer PEI Services Table.
+
+ Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer
+ in a platform specific manner.
+
+ If PeiServicesTablePointer is NULL, then ASSERT().
+
+ @param PeiServicesTablePointer The address of PeiServices pointer.
+**/
+VOID
+EFIAPI
+SetPeiServicesTablePointer (
+ IN CONST EFI_PEI_SERVICES **PeiServicesTablePointer
+ )
+{
+ ASSERT (PeiServicesTablePointer != NULL);
+ CsrWrite (LOONGARCH_CSR_KS0, (UINTN)PeiServicesTablePointer);
+}
+
+/**
+ Retrieves the cached value of the PEI Services Table pointer.
+
+ Returns the cached value of the PEI Services Table pointer in a CPU specific manner
+ as specified in the CPU binding section of the Platform Initialization Pre-EFI
+ Initialization Core Interface Specification.
+
+ If the cached PEI Services Table pointer is NULL, then ASSERT().
+
+ @return The pointer to PeiServices.
+
+**/
+CONST EFI_PEI_SERVICES **
+EFIAPI
+GetPeiServicesTablePointer (
+ VOID
+ )
+{
+ CONST EFI_PEI_SERVICES **PeiServices;
+
+ PeiServices = (CONST EFI_PEI_SERVICES **)(CsrRead (LOONGARCH_CSR_KS0));
+ ASSERT (PeiServices != NULL);
+ return PeiServices;
+}
+
+/**
+ Perform CPU specific actions required to migrate the PEI Services Table
+ pointer from temporary RAM to permanent RAM.
+
+ For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes
+ immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+ For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
+ immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+ For Itanium, ARM and LoongArch CPUs, a the PEI Services Table Pointer
+ is stored in a dedicated CPU register. This means that there is no
+ memory storage associated with storing the PEI Services Table pointer,
+ so no additional migration actions are required for Itanium, ARM and
+ LoongArch CPUs.
+
+**/
+VOID
+EFIAPI
+MigratePeiServicesTablePointer (
+ VOID
+ )
+{
+ return;
+}
diff --git a/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointerLibKs0.inf b/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointerLibKs0.inf
new file mode 100644
index 0000000000..513f62517d
--- /dev/null
+++ b/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointerLibKs0.inf
@@ -0,0 +1,37 @@
+## @file
+# Instance of PEI Services Table Pointer Library using register CSR KS0 for the table pointer.
+#
+# PEI Services Table Pointer Library implementation that retrieves a pointer to the
+# PEI Services Table from a CPU register. Applies to modules that execute from
+# read-only memory.
+#
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2011 Hewlett-Packard Corporation. All rights reserved.<BR>
+# Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 1.29
+ BASE_NAME = PeiServicesTablePointerLib
+ MODULE_UNI_FILE = PeiServicesTablePointerLibKs0.uni
+ FILE_GUID = 619950D1-7C5F-EA1B-D6DD-2FF7B0A4A2B7
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PeiServicesTablePointerLib|PEIM PEI_CORE SEC
+
+#
+# VALID_ARCHITECTURES = LOONGARCH64
+#
+
+[Sources]
+ PeiServicesTablePointer.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ DebugLib
diff --git a/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointerLibKs0.uni b/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointerLibKs0.uni
new file mode 100644
index 0000000000..a1db86b0b7
--- /dev/null
+++ b/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointerLibKs0.uni
@@ -0,0 +1,20 @@
+// /** @file
+// Instance of PEI Services Table Pointer Library using register CSR KS0 for the table pointer.
+//
+// PEI Services Table Pointer Library implementation that retrieves a pointer to the
+// PEI Services Table from a CPU register. Applies to modules that execute from
+// read-only memory.
+//
+// Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2011 Hewlett-Packard Corporation. All rights reserved.<BR>
+// Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Instance of PEI Services Table Pointer Library using CPU register for the table pointer"
+
+#string STR_MODULE_DESCRIPTION #language en-US "The PEI Services Table Pointer Library implementation that retrieves a pointer to the PEI Services Table from a CPU register. Applies to modules that execute from read-only memory."
+
diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc
index 3abd1a1e23..109224c527 100644
--- a/MdePkg/MdePkg.dsc
+++ b/MdePkg/MdePkg.dsc
@@ -200,4 +200,7 @@ [Components.RISCV64]
MdePkg/Library/BaseSerialPortLibRiscVSbiLib/BaseSerialPortLibRiscVSbiLib.inf
MdePkg/Library/BaseSerialPortLibRiscVSbiLib/BaseSerialPortLibRiscVSbiLibRam.inf
+[Components.LOONGARCH64]
+ MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointerLibKs0.inf
+
[BuildOptions]
--
2.27.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [edk2-devel] [PATCH v1 10/19] MdePkg: Add some comments for LoongArch exceptions
2024-02-02 2:26 [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Chao Li
` (8 preceding siblings ...)
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 09/19] MdePkg: Add a new library named PeiServicesTablePointerLibKs0 Chao Li
@ 2024-02-02 2:28 ` Chao Li
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 11/19] EmbeddedPkg: Add PcdPrePiCpuIoSize width for LOONGARCH64 Chao Li
` (9 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Chao Li @ 2024-02-02 2:28 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu
Added some comments for registing LoongArch exceptions.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
---
MdePkg/Include/Protocol/DebugSupport.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Protocol/DebugSupport.h
index 9742663619..06f99ba7f7 100644
--- a/MdePkg/Include/Protocol/DebugSupport.h
+++ b/MdePkg/Include/Protocol/DebugSupport.h
@@ -683,6 +683,20 @@ typedef struct {
//
// LoongArch processor exception types.
//
+// The exception types is located in the CSR ESTAT
+// register offset 16 bits, width 6 bits.
+//
+// If you want to register an exception hook, you can
+// shfit the number left by 16 bits, and the exception
+// handler will know the types.
+//
+// For example:
+// mCpu->CpuRegisterInterruptHandler (
+// mCpu,
+// (EXCEPT_LOONGARCH_PPI << CSR_ESTAT_EXC_SHIFT),
+// PpiExceptionHandler
+// );
+//
#define EXCEPT_LOONGARCH_INT 0
#define EXCEPT_LOONGARCH_PIL 1
#define EXCEPT_LOONGARCH_PIS 2
--
2.27.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [edk2-devel] [PATCH v1 11/19] EmbeddedPkg: Add PcdPrePiCpuIoSize width for LOONGARCH64
2024-02-02 2:26 [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Chao Li
` (9 preceding siblings ...)
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 10/19] MdePkg: Add some comments for LoongArch exceptions Chao Li
@ 2024-02-02 2:28 ` Chao Li
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 12/19] ArmVirtPkg: Move PCD of FDT base address and FDT padding to OvmfPkg Chao Li
` (8 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Chao Li @ 2024-02-02 2:28 UTC (permalink / raw)
To: devel; +Cc: Leif Lindholm, Ard Biesheuvel, Abner Chang, Daniel Schaefer
Added LoongArch64 architecture CPU IO width.
https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
---
EmbeddedPkg/EmbeddedPkg.dec | 3 +++
1 file changed, 3 insertions(+)
diff --git a/EmbeddedPkg/EmbeddedPkg.dec b/EmbeddedPkg/EmbeddedPkg.dec
index b4834e8b4f..5dfbbc2933 100644
--- a/EmbeddedPkg/EmbeddedPkg.dec
+++ b/EmbeddedPkg/EmbeddedPkg.dec
@@ -166,6 +166,9 @@ [PcdsFixedAtBuild.IA32]
[PcdsFixedAtBuild.X64]
gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16|UINT8|0x00000011
+[PcdsFixedAtBuild.LOONGARCH64]
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16|UINT8|0x00000011
+
[PcdsFixedAtBuild.common, PcdsDynamic.common]
#
# Value to add to a host address to obtain a device address, using
--
2.27.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [edk2-devel] [PATCH v1 12/19] ArmVirtPkg: Move PCD of FDT base address and FDT padding to OvmfPkg
2024-02-02 2:26 [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Chao Li
` (10 preceding siblings ...)
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 11/19] EmbeddedPkg: Add PcdPrePiCpuIoSize width for LOONGARCH64 Chao Li
@ 2024-02-02 2:28 ` Chao Li
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 13/19] UefiCpuPkg: Add a new CPU IO 2 driver named CpuMmio2Dxe Chao Li
` (7 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Chao Li @ 2024-02-02 2:28 UTC (permalink / raw)
To: devel
Cc: Ard Biesheuvel, Laszlo Ersek, Leif Lindholm, Sami Mujawar,
Gerd Hoffmann, Jiewen Yao, Jordan Justen
Moved PcdDeviceTreeInitialBaseAddress and PcdDeviceTreeAllocationPadding
to OvmfPkg for easier use by other architectures.
Build-tested only (with "ArmVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
---
ArmVirtPkg/ArmVirtCloudHv.dsc | 2 +-
ArmVirtPkg/ArmVirtKvmTool.dsc | 2 +-
ArmVirtPkg/ArmVirtPkg.dec | 14 --------------
ArmVirtPkg/ArmVirtQemu.dsc | 2 +-
ArmVirtPkg/ArmVirtQemuKernel.dsc | 2 +-
ArmVirtPkg/ArmVirtXen.dsc | 2 +-
.../ArmVirtPsciResetSystemPeiLib.inf | 3 ++-
.../CloudHvVirtMemInfoPeiLib.inf | 3 ++-
.../DebugLibFdtPL011UartFlash.inf | 3 ++-
.../EarlyFdt16550SerialPortHookLib.inf | 3 ++-
.../EarlyFdtPL011SerialPortLib.inf | 3 ++-
.../KvmtoolPlatformPeiLib.inf | 5 +++--
.../Library/PlatformPeiLib/PlatformPeiLib.inf | 10 +++++-----
.../QemuVirtMemInfoLib/QemuVirtMemInfoPeiLib.inf | 3 ++-
.../PrePi/ArmVirtPrePiUniCoreRelocatable.inf | 3 ++-
OvmfPkg/OvmfPkg.dec | 15 +++++++++++++++
16 files changed, 42 insertions(+), 33 deletions(-)
diff --git a/ArmVirtPkg/ArmVirtCloudHv.dsc b/ArmVirtPkg/ArmVirtCloudHv.dsc
index 2cb89ce10c..76c0d28544 100644
--- a/ArmVirtPkg/ArmVirtCloudHv.dsc
+++ b/ArmVirtPkg/ArmVirtCloudHv.dsc
@@ -129,7 +129,7 @@ [PcdsFixedAtBuild.common]
gArmTokenSpaceGuid.PcdSystemMemoryBase|0x40000000
# initial location of the device tree blob passed by Cloud Hypervisor -- base of DRAM
- gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x40000000
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x40000000
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
diff --git a/ArmVirtPkg/ArmVirtKvmTool.dsc b/ArmVirtPkg/ArmVirtKvmTool.dsc
index f50d53bf15..cac4fe06d3 100644
--- a/ArmVirtPkg/ArmVirtKvmTool.dsc
+++ b/ArmVirtPkg/ArmVirtKvmTool.dsc
@@ -179,7 +179,7 @@ [PcdsPatchableInModule.common]
# We are booting from RAM using the Linux kernel boot protocol,
# x0 will point to the DTB image in memory.
#
- gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x0
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x0
gArmTokenSpaceGuid.PcdFdBaseAddress|0x0
gArmTokenSpaceGuid.PcdFvBaseAddress|0x0
diff --git a/ArmVirtPkg/ArmVirtPkg.dec b/ArmVirtPkg/ArmVirtPkg.dec
index 313aebda90..05d2d36c1d 100644
--- a/ArmVirtPkg/ArmVirtPkg.dec
+++ b/ArmVirtPkg/ArmVirtPkg.dec
@@ -42,20 +42,6 @@ [PcdsFeatureFlag]
gArmVirtTokenSpaceGuid.PcdTpm2SupportEnabled|FALSE|BOOLEAN|0x00000004
[PcdsFixedAtBuild, PcdsPatchableInModule]
- #
- # This is the physical address where the device tree is expected to be stored
- # upon first entry into UEFI. This needs to be a FixedAtBuild PCD, so that we
- # can do a first pass over the device tree in the SEC phase to discover the
- # UART base address.
- #
- gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x0|UINT64|0x00000001
-
- #
- # Padding in bytes to add to the device tree allocation, so that the DTB can
- # be modified in place (default: 256 bytes)
- #
- gArmVirtTokenSpaceGuid.PcdDeviceTreeAllocationPadding|256|UINT32|0x00000002
-
#
# Binary representation of the GUID that determines the terminal type. The
# size must be exactly 16 bytes. The default value corresponds to
diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc
index 30e3cfc8b9..cf306cac08 100644
--- a/ArmVirtPkg/ArmVirtQemu.dsc
+++ b/ArmVirtPkg/ArmVirtQemu.dsc
@@ -201,7 +201,7 @@ [PcdsFixedAtBuild.common]
gArmTokenSpaceGuid.PcdSystemMemoryBase|0x40000000
# initial location of the device tree blob passed by QEMU -- base of DRAM
- gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x40000000
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x40000000
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKernel.dsc
index b50f8e84a3..c0d079e28d 100644
--- a/ArmVirtPkg/ArmVirtQemuKernel.dsc
+++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc
@@ -198,7 +198,7 @@ [PcdsPatchableInModule.common]
# Define a default initial address for the device tree.
# Ignored if x0 != 0 at entry.
#
- gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x40000000
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x40000000
gArmTokenSpaceGuid.PcdFdBaseAddress|0x0
gArmTokenSpaceGuid.PcdFvBaseAddress|0x0
diff --git a/ArmVirtPkg/ArmVirtXen.dsc b/ArmVirtPkg/ArmVirtXen.dsc
index f0d15b823b..5809832e66 100644
--- a/ArmVirtPkg/ArmVirtXen.dsc
+++ b/ArmVirtPkg/ArmVirtXen.dsc
@@ -115,7 +115,7 @@ [PcdsPatchableInModule.common]
#
gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0
gArmTokenSpaceGuid.PcdSystemMemorySize|0x0
- gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x0
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x0
gArmTokenSpaceGuid.PcdFdBaseAddress|0x0
gArmTokenSpaceGuid.PcdFvBaseAddress|0x0
diff --git a/ArmVirtPkg/Library/ArmVirtPsciResetSystemPeiLib/ArmVirtPsciResetSystemPeiLib.inf b/ArmVirtPkg/Library/ArmVirtPsciResetSystemPeiLib/ArmVirtPsciResetSystemPeiLib.inf
index 3a65706e8d..79217d296d 100644
--- a/ArmVirtPkg/Library/ArmVirtPsciResetSystemPeiLib/ArmVirtPsciResetSystemPeiLib.inf
+++ b/ArmVirtPkg/Library/ArmVirtPsciResetSystemPeiLib/ArmVirtPsciResetSystemPeiLib.inf
@@ -26,6 +26,7 @@ [Packages]
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
+ OvmfPkg/OvmfPkg.dec
[LibraryClasses]
ArmSmcLib
@@ -36,4 +37,4 @@ [LibraryClasses]
HobLib
[Pcd]
- gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress
diff --git a/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoPeiLib.inf b/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoPeiLib.inf
index 666b5d9711..6df26ccd64 100644
--- a/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoPeiLib.inf
+++ b/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoPeiLib.inf
@@ -26,6 +26,7 @@ [Packages]
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
+ OvmfPkg/OvmfPkg.dec
[LibraryClasses]
ArmLib
@@ -44,4 +45,4 @@ [Pcd]
[FixedPcd]
gArmTokenSpaceGuid.PcdFdSize
gArmTokenSpaceGuid.PcdFvSize
- gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress
diff --git a/ArmVirtPkg/Library/DebugLibFdtPL011Uart/DebugLibFdtPL011UartFlash.inf b/ArmVirtPkg/Library/DebugLibFdtPL011Uart/DebugLibFdtPL011UartFlash.inf
index 7870ca2ae4..f35a0913f0 100644
--- a/ArmVirtPkg/Library/DebugLibFdtPL011Uart/DebugLibFdtPL011UartFlash.inf
+++ b/ArmVirtPkg/Library/DebugLibFdtPL011Uart/DebugLibFdtPL011UartFlash.inf
@@ -30,6 +30,7 @@ [Packages]
ArmPlatformPkg/ArmPlatformPkg.dec
ArmVirtPkg/ArmVirtPkg.dec
MdePkg/MdePkg.dec
+ OvmfPkg/OvmfPkg.dec
[LibraryClasses]
BaseLib
@@ -41,7 +42,7 @@ [LibraryClasses]
PrintLib
[Pcd]
- gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress # Flash.c
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress # Flash.c
gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask
gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel
diff --git a/ArmVirtPkg/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.inf b/ArmVirtPkg/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.inf
index 22aba53d9b..3e2303b7f4 100644
--- a/ArmVirtPkg/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.inf
+++ b/ArmVirtPkg/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.inf
@@ -29,7 +29,8 @@ [Packages]
ArmVirtPkg/ArmVirtPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
+ OvmfPkg/OvmfPkg.dec
[Pcd]
- gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
diff --git a/ArmVirtPkg/Library/FdtPL011SerialPortLib/EarlyFdtPL011SerialPortLib.inf b/ArmVirtPkg/Library/FdtPL011SerialPortLib/EarlyFdtPL011SerialPortLib.inf
index f47692f06a..e677f1d9e7 100644
--- a/ArmVirtPkg/Library/FdtPL011SerialPortLib/EarlyFdtPL011SerialPortLib.inf
+++ b/ArmVirtPkg/Library/FdtPL011SerialPortLib/EarlyFdtPL011SerialPortLib.inf
@@ -28,9 +28,10 @@ [Packages]
MdePkg/MdePkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
ArmVirtPkg/ArmVirtPkg.dec
+ OvmfPkg/OvmfPkg.dec
[Pcd]
- gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress
[FixedPcd]
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
diff --git a/ArmVirtPkg/Library/KvmtoolPlatformPeiLib/KvmtoolPlatformPeiLib.inf b/ArmVirtPkg/Library/KvmtoolPlatformPeiLib/KvmtoolPlatformPeiLib.inf
index f201aee50c..77c0b923bd 100644
--- a/ArmVirtPkg/Library/KvmtoolPlatformPeiLib/KvmtoolPlatformPeiLib.inf
+++ b/ArmVirtPkg/Library/KvmtoolPlatformPeiLib/KvmtoolPlatformPeiLib.inf
@@ -24,6 +24,7 @@ [Packages]
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
+ OvmfPkg/OvmfPkg.dec
[LibraryClasses]
DebugLib
@@ -34,12 +35,12 @@ [LibraryClasses]
[FixedPcd]
gArmTokenSpaceGuid.PcdFvSize
- gArmVirtTokenSpaceGuid.PcdDeviceTreeAllocationPadding
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeAllocationPadding
[Pcd]
gArmTokenSpaceGuid.PcdFvBaseAddress
- gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress
[Guids]
gFdtHobGuid
diff --git a/ArmVirtPkg/Library/PlatformPeiLib/PlatformPeiLib.inf b/ArmVirtPkg/Library/PlatformPeiLib/PlatformPeiLib.inf
index b867d8bb89..e9a34b6e2e 100644
--- a/ArmVirtPkg/Library/PlatformPeiLib/PlatformPeiLib.inf
+++ b/ArmVirtPkg/Library/PlatformPeiLib/PlatformPeiLib.inf
@@ -41,16 +41,16 @@ [LibraryClasses]
[FixedPcd]
gArmTokenSpaceGuid.PcdFvSize
- gArmVirtTokenSpaceGuid.PcdDeviceTreeAllocationPadding
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeAllocationPadding
[Pcd]
gArmTokenSpaceGuid.PcdFvBaseAddress
- gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress
- gEfiSecurityPkgTokenSpaceGuid.PcdTpmBaseAddress ## SOMETIMES_PRODUCES
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmBaseAddress ## SOMETIMES_PRODUCES
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress
[Ppis]
- gOvmfTpmDiscoveredPpiGuid ## SOMETIMES_PRODUCES
- gPeiTpmInitializationDonePpiGuid ## SOMETIMES_PRODUCES
+ gOvmfTpmDiscoveredPpiGuid ## SOMETIMES_PRODUCES
+ gPeiTpmInitializationDonePpiGuid ## SOMETIMES_PRODUCES
[Guids]
gEarlyPL011BaseAddressGuid
diff --git a/ArmVirtPkg/Library/QemuVirtMemInfoLib/QemuVirtMemInfoPeiLib.inf b/ArmVirtPkg/Library/QemuVirtMemInfoLib/QemuVirtMemInfoPeiLib.inf
index f045e39a41..76c3c5d3c8 100644
--- a/ArmVirtPkg/Library/QemuVirtMemInfoLib/QemuVirtMemInfoPeiLib.inf
+++ b/ArmVirtPkg/Library/QemuVirtMemInfoLib/QemuVirtMemInfoPeiLib.inf
@@ -26,6 +26,7 @@ [Packages]
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
+ OvmfPkg/OvmfPkg.dec
[LibraryClasses]
ArmLib
@@ -44,4 +45,4 @@ [FixedPcd]
gArmTokenSpaceGuid.PcdSystemMemorySize
gArmTokenSpaceGuid.PcdFdSize
gArmTokenSpaceGuid.PcdFvSize
- gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress
diff --git a/ArmVirtPkg/PrePi/ArmVirtPrePiUniCoreRelocatable.inf b/ArmVirtPkg/PrePi/ArmVirtPrePiUniCoreRelocatable.inf
index 7edf501808..6b9244bd1a 100755
--- a/ArmVirtPkg/PrePi/ArmVirtPrePiUniCoreRelocatable.inf
+++ b/ArmVirtPkg/PrePi/ArmVirtPrePiUniCoreRelocatable.inf
@@ -35,6 +35,7 @@ [Packages]
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
ArmVirtPkg/ArmVirtPkg.dec
+ OvmfPkg/OvmfPkg.dec
[LibraryClasses]
BaseLib
@@ -93,6 +94,6 @@ [FixedPcd]
[Pcd]
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize
- gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress
gArmTokenSpaceGuid.PcdFdBaseAddress
gArmTokenSpaceGuid.PcdFvBaseAddress
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress
diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec
index b44fa039f7..7bc2bf1674 100644
--- a/OvmfPkg/OvmfPkg.dec
+++ b/OvmfPkg/OvmfPkg.dec
@@ -386,6 +386,21 @@ [PcdsDynamic, PcdsDynamicEx]
#
gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi|0x0|BOOLEAN|0x69
+[PcdsFixedAtBuild, PcdsPatchableInModule]
+ #
+ # This is the physical address where the device tree is expected to be stored
+ # upon first entry into UEFI. This needs to be a FixedAtBuild PCD, so that we
+ # can do a first pass over the device tree in the SEC phase to discover the
+ # UART base address.
+ #
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x0|UINT64|0x6e
+
+ #
+ # Padding in bytes to add to the device tree allocation, so that the DTB can
+ # be modified in place (default: 256 bytes)
+ #
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeAllocationPadding|256|UINT32|0x6f
+
[PcdsFeatureFlag]
gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0x1c
gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN|0x1d
--
2.27.0
-=-=-=-=-=-=-=-=-=-=-=-
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [edk2-devel] [PATCH v1 13/19] UefiCpuPkg: Add a new CPU IO 2 driver named CpuMmio2Dxe
2024-02-02 2:26 [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Chao Li
` (11 preceding siblings ...)
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 12/19] ArmVirtPkg: Move PCD of FDT base address and FDT padding to OvmfPkg Chao Li
@ 2024-02-02 2:28 ` Chao Li
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 14/19] ArmVirtPkg: Enable CpuMmio2Dxe Chao Li
` (6 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Chao Li @ 2024-02-02 2:28 UTC (permalink / raw)
To: devel
Cc: Ray Ni, Laszlo Ersek, Rahul Kumar, Gerd Hoffmann, Leif Lindholm,
Ard Biesheuvel, Sami Mujawar
CpuIo2Dxe only supports IO to access to CPU IO. Some ARCHs that do not
implement ports for CPU IO require MMIO to access PCI IO, and they
pretty much put the IO devices under the LPC bus, which is usually under
the PCIe/PCI bus. CpuMmio2Dxe was added to meet these needs.
CpuMmio2Dxe depends on PcdPciIoTranslation. The code is copied from
ArmPkg.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Ray Ni <ray.ni@intel.com>
---
UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c | 557 +++++++++++++++++++++++++
UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf | 48 +++
UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.uni | 18 +
UefiCpuPkg/UefiCpuPkg.dsc | 1 +
4 files changed, 624 insertions(+)
create mode 100644 UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c
create mode 100644 UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
create mode 100644 UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.uni
diff --git a/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c b/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c
new file mode 100644
index 0000000000..32ccac1cc6
--- /dev/null
+++ b/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c
@@ -0,0 +1,557 @@
+/** @file
+ Produces the CPU I/O 2 Protocol.
+
+Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiDxe.h>
+
+#include <Protocol/CpuIo2.h>
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#define MAX_IO_PORT_ADDRESS 0xFFFF
+
+//
+// Handle for the CPU I/O 2 Protocol
+//
+STATIC EFI_HANDLE mHandle = NULL;
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mInStride[] = {
+ 1, // EfiCpuIoWidthUint8
+ 2, // EfiCpuIoWidthUint16
+ 4, // EfiCpuIoWidthUint32
+ 8, // EfiCpuIoWidthUint64
+ 0, // EfiCpuIoWidthFifoUint8
+ 0, // EfiCpuIoWidthFifoUint16
+ 0, // EfiCpuIoWidthFifoUint32
+ 0, // EfiCpuIoWidthFifoUint64
+ 1, // EfiCpuIoWidthFillUint8
+ 2, // EfiCpuIoWidthFillUint16
+ 4, // EfiCpuIoWidthFillUint32
+ 8 // EfiCpuIoWidthFillUint64
+};
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mOutStride[] = {
+ 1, // EfiCpuIoWidthUint8
+ 2, // EfiCpuIoWidthUint16
+ 4, // EfiCpuIoWidthUint32
+ 8, // EfiCpuIoWidthUint64
+ 1, // EfiCpuIoWidthFifoUint8
+ 2, // EfiCpuIoWidthFifoUint16
+ 4, // EfiCpuIoWidthFifoUint32
+ 8, // EfiCpuIoWidthFifoUint64
+ 0, // EfiCpuIoWidthFillUint8
+ 0, // EfiCpuIoWidthFillUint16
+ 0, // EfiCpuIoWidthFillUint32
+ 0 // EfiCpuIoWidthFillUint64
+};
+
+/**
+ Check parameters to a CPU I/O 2 Protocol service request.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The parameters for this request pass the checks.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+CpuIoCheckParameter (
+ IN BOOLEAN MmioOperation,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ UINT64 MaxCount;
+ UINT64 Limit;
+
+ //
+ // Check to see if Buffer is NULL
+ //
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check to see if Width is in the valid range
+ //
+ if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // For FIFO type, the target address won't increase during the access,
+ // so treat Count as 1
+ //
+ if ((Width >= EfiCpuIoWidthFifoUint8) && (Width <= EfiCpuIoWidthFifoUint64)) {
+ Count = 1;
+ }
+
+ //
+ // Check to see if Width is in the valid range for I/O Port operations
+ //
+ Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
+ if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check to see if Address is aligned
+ //
+ if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // Check to see if any address associated with this transfer exceeds the maximum
+ // allowed address. The maximum address implied by the parameters passed in is
+ // Address + Size * Count. If the following condition is met, then the transfer
+ // is not supported.
+ //
+ // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
+ //
+ // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
+ // can also be the maximum integer value supported by the CPU, this range
+ // check must be adjusted to avoid all overflow conditions.
+ //
+ // The following form of the range check is equivalent but assumes that
+ // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).
+ //
+ Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);
+ if (Count == 0) {
+ if (Address > Limit) {
+ return EFI_UNSUPPORTED;
+ }
+ } else {
+ MaxCount = RShiftU64 (Limit, Width);
+ if (MaxCount < (Count - 1)) {
+ return EFI_UNSUPPORTED;
+ }
+
+ if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
+ return EFI_UNSUPPORTED;
+ }
+ }
+
+ //
+ // Check to see if Buffer is aligned
+ //
+ if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) {
+ return EFI_UNSUPPORTED;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Reads memory-mapped registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[out] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuMemoryServiceRead (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ *Uint8Buffer = MmioRead8 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint64) {
+ *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Writes memory-mapped registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuMemoryServiceWrite (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ MmioWrite8 ((UINTN)Address, *Uint8Buffer);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+ } else if (OperationWidth == EfiCpuIoWidthUint64) {
+ MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Reads I/O registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[out] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuIoServiceRead (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Address += PcdGet64 (PcdPciIoTranslation);
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
+
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ *Uint8Buffer = MmioRead8 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Write I/O registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuIoServiceWrite (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ //
+ // Make sure the parameters are valid
+ //
+ Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Address += PcdGet64 (PcdPciIoTranslation);
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
+
+ for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ MmioWrite8 ((UINTN)Address, *Uint8Buffer);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+//
+// CPU I/O 2 Protocol instance
+//
+STATIC EFI_CPU_IO2_PROTOCOL mCpuMmio2 = {
+ {
+ CpuMemoryServiceRead,
+ CpuMemoryServiceWrite
+ },
+ {
+ CpuIoServiceRead,
+ CpuIoServiceWrite
+ }
+};
+
+/**
+ The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+ @retval other Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuMmio2Initialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mHandle,
+ &gEfiCpuIo2ProtocolGuid,
+ &mCpuMmio2,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
diff --git a/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf b/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
new file mode 100644
index 0000000000..32577be7ea
--- /dev/null
+++ b/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
@@ -0,0 +1,48 @@
+## @file
+# Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
+#
+# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+# Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 1.29
+ BASE_NAME = CpuMmio2Dxe
+ MODULE_UNI_FILE = CpuMmio2Dxe.uni
+ FILE_GUID = FBC36D76-CF22-2584-DBD8-85FF765BAEF1
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = CpuMmio2Initialize
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = ARM AARCH64 LOONGARCH64 RISCV64
+#
+
+[Sources]
+ CpuMmio2Dxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseLib
+ DebugLib
+ IoLib
+ PcdLib
+ UefiBootServicesTableLib
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation
+
+[Protocols]
+ gEfiCpuIo2ProtocolGuid ## PRODUCES
+
+[Depex]
+ TRUE
diff --git a/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.uni b/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.uni
new file mode 100644
index 0000000000..af3b1a656f
--- /dev/null
+++ b/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.uni
@@ -0,0 +1,18 @@
+// /** @file
+// Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
+//
+// Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
+//
+// Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+// Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Produces the CPU I/O 2 Protocol by using the services of the I/O Library"
+
+#string STR_MODULE_DESCRIPTION #language en-US "Produces the CPU I/O 2 Protocol by using the services of the I/O Library."
+
diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index 28eed85bce..10b33594e5 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -206,6 +206,7 @@ [Components.RISCV64]
UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
+ UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
[BuildOptions]
*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
--
2.27.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [edk2-devel] [PATCH v1 14/19] ArmVirtPkg: Enable CpuMmio2Dxe
2024-02-02 2:26 [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Chao Li
` (12 preceding siblings ...)
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 13/19] UefiCpuPkg: Add a new CPU IO 2 driver named CpuMmio2Dxe Chao Li
@ 2024-02-02 2:28 ` Chao Li
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 15/19] OvmfPkg/RiscVVirt: " Chao Li
` (5 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Chao Li @ 2024-02-02 2:28 UTC (permalink / raw)
To: devel
Cc: Ard Biesheuvel, Laszlo Ersek, Leif Lindholm, Sami Mujawar,
Gerd Hoffmann
CpuMmio2Dxe is supports MMIO, enable it.
Build-tested only (with "ArmVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
---
ArmVirtPkg/ArmVirtCloudHv.dsc | 2 +-
ArmVirtPkg/ArmVirtCloudHv.fdf | 2 +-
ArmVirtPkg/ArmVirtKvmTool.dsc | 2 +-
ArmVirtPkg/ArmVirtKvmTool.fdf | 2 +-
ArmVirtPkg/ArmVirtQemu.dsc | 2 +-
ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc | 2 +-
ArmVirtPkg/ArmVirtQemuKernel.dsc | 2 +-
7 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/ArmVirtPkg/ArmVirtCloudHv.dsc b/ArmVirtPkg/ArmVirtCloudHv.dsc
index 76c0d28544..5cb2a609b1 100644
--- a/ArmVirtPkg/ArmVirtCloudHv.dsc
+++ b/ArmVirtPkg/ArmVirtCloudHv.dsc
@@ -341,7 +341,7 @@ [Components.common]
#
# PCI support
#
- ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf {
+ UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf {
<LibraryClasses>
NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
}
diff --git a/ArmVirtPkg/ArmVirtCloudHv.fdf b/ArmVirtPkg/ArmVirtCloudHv.fdf
index 56d1ea6e8c..8554efc294 100644
--- a/ArmVirtPkg/ArmVirtCloudHv.fdf
+++ b/ArmVirtPkg/ArmVirtCloudHv.fdf
@@ -201,7 +201,7 @@ [FV.FvMain]
#
# PCI support
#
- INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ INF UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
diff --git a/ArmVirtPkg/ArmVirtKvmTool.dsc b/ArmVirtPkg/ArmVirtKvmTool.dsc
index cac4fe06d3..20da331966 100644
--- a/ArmVirtPkg/ArmVirtKvmTool.dsc
+++ b/ArmVirtPkg/ArmVirtKvmTool.dsc
@@ -372,7 +372,7 @@ [Components.common]
#
# PCI support
#
- ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf {
+ UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf {
<LibraryClasses>
NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
NULL|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpressLib.inf
diff --git a/ArmVirtPkg/ArmVirtKvmTool.fdf b/ArmVirtPkg/ArmVirtKvmTool.fdf
index 82aff47673..cdf756c112 100644
--- a/ArmVirtPkg/ArmVirtKvmTool.fdf
+++ b/ArmVirtPkg/ArmVirtKvmTool.fdf
@@ -195,7 +195,7 @@ [FV.FvMain]
#
# PCI support
#
- INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ INF UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
INF OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf
diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc
index cf306cac08..dbd2396c78 100644
--- a/ArmVirtPkg/ArmVirtQemu.dsc
+++ b/ArmVirtPkg/ArmVirtQemu.dsc
@@ -526,7 +526,7 @@ [Components.common]
#
# PCI support
#
- ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf {
+ UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf {
<LibraryClasses>
NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
}
diff --git a/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc b/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
index 9b3e37d5c9..c5d097ffb9 100644
--- a/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
+++ b/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
@@ -153,7 +153,7 @@ [FV.FvMain]
#
# PCI support
#
- INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ INF UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKernel.dsc
index c0d079e28d..6a6ecfc12a 100644
--- a/ArmVirtPkg/ArmVirtQemuKernel.dsc
+++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc
@@ -431,7 +431,7 @@ [Components.common]
#
# PCI support
#
- ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf {
+ UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf {
<LibraryClasses>
NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
}
--
2.27.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [edk2-devel] [PATCH v1 15/19] OvmfPkg/RiscVVirt: Enable CpuMmio2Dxe
2024-02-02 2:26 [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Chao Li
` (13 preceding siblings ...)
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 14/19] ArmVirtPkg: Enable CpuMmio2Dxe Chao Li
@ 2024-02-02 2:28 ` Chao Li
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 16/19] OvmfPkg/RiscVVirt: Remove PciCpuIo2Dxe from RiscVVirt Chao Li
` (4 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Chao Li @ 2024-02-02 2:28 UTC (permalink / raw)
To: devel; +Cc: Sunil V L, Andrei Warkentin
CpuMmio2Dxe is supports MMIO, enable it.
Build-tested only (with "RiscVVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 2 +-
OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
index 774dc81840..27f24648e8 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
+++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
@@ -433,7 +433,7 @@ [Components]
#
# PCI support
#
- OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf {
+ UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf {
<LibraryClasses>
NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
}
diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
index 8121b9e579..e579f5b9b7 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
+++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
@@ -184,7 +184,7 @@ [FV.DXEFV]
#
# PCI support
#
-INF OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+INF UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
--
2.27.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [edk2-devel] [PATCH v1 16/19] OvmfPkg/RiscVVirt: Remove PciCpuIo2Dxe from RiscVVirt
2024-02-02 2:26 [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Chao Li
` (14 preceding siblings ...)
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 15/19] OvmfPkg/RiscVVirt: " Chao Li
@ 2024-02-02 2:28 ` Chao Li
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 17/19] ArmVirtPkg: Move the FdtSerialPortAddressLib to OvmfPkg Chao Li
` (3 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Chao Li @ 2024-02-02 2:28 UTC (permalink / raw)
To: devel; +Cc: Sunil V L, Andrei Warkentin
CpuIo2Dxe is already used by RiscVVirt, so remove it.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 557 ------------------
.../RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 48 --
2 files changed, 605 deletions(-)
delete mode 100644 OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c
delete mode 100644 OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
diff --git a/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c b/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c
deleted file mode 100644
index f3bf07e631..0000000000
--- a/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c
+++ /dev/null
@@ -1,557 +0,0 @@
-/** @file
- Produces the CPU I/O 2 Protocol.
-
-Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
-Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
-Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
-
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiDxe.h>
-
-#include <Protocol/CpuIo2.h>
-
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-
-#define MAX_IO_PORT_ADDRESS 0xFFFF
-
-//
-// Handle for the CPU I/O 2 Protocol
-//
-STATIC EFI_HANDLE mHandle = NULL;
-
-//
-// Lookup table for increment values based on transfer widths
-//
-STATIC CONST UINT8 mInStride[] = {
- 1, // EfiCpuIoWidthUint8
- 2, // EfiCpuIoWidthUint16
- 4, // EfiCpuIoWidthUint32
- 8, // EfiCpuIoWidthUint64
- 0, // EfiCpuIoWidthFifoUint8
- 0, // EfiCpuIoWidthFifoUint16
- 0, // EfiCpuIoWidthFifoUint32
- 0, // EfiCpuIoWidthFifoUint64
- 1, // EfiCpuIoWidthFillUint8
- 2, // EfiCpuIoWidthFillUint16
- 4, // EfiCpuIoWidthFillUint32
- 8 // EfiCpuIoWidthFillUint64
-};
-
-//
-// Lookup table for increment values based on transfer widths
-//
-STATIC CONST UINT8 mOutStride[] = {
- 1, // EfiCpuIoWidthUint8
- 2, // EfiCpuIoWidthUint16
- 4, // EfiCpuIoWidthUint32
- 8, // EfiCpuIoWidthUint64
- 1, // EfiCpuIoWidthFifoUint8
- 2, // EfiCpuIoWidthFifoUint16
- 4, // EfiCpuIoWidthFifoUint32
- 8, // EfiCpuIoWidthFifoUint64
- 0, // EfiCpuIoWidthFillUint8
- 0, // EfiCpuIoWidthFillUint16
- 0, // EfiCpuIoWidthFillUint32
- 0 // EfiCpuIoWidthFillUint64
-};
-
-/**
- Check parameters to a CPU I/O 2 Protocol service request.
-
- The I/O operations are carried out exactly as requested. The caller is responsible
- for satisfying any alignment and I/O width restrictions that a PI System on a
- platform might require. For example on some platforms, width requests of
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
- be handled by the driver.
-
- @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation.
- @param[in] Width Signifies the width of the I/O or Memory operation.
- @param[in] Address The base address of the I/O operation.
- @param[in] Count The number of I/O operations to perform. The number of
- bytes moved is Width size * Count, starting at Address.
- @param[in] Buffer For read operations, the destination buffer to store the results.
- For write operations, the source buffer from which to write data.
-
- @retval EFI_SUCCESS The parameters for this request pass the checks.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
- @retval EFI_UNSUPPORTED The address range specified by Address, Width,
- and Count is not valid for this PI system.
-
-**/
-STATIC
-EFI_STATUS
-CpuIoCheckParameter (
- IN BOOLEAN MmioOperation,
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- UINT64 MaxCount;
- UINT64 Limit;
-
- //
- // Check to see if Buffer is NULL
- //
- if (Buffer == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Check to see if Width is in the valid range
- //
- if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // For FIFO type, the target address won't increase during the access,
- // so treat Count as 1
- //
- if ((Width >= EfiCpuIoWidthFifoUint8) && (Width <= EfiCpuIoWidthFifoUint64)) {
- Count = 1;
- }
-
- //
- // Check to see if Width is in the valid range for I/O Port operations
- //
- Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
- if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Check to see if Address is aligned
- //
- if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
- return EFI_UNSUPPORTED;
- }
-
- //
- // Check to see if any address associated with this transfer exceeds the maximum
- // allowed address. The maximum address implied by the parameters passed in is
- // Address + Size * Count. If the following condition is met, then the transfer
- // is not supported.
- //
- // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
- //
- // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
- // can also be the maximum integer value supported by the CPU, this range
- // check must be adjusted to avoid all overflow conditions.
- //
- // The following form of the range check is equivalent but assumes that
- // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).
- //
- Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);
- if (Count == 0) {
- if (Address > Limit) {
- return EFI_UNSUPPORTED;
- }
- } else {
- MaxCount = RShiftU64 (Limit, Width);
- if (MaxCount < (Count - 1)) {
- return EFI_UNSUPPORTED;
- }
-
- if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
- return EFI_UNSUPPORTED;
- }
- }
-
- //
- // Check to see if Buffer is aligned
- //
- if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) {
- return EFI_UNSUPPORTED;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Reads memory-mapped registers.
-
- The I/O operations are carried out exactly as requested. The caller is responsible
- for satisfying any alignment and I/O width restrictions that a PI System on a
- platform might require. For example on some platforms, width requests of
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
- be handled by the driver.
-
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
- each of the Count operations that is performed.
-
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
- incremented for each of the Count operations that is performed. The read or
- write operation is performed Count times on the same Address.
-
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
- incremented for each of the Count operations that is performed. The read or
- write operation is performed Count times from the first element of Buffer.
-
- @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
- @param[in] Width Signifies the width of the I/O or Memory operation.
- @param[in] Address The base address of the I/O operation.
- @param[in] Count The number of I/O operations to perform. The number of
- bytes moved is Width size * Count, starting at Address.
- @param[out] Buffer For read operations, the destination buffer to store the results.
- For write operations, the source buffer from which to write data.
-
- @retval EFI_SUCCESS The data was read from or written to the PI system.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
- @retval EFI_UNSUPPORTED The address range specified by Address, Width,
- and Count is not valid for this PI system.
-
-**/
-STATIC
-EFI_STATUS
-EFIAPI
-CpuMemoryServiceRead (
- IN EFI_CPU_IO2_PROTOCOL *This,
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- OUT VOID *Buffer
- )
-{
- EFI_STATUS Status;
- UINT8 InStride;
- UINT8 OutStride;
- EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
- UINT8 *Uint8Buffer;
-
- Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- //
- // Select loop based on the width of the transfer
- //
- InStride = mInStride[Width];
- OutStride = mOutStride[Width];
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
- for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
- if (OperationWidth == EfiCpuIoWidthUint8) {
- *Uint8Buffer = MmioRead8 ((UINTN)Address);
- } else if (OperationWidth == EfiCpuIoWidthUint16) {
- *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
- } else if (OperationWidth == EfiCpuIoWidthUint32) {
- *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
- } else if (OperationWidth == EfiCpuIoWidthUint64) {
- *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
- }
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Writes memory-mapped registers.
-
- The I/O operations are carried out exactly as requested. The caller is responsible
- for satisfying any alignment and I/O width restrictions that a PI System on a
- platform might require. For example on some platforms, width requests of
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
- be handled by the driver.
-
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
- each of the Count operations that is performed.
-
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
- incremented for each of the Count operations that is performed. The read or
- write operation is performed Count times on the same Address.
-
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
- incremented for each of the Count operations that is performed. The read or
- write operation is performed Count times from the first element of Buffer.
-
- @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
- @param[in] Width Signifies the width of the I/O or Memory operation.
- @param[in] Address The base address of the I/O operation.
- @param[in] Count The number of I/O operations to perform. The number of
- bytes moved is Width size * Count, starting at Address.
- @param[in] Buffer For read operations, the destination buffer to store the results.
- For write operations, the source buffer from which to write data.
-
- @retval EFI_SUCCESS The data was read from or written to the PI system.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
- @retval EFI_UNSUPPORTED The address range specified by Address, Width,
- and Count is not valid for this PI system.
-
-**/
-STATIC
-EFI_STATUS
-EFIAPI
-CpuMemoryServiceWrite (
- IN EFI_CPU_IO2_PROTOCOL *This,
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- EFI_STATUS Status;
- UINT8 InStride;
- UINT8 OutStride;
- EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
- UINT8 *Uint8Buffer;
-
- Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- //
- // Select loop based on the width of the transfer
- //
- InStride = mInStride[Width];
- OutStride = mOutStride[Width];
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
- for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
- if (OperationWidth == EfiCpuIoWidthUint8) {
- MmioWrite8 ((UINTN)Address, *Uint8Buffer);
- } else if (OperationWidth == EfiCpuIoWidthUint16) {
- MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
- } else if (OperationWidth == EfiCpuIoWidthUint32) {
- MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
- } else if (OperationWidth == EfiCpuIoWidthUint64) {
- MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
- }
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Reads I/O registers.
-
- The I/O operations are carried out exactly as requested. The caller is responsible
- for satisfying any alignment and I/O width restrictions that a PI System on a
- platform might require. For example on some platforms, width requests of
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
- be handled by the driver.
-
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
- each of the Count operations that is performed.
-
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
- incremented for each of the Count operations that is performed. The read or
- write operation is performed Count times on the same Address.
-
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
- incremented for each of the Count operations that is performed. The read or
- write operation is performed Count times from the first element of Buffer.
-
- @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
- @param[in] Width Signifies the width of the I/O or Memory operation.
- @param[in] Address The base address of the I/O operation.
- @param[in] Count The number of I/O operations to perform. The number of
- bytes moved is Width size * Count, starting at Address.
- @param[out] Buffer For read operations, the destination buffer to store the results.
- For write operations, the source buffer from which to write data.
-
- @retval EFI_SUCCESS The data was read from or written to the PI system.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
- @retval EFI_UNSUPPORTED The address range specified by Address, Width,
- and Count is not valid for this PI system.
-
-**/
-STATIC
-EFI_STATUS
-EFIAPI
-CpuIoServiceRead (
- IN EFI_CPU_IO2_PROTOCOL *This,
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- OUT VOID *Buffer
- )
-{
- EFI_STATUS Status;
- UINT8 InStride;
- UINT8 OutStride;
- EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
- UINT8 *Uint8Buffer;
-
- Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- Address += PcdGet64 (PcdPciIoTranslation);
-
- //
- // Select loop based on the width of the transfer
- //
- InStride = mInStride[Width];
- OutStride = mOutStride[Width];
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
-
- for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
- if (OperationWidth == EfiCpuIoWidthUint8) {
- *Uint8Buffer = MmioRead8 ((UINTN)Address);
- } else if (OperationWidth == EfiCpuIoWidthUint16) {
- *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
- } else if (OperationWidth == EfiCpuIoWidthUint32) {
- *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
- }
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Write I/O registers.
-
- The I/O operations are carried out exactly as requested. The caller is responsible
- for satisfying any alignment and I/O width restrictions that a PI System on a
- platform might require. For example on some platforms, width requests of
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
- be handled by the driver.
-
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
- each of the Count operations that is performed.
-
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
- incremented for each of the Count operations that is performed. The read or
- write operation is performed Count times on the same Address.
-
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
- incremented for each of the Count operations that is performed. The read or
- write operation is performed Count times from the first element of Buffer.
-
- @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
- @param[in] Width Signifies the width of the I/O or Memory operation.
- @param[in] Address The base address of the I/O operation.
- @param[in] Count The number of I/O operations to perform. The number of
- bytes moved is Width size * Count, starting at Address.
- @param[in] Buffer For read operations, the destination buffer to store the results.
- For write operations, the source buffer from which to write data.
-
- @retval EFI_SUCCESS The data was read from or written to the PI system.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
- @retval EFI_UNSUPPORTED The address range specified by Address, Width,
- and Count is not valid for this PI system.
-
-**/
-STATIC
-EFI_STATUS
-EFIAPI
-CpuIoServiceWrite (
- IN EFI_CPU_IO2_PROTOCOL *This,
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- EFI_STATUS Status;
- UINT8 InStride;
- UINT8 OutStride;
- EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
- UINT8 *Uint8Buffer;
-
- //
- // Make sure the parameters are valid
- //
- Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- Address += PcdGet64 (PcdPciIoTranslation);
-
- //
- // Select loop based on the width of the transfer
- //
- InStride = mInStride[Width];
- OutStride = mOutStride[Width];
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
-
- for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
- if (OperationWidth == EfiCpuIoWidthUint8) {
- MmioWrite8 ((UINTN)Address, *Uint8Buffer);
- } else if (OperationWidth == EfiCpuIoWidthUint16) {
- MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
- } else if (OperationWidth == EfiCpuIoWidthUint32) {
- MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
- }
- }
-
- return EFI_SUCCESS;
-}
-
-//
-// CPU I/O 2 Protocol instance
-//
-STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
- {
- CpuMemoryServiceRead,
- CpuMemoryServiceWrite
- },
- {
- CpuIoServiceRead,
- CpuIoServiceWrite
- }
-};
-
-/**
- The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
-
- @param[in] ImageHandle The firmware allocated handle for the EFI image.
- @param[in] SystemTable A pointer to the EFI System Table.
-
- @retval EFI_SUCCESS The entry point is executed successfully.
- @retval other Some error occurs when executing this entry point.
-
-**/
-EFI_STATUS
-EFIAPI
-PciCpuIo2Initialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_STATUS Status;
-
- ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
- Status = gBS->InstallMultipleProtocolInterfaces (
- &mHandle,
- &gEfiCpuIo2ProtocolGuid,
- &mCpuIo2,
- NULL
- );
- ASSERT_EFI_ERROR (Status);
-
- return Status;
-}
diff --git a/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf b/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
deleted file mode 100644
index 4f78cfa406..0000000000
--- a/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+++ /dev/null
@@ -1,48 +0,0 @@
-## @file
-# Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
-#
-# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
-# Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
-# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-[Defines]
- INF_VERSION = 0x0001001B
- BASE_NAME = PciCpuIo2Dxe
- FILE_GUID = 9BD3C765-2579-4CF0-9349-D77205565030
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = PciCpuIo2Initialize
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = RISCV64
-#
-
-[Sources]
- PciCpuIo2Dxe.c
-
-[Packages]
- OvmfPkg/OvmfPkg.dec
- MdePkg/MdePkg.dec
-
-[LibraryClasses]
- UefiDriverEntryPoint
- BaseLib
- DebugLib
- IoLib
- PcdLib
- UefiBootServicesTableLib
-
-[Pcd]
- gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation
-
-[Protocols]
- gEfiCpuIo2ProtocolGuid ## PRODUCES
-
-[Depex]
- TRUE
--
2.27.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [edk2-devel] [PATCH v1 17/19] ArmVirtPkg: Move the FdtSerialPortAddressLib to OvmfPkg
2024-02-02 2:26 [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Chao Li
` (15 preceding siblings ...)
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 16/19] OvmfPkg/RiscVVirt: Remove PciCpuIo2Dxe from RiscVVirt Chao Li
@ 2024-02-02 2:28 ` Chao Li
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 18/19] ArmVirtPkg: Move two PCD variables into OvmfPkg Chao Li
` (2 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Chao Li @ 2024-02-02 2:28 UTC (permalink / raw)
To: devel
Cc: Ard Biesheuvel, Laszlo Ersek, Leif Lindholm, Sami Mujawar,
Gerd Hoffmann, Jiewen Yao
Move the FdtSerialPortAddressLib to Ovmfpkg so that other ARCH can
easily use it.
Build-tested only (with "ArmVirtQemu.dsc and OvmfPkgX64.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
---
ArmVirtPkg/ArmVirt.dsc.inc | 2 +-
ArmVirtPkg/ArmVirtPkg.dec | 1 -
.../Include/Library/FdtSerialPortAddressLib.h | 0
.../Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.c | 0
.../FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf | 2 +-
OvmfPkg/OvmfPkg.dec | 4 ++++
6 files changed, 6 insertions(+), 3 deletions(-)
rename {ArmVirtPkg => OvmfPkg}/Include/Library/FdtSerialPortAddressLib.h (100%)
rename {ArmVirtPkg => OvmfPkg}/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.c (100%)
rename {ArmVirtPkg => OvmfPkg}/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf (90%)
diff --git a/ArmVirtPkg/ArmVirt.dsc.inc b/ArmVirtPkg/ArmVirt.dsc.inc
index 9b23ef97ec..2bc6a29eb1 100644
--- a/ArmVirtPkg/ArmVirt.dsc.inc
+++ b/ArmVirtPkg/ArmVirt.dsc.inc
@@ -122,7 +122,7 @@ [LibraryClasses.common]
# ARM PL011 UART Driver
PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf
SerialPortLib|ArmVirtPkg/Library/FdtPL011SerialPortLib/FdtPL011SerialPortLib.inf
- FdtSerialPortAddressLib|ArmVirtPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
+ FdtSerialPortAddressLib|OvmfPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
#PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
diff --git a/ArmVirtPkg/ArmVirtPkg.dec b/ArmVirtPkg/ArmVirtPkg.dec
index 05d2d36c1d..a658c91031 100644
--- a/ArmVirtPkg/ArmVirtPkg.dec
+++ b/ArmVirtPkg/ArmVirtPkg.dec
@@ -27,7 +27,6 @@ [Includes.common]
[LibraryClasses]
ArmVirtMemInfoLib|Include/Library/ArmVirtMemInfoLib.h
- FdtSerialPortAddressLib|Include/Library/FdtSerialPortAddressLib.h
[Guids.common]
gArmVirtTokenSpaceGuid = { 0x0B6F5CA7, 0x4F53, 0x445A, { 0xB7, 0x6E, 0x2E, 0x36, 0x5B, 0x80, 0x63, 0x66 } }
diff --git a/ArmVirtPkg/Include/Library/FdtSerialPortAddressLib.h b/OvmfPkg/Include/Library/FdtSerialPortAddressLib.h
similarity index 100%
rename from ArmVirtPkg/Include/Library/FdtSerialPortAddressLib.h
rename to OvmfPkg/Include/Library/FdtSerialPortAddressLib.h
diff --git a/ArmVirtPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.c b/OvmfPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.c
similarity index 100%
rename from ArmVirtPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.c
rename to OvmfPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.c
diff --git a/ArmVirtPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf b/OvmfPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
similarity index 90%
rename from ArmVirtPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
rename to OvmfPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
index ae6d0d374b..e27742e9fa 100644
--- a/ArmVirtPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
+++ b/OvmfPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
@@ -18,9 +18,9 @@ [Sources]
FdtSerialPortAddressLib.c
[Packages]
- ArmVirtPkg/ArmVirtPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
+ OvmfPkg/OvmfPkg.dec
[LibraryClasses]
BaseLib
diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec
index 7bc2bf1674..13e69e6648 100644
--- a/OvmfPkg/OvmfPkg.dec
+++ b/OvmfPkg/OvmfPkg.dec
@@ -29,6 +29,10 @@ [LibraryClasses]
## @libraryclass Verify blobs read from the VMM
BlobVerifierLib|Include/Library/BlobVerifierLib.h
+ ## @libraryclass FdtSerialPortAddressLib
+ #
+ FdtSerialPortAddressLib|Include/Library/FdtSerialPortAddressLib.h
+
## @libraryclass Loads and boots a Linux kernel image
#
LoadLinuxLib|Include/Library/LoadLinuxLib.h
--
2.27.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [edk2-devel] [PATCH v1 18/19] ArmVirtPkg: Move two PCD variables into OvmfPkg
2024-02-02 2:26 [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Chao Li
` (16 preceding siblings ...)
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 17/19] ArmVirtPkg: Move the FdtSerialPortAddressLib to OvmfPkg Chao Li
@ 2024-02-02 2:28 ` Chao Li
2024-02-02 2:29 ` [edk2-devel] [PATCH v1 19/19] ArmVirtPkg: Move PlatformBootManagerLib to OvmfPkg Chao Li
2024-02-02 14:56 ` [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Laszlo Ersek
19 siblings, 0 replies; 27+ messages in thread
From: Chao Li @ 2024-02-02 2:28 UTC (permalink / raw)
To: devel
Cc: Ard Biesheuvel, Laszlo Ersek, Leif Lindholm, Sami Mujawar,
Gerd Hoffmann, Jiewen Yao
Move the PcdTerminalTypeGuidBuffer and PcdUninstallMemAttrProtocol into
OvmfPkg so other ARCH can easily use it.
Build-tested only (with "ArmVirtQemu.dsc and OvmfPkgX64.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
---
ArmVirtPkg/ArmVirtPkg.dec | 13 -------------
ArmVirtPkg/ArmVirtQemu.dsc | 2 +-
ArmVirtPkg/ArmVirtQemuKernel.dsc | 2 +-
.../PlatformBootManagerLib.inf | 5 ++---
OvmfPkg/OvmfPkg.dec | 13 +++++++++++++
5 files changed, 17 insertions(+), 18 deletions(-)
diff --git a/ArmVirtPkg/ArmVirtPkg.dec b/ArmVirtPkg/ArmVirtPkg.dec
index a658c91031..6aa5ea05f4 100644
--- a/ArmVirtPkg/ArmVirtPkg.dec
+++ b/ArmVirtPkg/ArmVirtPkg.dec
@@ -41,21 +41,8 @@ [PcdsFeatureFlag]
gArmVirtTokenSpaceGuid.PcdTpm2SupportEnabled|FALSE|BOOLEAN|0x00000004
[PcdsFixedAtBuild, PcdsPatchableInModule]
- #
- # Binary representation of the GUID that determines the terminal type. The
- # size must be exactly 16 bytes. The default value corresponds to
- # EFI_VT_100_GUID.
- #
- gArmVirtTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x65, 0x60, 0xA6, 0xDF, 0x19, 0xB4, 0xD3, 0x11, 0x9A, 0x2D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}|VOID*|0x00000007
-
##
# This is the physical address of Rsdp which is the core struct of Acpi.
# Cloud Hypervisor has no other way to pass Rsdp address to the guest except use a PCD.
#
gArmVirtTokenSpaceGuid.PcdCloudHvAcpiRsdpBaseAddress|0x0|UINT64|0x00000005
-
- ##
- # Whether the EFI memory attributes protocol should be uninstalled before
- # invoking the OS loader. This may be needed to work around problematic
- # builds of shim that use the protocol incorrectly.
- gArmVirtTokenSpaceGuid.PcdUninstallMemAttrProtocol|FALSE|BOOLEAN|0x00000006
diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc
index dbd2396c78..147180f645 100644
--- a/ArmVirtPkg/ArmVirtQemu.dsc
+++ b/ArmVirtPkg/ArmVirtQemu.dsc
@@ -182,7 +182,7 @@ [PcdsFixedAtBuild.common]
!if $(TTY_TERMINAL) == TRUE
gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
# Set terminal type to TtyTerm, the value encoded is EFI_TTY_TERM_GUID
- gArmVirtTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x80, 0x6d, 0x91, 0x7d, 0xb1, 0x5b, 0x8c, 0x45, 0xa4, 0x8f, 0xe2, 0x5f, 0xdd, 0x51, 0xef, 0x94}
+ gUefiOvmfPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x80, 0x6d, 0x91, 0x7d, 0xb1, 0x5b, 0x8c, 0x45, 0xa4, 0x8f, 0xe2, 0x5f, 0xdd, 0x51, 0xef, 0x94}
!else
gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|1
!endif
diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKernel.dsc
index 6a6ecfc12a..c22a422353 100644
--- a/ArmVirtPkg/ArmVirtQemuKernel.dsc
+++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc
@@ -147,7 +147,7 @@ [PcdsFixedAtBuild.common]
!if $(TTY_TERMINAL) == TRUE
gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
# Set terminal type to TtyTerm, the value encoded is EFI_TTY_TERM_GUID
- gArmVirtTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x80, 0x6d, 0x91, 0x7d, 0xb1, 0x5b, 0x8c, 0x45, 0xa4, 0x8f, 0xe2, 0x5f, 0xdd, 0x51, 0xef, 0x94}
+ gUefiOvmfPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x80, 0x6d, 0x91, 0x7d, 0xb1, 0x5b, 0x8c, 0x45, 0xa4, 0x8f, 0xe2, 0x5f, 0xdd, 0x51, 0xef, 0x94}
!else
gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|1
!endif
diff --git a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
index 70e4ebf94a..8e7cd5605f 100644
--- a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -29,7 +29,6 @@ [Sources]
QemuKernel.c
[Packages]
- ArmVirtPkg/ArmVirtPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
OvmfPkg/OvmfPkg.dec
@@ -56,15 +55,15 @@ [LibraryClasses]
UefiRuntimeServicesTableLib
[FixedPcd]
- gArmVirtTokenSpaceGuid.PcdUninstallMemAttrProtocol
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
+ gUefiOvmfPkgTokenSpaceGuid.PcdUninstallMemAttrProtocol
[Pcd]
- gArmVirtTokenSpaceGuid.PcdTerminalTypeGuidBuffer
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
+ gUefiOvmfPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer
[Guids]
gEfiEndOfDxeEventGroupGuid
diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec
index 13e69e6648..fbc81e4c80 100644
--- a/OvmfPkg/OvmfPkg.dec
+++ b/OvmfPkg/OvmfPkg.dec
@@ -405,6 +405,19 @@ [PcdsFixedAtBuild, PcdsPatchableInModule]
#
gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeAllocationPadding|256|UINT32|0x6f
+ #
+ # Binary representation of the GUID that determines the terminal type. The
+ # size must be exactly 16 bytes. The default value corresponds to
+ # EFI_VT_100_GUID.
+ #
+ gUefiOvmfPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x65, 0x60, 0xA6, 0xDF, 0x19, 0xB4, 0xD3, 0x11, 0x9A, 0x2D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}|VOID*|0x66
+
+ ##
+ # Whether the EFI memory attributes protocol should be uninstalled before
+ # invoking the OS loader. This may be needed to work around problematic
+ # builds of shim that use the protocol incorrectly.
+ gUefiOvmfPkgTokenSpaceGuid.PcdUninstallMemAttrProtocol|FALSE|BOOLEAN|0x67
+
[PcdsFeatureFlag]
gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0x1c
gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN|0x1d
--
2.27.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [edk2-devel] [PATCH v1 19/19] ArmVirtPkg: Move PlatformBootManagerLib to OvmfPkg
2024-02-02 2:26 [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Chao Li
` (17 preceding siblings ...)
2024-02-02 2:28 ` [edk2-devel] [PATCH v1 18/19] ArmVirtPkg: Move two PCD variables into OvmfPkg Chao Li
@ 2024-02-02 2:29 ` Chao Li
2024-02-02 14:56 ` [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Laszlo Ersek
19 siblings, 0 replies; 27+ messages in thread
From: Chao Li @ 2024-02-02 2:29 UTC (permalink / raw)
To: devel
Cc: Ard Biesheuvel, Laszlo Ersek, Leif Lindholm, Sami Mujawar,
Gerd Hoffmann, Jiewen Yao
Moved the PlatformBootManagerLib to OvmfPkg and renamed to
PlatformBootManagerLibLight for easy use by other ARCH.
Build-tested only (with "ArmVirtQemu.dsc and OvmfPkgX64.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4663
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Lazlo Ersek <lersek@redhat.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
---
ArmVirtPkg/ArmVirtPkg.ci.yaml | 1 -
ArmVirtPkg/ArmVirtQemu.dsc | 2 +-
ArmVirtPkg/ArmVirtQemuKernel.dsc | 2 +-
.../Library/PlatformBootManagerLibLight}/PlatformBm.c | 0
.../Library/PlatformBootManagerLibLight}/PlatformBm.h | 0
.../PlatformBootManagerLibLight}/PlatformBootManagerLib.inf | 0
.../Library/PlatformBootManagerLibLight}/QemuKernel.c | 0
7 files changed, 2 insertions(+), 3 deletions(-)
rename {ArmVirtPkg/Library/PlatformBootManagerLib => OvmfPkg/Library/PlatformBootManagerLibLight}/PlatformBm.c (100%)
rename {ArmVirtPkg/Library/PlatformBootManagerLib => OvmfPkg/Library/PlatformBootManagerLibLight}/PlatformBm.h (100%)
rename {ArmVirtPkg/Library/PlatformBootManagerLib => OvmfPkg/Library/PlatformBootManagerLibLight}/PlatformBootManagerLib.inf (100%)
rename {ArmVirtPkg/Library/PlatformBootManagerLib => OvmfPkg/Library/PlatformBootManagerLibLight}/QemuKernel.c (100%)
diff --git a/ArmVirtPkg/ArmVirtPkg.ci.yaml b/ArmVirtPkg/ArmVirtPkg.ci.yaml
index 506b0e72f0..b186d4eb42 100644
--- a/ArmVirtPkg/ArmVirtPkg.ci.yaml
+++ b/ArmVirtPkg/ArmVirtPkg.ci.yaml
@@ -24,7 +24,6 @@
],
## Both file path and directory path are accepted.
"IgnoreFiles": [
- "Library/PlatformBootManagerLib/PlatformBm.c"
]
},
## options defined .pytool/Plugin/CompilerPlugin
diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc
index 147180f645..e48c75b5e9 100644
--- a/ArmVirtPkg/ArmVirtQemu.dsc
+++ b/ArmVirtPkg/ArmVirtQemu.dsc
@@ -70,7 +70,7 @@ [LibraryClasses.common]
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
- PlatformBootManagerLib|ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+ PlatformBootManagerLib|OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBootManagerLib.inf
PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrintScLib.inf
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf
diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKernel.dsc
index c22a422353..668a65ba64 100644
--- a/ArmVirtPkg/ArmVirtQemuKernel.dsc
+++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc
@@ -69,7 +69,7 @@ [LibraryClasses.common]
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
- PlatformBootManagerLib|ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+ PlatformBootManagerLib|OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBootManagerLib.inf
PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrintScLib.inf
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf
diff --git a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.c b/OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBm.c
similarity index 100%
rename from ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.c
rename to OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBm.c
diff --git a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.h b/OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBm.h
similarity index 100%
rename from ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.h
rename to OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBm.h
diff --git a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBootManagerLib.inf
similarity index 100%
rename from ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
rename to OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBootManagerLib.inf
diff --git a/ArmVirtPkg/Library/PlatformBootManagerLib/QemuKernel.c b/OvmfPkg/Library/PlatformBootManagerLibLight/QemuKernel.c
similarity index 100%
rename from ArmVirtPkg/Library/PlatformBootManagerLib/QemuKernel.c
rename to OvmfPkg/Library/PlatformBootManagerLibLight/QemuKernel.c
--
2.27.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines
2024-02-02 2:26 [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Chao Li
` (18 preceding siblings ...)
2024-02-02 2:29 ` [edk2-devel] [PATCH v1 19/19] ArmVirtPkg: Move PlatformBootManagerLib to OvmfPkg Chao Li
@ 2024-02-02 14:56 ` Laszlo Ersek
2024-02-02 15:17 ` Ni, Ray
19 siblings, 1 reply; 27+ messages in thread
From: Laszlo Ersek @ 2024-02-02 14:56 UTC (permalink / raw)
To: devel, lichao
Cc: Michael D Kinney, Liming Gao, Zhiguang Liu, Leif Lindholm,
Ard Biesheuvel, Abner Chang, Sami Mujawar, Gerd Hoffmann, Ray Ni,
Rahul Kumar, Jiewen Yao, Sunil V L, Andrei Warkentin,
Dongyan Qian
On 2/2/24 03:26, Chao Li wrote:
> This series is part 1 of enabling LoongArch64 virtual machine.
>
> Added LoongArch helper functions and defines in MdePkg, added LoongArch
> CPU IO width in EmbeddedPkg, moved some libraries and PCDs from
> ArmVirtPkg to OvmfPkg for easiser use by other ARCHs, added a new CPU IO2
> driver named CpuMmio2Dxe in UefiCpuPkg, for non-IO port implement CPUs.
I think this series is good to go; fully reviewed, so we can merge it
during (not just before) the soft feature freeze period.
Ray, can you confirm you are OK with this version? You made some
comments under v8 that make me a bit uncertain.
Laszlo
>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> Cc: Leif Lindholm <quic_llindhol@quicinc.com>
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> Cc: Abner Chang <abner.chang@amd.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Leif Lindholm <quic_llindhol@quicinc.com>
> Cc: Sami Mujawar <sami.mujawar@arm.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Sunil V L <sunilvl@ventanamicro.com>
> Cc: Andrei Warkentin <andrei.warkentin@intel.com>
> Cc: Dongyan Qian <qiandongyan@loongson.cn>
>
> Chao Li (19):
> MdePkg: Add the header file named Csr.h for LoongArch64
> MdePkg: Add LoongArch64 FPU function set into BaseCpuLib
> MdePkg: Add LoongArch64 exception function set into BaseLib
> MdePkg: Add LoongArch64 local interrupt function set into BaseLib
> MdePkg: Add LoongArch Cpucfg function
> MdePkg: Add read stable counter operation for LoongArch
> MdePkg: Add CSR operation for LoongArch
> MdePkg: Add IOCSR operation for LoongArch
> MdePkg: Add a new library named PeiServicesTablePointerLibKs0
> MdePkg: Add some comments for LoongArch exceptions
> EmbeddedPkg: Add PcdPrePiCpuIoSize width for LOONGARCH64
> ArmVirtPkg: Move PCD of FDT base address and FDT padding to OvmfPkg
> UefiCpuPkg: Add a new CPU IO 2 driver named CpuMmio2Dxe
> ArmVirtPkg: Enable CpuMmio2Dxe
> OvmfPkg/RiscVVirt: Enable CpuMmio2Dxe
> OvmfPkg/RiscVVirt: Remove PciCpuIo2Dxe from RiscVVirt
> ArmVirtPkg: Move the FdtSerialPortAddressLib to OvmfPkg
> ArmVirtPkg: Move two PCD variables into OvmfPkg
> ArmVirtPkg: Move PlatformBootManagerLib to OvmfPkg
>
> ArmVirtPkg/ArmVirt.dsc.inc | 2 +-
> ArmVirtPkg/ArmVirtCloudHv.dsc | 4 +-
> ArmVirtPkg/ArmVirtCloudHv.fdf | 2 +-
> ArmVirtPkg/ArmVirtKvmTool.dsc | 4 +-
> ArmVirtPkg/ArmVirtKvmTool.fdf | 2 +-
> ArmVirtPkg/ArmVirtPkg.ci.yaml | 1 -
> ArmVirtPkg/ArmVirtPkg.dec | 28 -
> ArmVirtPkg/ArmVirtQemu.dsc | 8 +-
> ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc | 2 +-
> ArmVirtPkg/ArmVirtQemuKernel.dsc | 8 +-
> ArmVirtPkg/ArmVirtXen.dsc | 2 +-
> .../ArmVirtPsciResetSystemPeiLib.inf | 3 +-
> .../CloudHvVirtMemInfoPeiLib.inf | 3 +-
> .../DebugLibFdtPL011UartFlash.inf | 3 +-
> .../EarlyFdt16550SerialPortHookLib.inf | 3 +-
> .../EarlyFdtPL011SerialPortLib.inf | 3 +-
> .../KvmtoolPlatformPeiLib.inf | 5 +-
> .../Library/PlatformPeiLib/PlatformPeiLib.inf | 10 +-
> .../QemuVirtMemInfoPeiLib.inf | 3 +-
> .../PrePi/ArmVirtPrePiUniCoreRelocatable.inf | 3 +-
> EmbeddedPkg/EmbeddedPkg.dec | 3 +
> MdePkg/Include/Library/BaseLib.h | 221 +++++++
> MdePkg/Include/Library/CpuLib.h | 43 +-
> .../Library/PeiServicesTablePointerLib.h | 9 +-
> MdePkg/Include/Protocol/DebugSupport.h | 14 +
> MdePkg/Include/Register/LoongArch64/Cpucfg.h | 565 ++++++++++++++++++
> MdePkg/Include/Register/LoongArch64/Csr.h | 263 ++++++++
> MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 7 +-
> .../Library/BaseCpuLib/LoongArch/DisableFpu.S | 17 +
> .../Library/BaseCpuLib/LoongArch/EnableFpu.S | 17 +
> .../BaseCpuLib/LoongArch/InitializeFpu.S | 51 ++
> MdePkg/Library/BaseLib/BaseLib.inf | 6 +
> MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S | 422 +++++++++++++
> MdePkg/Library/BaseLib/LoongArch64/Cpucfg.S | 26 +
> MdePkg/Library/BaseLib/LoongArch64/Csr.c | 81 +++
> .../BaseLib/LoongArch64/DisableInterrupts.S | 22 +-
> .../BaseLib/LoongArch64/EnableInterrupts.S | 22 +-
> .../BaseLib/LoongArch64/ExceptionBase.S | 41 ++
> MdePkg/Library/BaseLib/LoongArch64/IoCsr.S | 120 ++++
> .../BaseLib/LoongArch64/ReadStableCounter.S | 24 +
> .../PeiServicesTablePointer.c | 87 +++
> .../PeiServicesTablePointerLibKs0.inf | 37 ++
> .../PeiServicesTablePointerLibKs0.uni | 20 +
> MdePkg/MdePkg.ci.yaml | 3 +-
> MdePkg/MdePkg.dsc | 3 +
> .../Include/Library/FdtSerialPortAddressLib.h | 0
> .../FdtSerialPortAddressLib.c | 0
> .../FdtSerialPortAddressLib.inf | 2 +-
> .../PlatformBootManagerLibLight}/PlatformBm.c | 0
> .../PlatformBootManagerLibLight}/PlatformBm.h | 0
> .../PlatformBootManagerLib.inf | 5 +-
> .../PlatformBootManagerLibLight}/QemuKernel.c | 0
> OvmfPkg/OvmfPkg.dec | 32 +
> OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 2 +-
> OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 2 +-
> .../CpuMmio2Dxe/CpuMmio2Dxe.c | 8 +-
> .../CpuMmio2Dxe/CpuMmio2Dxe.inf | 16 +-
> UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.uni | 18 +
> UefiCpuPkg/UefiCpuPkg.dsc | 1 +
> 59 files changed, 2209 insertions(+), 100 deletions(-)
> create mode 100644 MdePkg/Include/Register/LoongArch64/Cpucfg.h
> create mode 100644 MdePkg/Include/Register/LoongArch64/Csr.h
> create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/DisableFpu.S
> create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/EnableFpu.S
> create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/InitializeFpu.S
> create mode 100644 MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S
> create mode 100644 MdePkg/Library/BaseLib/LoongArch64/Cpucfg.S
> create mode 100644 MdePkg/Library/BaseLib/LoongArch64/Csr.c
> create mode 100644 MdePkg/Library/BaseLib/LoongArch64/ExceptionBase.S
> create mode 100644 MdePkg/Library/BaseLib/LoongArch64/IoCsr.S
> create mode 100644 MdePkg/Library/BaseLib/LoongArch64/ReadStableCounter.S
> create mode 100644 MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointer.c
> create mode 100644 MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointerLibKs0.inf
> create mode 100644 MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointerLibKs0.uni
> rename {ArmVirtPkg => OvmfPkg}/Include/Library/FdtSerialPortAddressLib.h (100%)
> rename {ArmVirtPkg => OvmfPkg}/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.c (100%)
> rename {ArmVirtPkg => OvmfPkg}/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf (90%)
> rename {ArmVirtPkg/Library/PlatformBootManagerLib => OvmfPkg/Library/PlatformBootManagerLibLight}/PlatformBm.c (100%)
> rename {ArmVirtPkg/Library/PlatformBootManagerLib => OvmfPkg/Library/PlatformBootManagerLibLight}/PlatformBm.h (100%)
> rename {ArmVirtPkg/Library/PlatformBootManagerLib => OvmfPkg/Library/PlatformBootManagerLibLight}/PlatformBootManagerLib.inf (89%)
> rename {ArmVirtPkg/Library/PlatformBootManagerLib => OvmfPkg/Library/PlatformBootManagerLibLight}/QemuKernel.c (100%)
> rename OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c => UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c (96%)
> rename OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf => UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf (61%)
> create mode 100644 UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.uni
>
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^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines
2024-02-02 14:56 ` [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines Laszlo Ersek
@ 2024-02-02 15:17 ` Ni, Ray
2024-02-02 16:14 ` Laszlo Ersek
0 siblings, 1 reply; 27+ messages in thread
From: Ni, Ray @ 2024-02-02 15:17 UTC (permalink / raw)
To: Laszlo Ersek, devel@edk2.groups.io, lichao@loongson.cn
Cc: Kinney, Michael D, Liming Gao, Liu, Zhiguang, Leif Lindholm,
Ard Biesheuvel, Abner Chang, Sami Mujawar, Gerd Hoffmann,
Kumar, Rahul R, Yao, Jiewen, Sunil V L, Warkentin, Andrei,
Dongyan Qian
My comments are for other drivers/libraries in UefiCpuPkg.
This patch series only contain CpuMmio2Dxe driver which I've already given R-b.
I am ok with the CpuMmio2Dxe patch.
Thanks,
Ray
> -----Original Message-----
> From: Laszlo Ersek <lersek@redhat.com>
> Sent: Friday, February 2, 2024 10:56 PM
> To: devel@edk2.groups.io; lichao@loongson.cn
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Liming Gao
> <gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com>; Leif
> Lindholm <quic_llindhol@quicinc.com>; Ard Biesheuvel
> <ardb+tianocore@kernel.org>; Abner Chang <abner.chang@amd.com>; Sami
> Mujawar <sami.mujawar@arm.com>; Gerd Hoffmann <kraxel@redhat.com>;
> Ni, Ray <ray.ni@intel.com>; Kumar, Rahul R <rahul.r.kumar@intel.com>; Yao,
> Jiewen <jiewen.yao@intel.com>; Sunil V L <sunilvl@ventanamicro.com>;
> Warkentin, Andrei <andrei.warkentin@intel.com>; Dongyan Qian
> <qiandongyan@loongson.cn>
> Subject: Re: [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions
> and defines
>
> On 2/2/24 03:26, Chao Li wrote:
> > This series is part 1 of enabling LoongArch64 virtual machine.
> >
> > Added LoongArch helper functions and defines in MdePkg, added
> LoongArch
> > CPU IO width in EmbeddedPkg, moved some libraries and PCDs from
> > ArmVirtPkg to OvmfPkg for easiser use by other ARCHs, added a new CPU
> IO2
> > driver named CpuMmio2Dxe in UefiCpuPkg, for non-IO port implement
> CPUs.
>
> I think this series is good to go; fully reviewed, so we can merge it
> during (not just before) the soft feature freeze period.
>
> Ray, can you confirm you are OK with this version? You made some
> comments under v8 that make me a bit uncertain.
>
> Laszlo
>
> >
> > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > Cc: Liming Gao <gaoliming@byosoft.com.cn>
> > Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> > Cc: Leif Lindholm <quic_llindhol@quicinc.com>
> > Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> > Cc: Abner Chang <abner.chang@amd.com>
> > Cc: Laszlo Ersek <lersek@redhat.com>
> > Cc: Leif Lindholm <quic_llindhol@quicinc.com>
> > Cc: Sami Mujawar <sami.mujawar@arm.com>
> > Cc: Gerd Hoffmann <kraxel@redhat.com>
> > Cc: Ray Ni <ray.ni@intel.com>
> > Cc: Rahul Kumar <rahul1.kumar@intel.com>
> > Cc: Gerd Hoffmann <kraxel@redhat.com>
> > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > Cc: Sunil V L <sunilvl@ventanamicro.com>
> > Cc: Andrei Warkentin <andrei.warkentin@intel.com>
> > Cc: Dongyan Qian <qiandongyan@loongson.cn>
> >
> > Chao Li (19):
> > MdePkg: Add the header file named Csr.h for LoongArch64
> > MdePkg: Add LoongArch64 FPU function set into BaseCpuLib
> > MdePkg: Add LoongArch64 exception function set into BaseLib
> > MdePkg: Add LoongArch64 local interrupt function set into BaseLib
> > MdePkg: Add LoongArch Cpucfg function
> > MdePkg: Add read stable counter operation for LoongArch
> > MdePkg: Add CSR operation for LoongArch
> > MdePkg: Add IOCSR operation for LoongArch
> > MdePkg: Add a new library named PeiServicesTablePointerLibKs0
> > MdePkg: Add some comments for LoongArch exceptions
> > EmbeddedPkg: Add PcdPrePiCpuIoSize width for LOONGARCH64
> > ArmVirtPkg: Move PCD of FDT base address and FDT padding to OvmfPkg
> > UefiCpuPkg: Add a new CPU IO 2 driver named CpuMmio2Dxe
> > ArmVirtPkg: Enable CpuMmio2Dxe
> > OvmfPkg/RiscVVirt: Enable CpuMmio2Dxe
> > OvmfPkg/RiscVVirt: Remove PciCpuIo2Dxe from RiscVVirt
> > ArmVirtPkg: Move the FdtSerialPortAddressLib to OvmfPkg
> > ArmVirtPkg: Move two PCD variables into OvmfPkg
> > ArmVirtPkg: Move PlatformBootManagerLib to OvmfPkg
> >
> > ArmVirtPkg/ArmVirt.dsc.inc | 2 +-
> > ArmVirtPkg/ArmVirtCloudHv.dsc | 4 +-
> > ArmVirtPkg/ArmVirtCloudHv.fdf | 2 +-
> > ArmVirtPkg/ArmVirtKvmTool.dsc | 4 +-
> > ArmVirtPkg/ArmVirtKvmTool.fdf | 2 +-
> > ArmVirtPkg/ArmVirtPkg.ci.yaml | 1 -
> > ArmVirtPkg/ArmVirtPkg.dec | 28 -
> > ArmVirtPkg/ArmVirtQemu.dsc | 8 +-
> > ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc | 2 +-
> > ArmVirtPkg/ArmVirtQemuKernel.dsc | 8 +-
> > ArmVirtPkg/ArmVirtXen.dsc | 2 +-
> > .../ArmVirtPsciResetSystemPeiLib.inf | 3 +-
> > .../CloudHvVirtMemInfoPeiLib.inf | 3 +-
> > .../DebugLibFdtPL011UartFlash.inf | 3 +-
> > .../EarlyFdt16550SerialPortHookLib.inf | 3 +-
> > .../EarlyFdtPL011SerialPortLib.inf | 3 +-
> > .../KvmtoolPlatformPeiLib.inf | 5 +-
> > .../Library/PlatformPeiLib/PlatformPeiLib.inf | 10 +-
> > .../QemuVirtMemInfoPeiLib.inf | 3 +-
> > .../PrePi/ArmVirtPrePiUniCoreRelocatable.inf | 3 +-
> > EmbeddedPkg/EmbeddedPkg.dec | 3 +
> > MdePkg/Include/Library/BaseLib.h | 221 +++++++
> > MdePkg/Include/Library/CpuLib.h | 43 +-
> > .../Library/PeiServicesTablePointerLib.h | 9 +-
> > MdePkg/Include/Protocol/DebugSupport.h | 14 +
> > MdePkg/Include/Register/LoongArch64/Cpucfg.h | 565
> ++++++++++++++++++
> > MdePkg/Include/Register/LoongArch64/Csr.h | 263 ++++++++
> > MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 7 +-
> > .../Library/BaseCpuLib/LoongArch/DisableFpu.S | 17 +
> > .../Library/BaseCpuLib/LoongArch/EnableFpu.S | 17 +
> > .../BaseCpuLib/LoongArch/InitializeFpu.S | 51 ++
> > MdePkg/Library/BaseLib/BaseLib.inf | 6 +
> > MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S | 422 +++++++++++++
> > MdePkg/Library/BaseLib/LoongArch64/Cpucfg.S | 26 +
> > MdePkg/Library/BaseLib/LoongArch64/Csr.c | 81 +++
> > .../BaseLib/LoongArch64/DisableInterrupts.S | 22 +-
> > .../BaseLib/LoongArch64/EnableInterrupts.S | 22 +-
> > .../BaseLib/LoongArch64/ExceptionBase.S | 41 ++
> > MdePkg/Library/BaseLib/LoongArch64/IoCsr.S | 120 ++++
> > .../BaseLib/LoongArch64/ReadStableCounter.S | 24 +
> > .../PeiServicesTablePointer.c | 87 +++
> > .../PeiServicesTablePointerLibKs0.inf | 37 ++
> > .../PeiServicesTablePointerLibKs0.uni | 20 +
> > MdePkg/MdePkg.ci.yaml | 3 +-
> > MdePkg/MdePkg.dsc | 3 +
> > .../Include/Library/FdtSerialPortAddressLib.h | 0
> > .../FdtSerialPortAddressLib.c | 0
> > .../FdtSerialPortAddressLib.inf | 2 +-
> > .../PlatformBootManagerLibLight}/PlatformBm.c | 0
> > .../PlatformBootManagerLibLight}/PlatformBm.h | 0
> > .../PlatformBootManagerLib.inf | 5 +-
> > .../PlatformBootManagerLibLight}/QemuKernel.c | 0
> > OvmfPkg/OvmfPkg.dec | 32 +
> > OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 2 +-
> > OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 2 +-
> > .../CpuMmio2Dxe/CpuMmio2Dxe.c | 8 +-
> > .../CpuMmio2Dxe/CpuMmio2Dxe.inf | 16 +-
> > UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.uni | 18 +
> > UefiCpuPkg/UefiCpuPkg.dsc | 1 +
> > 59 files changed, 2209 insertions(+), 100 deletions(-)
> > create mode 100644 MdePkg/Include/Register/LoongArch64/Cpucfg.h
> > create mode 100644 MdePkg/Include/Register/LoongArch64/Csr.h
> > create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/DisableFpu.S
> > create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/EnableFpu.S
> > create mode 100644
> MdePkg/Library/BaseCpuLib/LoongArch/InitializeFpu.S
> > create mode 100644 MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S
> > create mode 100644 MdePkg/Library/BaseLib/LoongArch64/Cpucfg.S
> > create mode 100644 MdePkg/Library/BaseLib/LoongArch64/Csr.c
> > create mode 100644
> MdePkg/Library/BaseLib/LoongArch64/ExceptionBase.S
> > create mode 100644 MdePkg/Library/BaseLib/LoongArch64/IoCsr.S
> > create mode 100644
> MdePkg/Library/BaseLib/LoongArch64/ReadStableCounter.S
> > create mode 100644
> MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointer.c
> > create mode 100644
> MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointerLibKs0.
> inf
> > create mode 100644
> MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointerLibKs0.
> uni
> > rename {ArmVirtPkg =>
> OvmfPkg}/Include/Library/FdtSerialPortAddressLib.h (100%)
> > rename {ArmVirtPkg =>
> OvmfPkg}/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.c (100%)
> > rename {ArmVirtPkg =>
> OvmfPkg}/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf (90%)
> > rename {ArmVirtPkg/Library/PlatformBootManagerLib =>
> OvmfPkg/Library/PlatformBootManagerLibLight}/PlatformBm.c (100%)
> > rename {ArmVirtPkg/Library/PlatformBootManagerLib =>
> OvmfPkg/Library/PlatformBootManagerLibLight}/PlatformBm.h (100%)
> > rename {ArmVirtPkg/Library/PlatformBootManagerLib =>
> OvmfPkg/Library/PlatformBootManagerLibLight}/PlatformBootManagerLib.in
> f (89%)
> > rename {ArmVirtPkg/Library/PlatformBootManagerLib =>
> OvmfPkg/Library/PlatformBootManagerLibLight}/QemuKernel.c (100%)
> > rename OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c =>
> UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c (96%)
> > rename OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf =>
> UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf (61%)
> > create mode 100644 UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.uni
> >
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^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines
2024-02-02 15:17 ` Ni, Ray
@ 2024-02-02 16:14 ` Laszlo Ersek
2024-02-04 3:16 ` Chao Li
0 siblings, 1 reply; 27+ messages in thread
From: Laszlo Ersek @ 2024-02-02 16:14 UTC (permalink / raw)
To: Ni, Ray, devel@edk2.groups.io, lichao@loongson.cn
Cc: Kinney, Michael D, Liming Gao, Liu, Zhiguang, Leif Lindholm,
Ard Biesheuvel, Abner Chang, Sami Mujawar, Gerd Hoffmann,
Kumar, Rahul R, Yao, Jiewen, Sunil V L, Warkentin, Andrei,
Dongyan Qian
On 2/2/24 16:17, Ni, Ray wrote:
> My comments are for other drivers/libraries in UefiCpuPkg.
> This patch series only contain CpuMmio2Dxe driver which I've already given R-b.
> I am ok with the CpuMmio2Dxe patch.
Sounds great, thank you.
If there are no objections, I'll merge this next Monday (5 Feb).
Laszlo
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^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines
2024-02-02 16:14 ` Laszlo Ersek
@ 2024-02-04 3:16 ` Chao Li
2024-02-05 7:34 ` Laszlo Ersek
0 siblings, 1 reply; 27+ messages in thread
From: Chao Li @ 2024-02-04 3:16 UTC (permalink / raw)
To: devel, lersek, Ni, Ray
Cc: Kinney, Michael D, Liming Gao, Liu, Zhiguang, Leif Lindholm,
Ard Biesheuvel, Abner Chang, Sami Mujawar, Gerd Hoffmann,
Kumar, Rahul R, Yao, Jiewen, Sunil V L, Warkentin, Andrei,
Dongyan Qian
[-- Attachment #1: Type: text/plain, Size: 946 bytes --]
Hi All,
I forgot to add the PR link in the cover-letter, and now that I have
added it below and it has passed the CI.
https://github.com/tianocore/edk2/pull/5334
Thanks,
Chao
On 2024/2/3 00:14, Laszlo Ersek wrote:
> On 2/2/24 16:17, Ni, Ray wrote:
>> My comments are for other drivers/libraries in UefiCpuPkg.
>> This patch series only contain CpuMmio2Dxe driver which I've already given R-b.
>> I am ok with the CpuMmio2Dxe patch.
> Sounds great, thank you.
>
> If there are no objections, I'll merge this next Monday (5 Feb).
>
> Laszlo
>
>
>
>
>
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* Re: [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines
2024-02-04 3:16 ` Chao Li
@ 2024-02-05 7:34 ` Laszlo Ersek
2024-02-05 9:11 ` Chao Li
0 siblings, 1 reply; 27+ messages in thread
From: Laszlo Ersek @ 2024-02-05 7:34 UTC (permalink / raw)
To: Kinney, Michael D, Liming Gao
Cc: Liu, Zhiguang, Leif Lindholm, Ard Biesheuvel, Abner Chang,
Sami Mujawar, Gerd Hoffmann, Kumar, Rahul R, Yao, Jiewen,
Sunil V L, Warkentin, Andrei, Dongyan Qian, edk2-devel-groups-io,
Chao Li, Ni, Ray
Hi Liming, Mike,
can you please merge this patch set? Its review had completed before the
soft feature freeze.
I planned to merge it today, but Liming's announcement of the SFF
reminds me that I can't set the "push" label now.
Thanks!
Laszlo
On 2/4/24 04:16, Chao Li wrote:
> Hi All,
>
> I forgot to add the PR link in the cover-letter, and now that I have
> added it below and it has passed the CI.
>
> https://github.com/tianocore/edk2/pull/5334
>
>
> Thanks,
> Chao
> On 2024/2/3 00:14, Laszlo Ersek wrote:
>> On 2/2/24 16:17, Ni, Ray wrote:
>>> My comments are for other drivers/libraries in UefiCpuPkg.
>>> This patch series only contain CpuMmio2Dxe driver which I've already given R-b.
>>> I am ok with the CpuMmio2Dxe patch.
>> Sounds great, thank you.
>>
>> If there are no objections, I'll merge this next Monday (5 Feb).
>>
>> Laszlo
>>
>>
>>
>>
>>
>
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* Re: [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines
2024-02-05 7:34 ` Laszlo Ersek
@ 2024-02-05 9:11 ` Chao Li
2024-02-06 15:52 ` 回复: " gaoliming via groups.io
0 siblings, 1 reply; 27+ messages in thread
From: Chao Li @ 2024-02-05 9:11 UTC (permalink / raw)
To: devel, lersek, Kinney, Michael D, Liming Gao
Cc: Liu, Zhiguang, Leif Lindholm, Ard Biesheuvel, Abner Chang,
Sami Mujawar, Gerd Hoffmann, Kumar, Rahul R, Yao, Jiewen,
Sunil V L, Warkentin, Andrei, Dongyan Qian, Ni, Ray
[-- Attachment #1: Type: text/plain, Size: 1660 bytes --]
Hi Liming, Mike,
This series has been reviewed done before and was send before the SFF, I
want to catch stable202402 tag.
So can you pass this merge request?
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4663
PR: https://github.com/tianocore/edk2/pull/5334
Thanks,
Chao
On 2024/2/5 15:34, Laszlo Ersek wrote:
> Hi Liming, Mike,
>
> can you please merge this patch set? Its review had completed before the
> soft feature freeze.
>
> I planned to merge it today, but Liming's announcement of the SFF
> reminds me that I can't set the "push" label now.
>
> Thanks!
> Laszlo
>
> On 2/4/24 04:16, Chao Li wrote:
>> Hi All,
>>
>> I forgot to add the PR link in the cover-letter, and now that I have
>> added it below and it has passed the CI.
>>
>> https://github.com/tianocore/edk2/pull/5334
>>
>>
>> Thanks,
>> Chao
>> On 2024/2/3 00:14, Laszlo Ersek wrote:
>>> On 2/2/24 16:17, Ni, Ray wrote:
>>>> My comments are for other drivers/libraries in UefiCpuPkg.
>>>> This patch series only contain CpuMmio2Dxe driver which I've already given R-b.
>>>> I am ok with the CpuMmio2Dxe patch.
>>> Sounds great, thank you.
>>>
>>> If there are no objections, I'll merge this next Monday (5 Feb).
>>>
>>> Laszlo
>>>
>>>
>>>
>>>
>>>
>
>
>
>
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* 回复: [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines
2024-02-05 9:11 ` Chao Li
@ 2024-02-06 15:52 ` gaoliming via groups.io
0 siblings, 0 replies; 27+ messages in thread
From: gaoliming via groups.io @ 2024-02-06 15:52 UTC (permalink / raw)
To: devel, lichao, lersek, 'Kinney, Michael D'
Cc: 'Liu, Zhiguang', 'Leif Lindholm',
'Ard Biesheuvel', 'Abner Chang',
'Sami Mujawar', 'Gerd Hoffmann',
'Kumar, Rahul R', 'Yao, Jiewen',
'Sunil V L', 'Warkentin, Andrei',
'Dongyan Qian', 'Ni, Ray'
[-- Attachment #1: Type: text/plain, Size: 2491 bytes --]
Chao:
I just add push label and merge it.
Thanks
Liming
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Chao Li
发送时间: 2024年2月5日 17:12
收件人: devel@edk2.groups.io; lersek@redhat.com; Kinney, Michael D <michael.d.kinney@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>
抄送: Liu, Zhiguang <zhiguang.liu@intel.com>; Leif Lindholm <quic_llindhol@quicinc.com>; Ard Biesheuvel <ardb+tianocore@kernel.org>; Abner Chang <abner.chang@amd.com>; Sami Mujawar <sami.mujawar@arm.com>; Gerd Hoffmann <kraxel@redhat.com>; Kumar, Rahul R <rahul.r.kumar@intel.com>; Yao, Jiewen <jiewen.yao@intel.com>; Sunil V L <sunilvl@ventanamicro.com>; Warkentin, Andrei <andrei.warkentin@intel.com>; Dongyan Qian <qiandongyan@loongson.cn>; Ni, Ray <ray.ni@intel.com>
主题: Re: [edk2-devel] [PATCH v1 00/19] Add LoongArch helper functions and defines
Hi Liming, Mike,
This series has been reviewed done before and was send before the SFF, I want to catch stable202402 tag.
So can you pass this merge request?
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4663
PR: https://github.com/tianocore/edk2/pull/5334
Thanks,
Chao
On 2024/2/5 15:34, Laszlo Ersek wrote:
Hi Liming, Mike,
can you please merge this patch set? Its review had completed before the
soft feature freeze.
I planned to merge it today, but Liming's announcement of the SFF
reminds me that I can't set the "push" label now.
Thanks!
Laszlo
On 2/4/24 04:16, Chao Li wrote:
Hi All,
I forgot to add the PR link in the cover-letter, and now that I have
added it below and it has passed the CI.
https://github.com/tianocore/edk2/pull/5334
Thanks,
Chao
On 2024/2/3 00:14, Laszlo Ersek wrote:
On 2/2/24 16:17, Ni, Ray wrote:
My comments are for other drivers/libraries in UefiCpuPkg.
This patch series only contain CpuMmio2Dxe driver which I've already given R-b.
I am ok with the CpuMmio2Dxe patch.
Sounds great, thank you.
If there are no objections, I'll merge this next Monday (5 Feb).
Laszlo
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