From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 71FE9D80144 for ; Tue, 6 Feb 2024 01:58:24 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=M7zwjqc1nNQPAo0/geHOuWAJ1rN4GXEb7lf5c6E04+U=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1707184703; v=1; b=rpMsAzToHvu/JwRuugwOjuSjR0bd/KjybtqocLdic+5GEbjWiUK8XScnuNJeG8ASdlmtboRy DG/4Ub1yG5BciyfQHxRzkfEa54iLHq4EftPAKEjWh4dq2asP8a5wtkN77aUtcIyFfTitP98ZOz2 qy4RcNbVtJLQi1tL0FqSgYPY= X-Received: by 127.0.0.2 with SMTP id UYYNYY7687511xnHn2jI05G9; Mon, 05 Feb 2024 17:58:23 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mx.groups.io with SMTP id smtpd.web11.12552.1707184694246358540 for ; Mon, 05 Feb 2024 17:58:22 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10975"; a="18074375" X-IronPort-AV: E=Sophos;i="6.05,245,1701158400"; d="scan'208";a="18074375" X-Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2024 17:58:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10975"; a="909469839" X-IronPort-AV: E=Sophos;i="6.05,245,1701158400"; d="scan'208";a="909469839" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.43]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2024 17:58:20 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V2 3/3] UefiCpuPkg/PiSmmCpuDxeSmm:Map SMRAM in 4K page granularity Date: Tue, 6 Feb 2024 09:57:57 +0800 Message-Id: <20240206015757.1816-4-dun.tan@intel.com> In-Reply-To: <20240206015757.1816-1-dun.tan@intel.com> References: <20240206015757.1816-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: GxNQJjlql0RyiFQpgeVVaLJNx7686176AA= Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=rpMsAzTo; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none) This patch is to map SMRAM in 4K page granularity during SMM page table initialization(SmmInitPageTable) so as to avoid the SMRAM paging-structure layout change when SMI happens (PerformRemainingTasks). The reason is to avoid the Paging-Structure change impact to the multiple Processors. Refer SDM section "4.10.4" & "4.10.5". Currently, SMM BSP needs to update the SMRAM range paging attribute in smm page table according to the SmmMemoryAttributesTable when SMM ready to lock happens. If the SMRAM range is not 4k mapped in page table, the page table update process may split 1G/2M paging entries to 4k ones.Meanwhile, all APs are still running in SMI, which might access the affected linear-address range between the time of modification and the time of invalidation access. That will be a potential problem leading exception happens. Signed-off-by: Dun Tan Reviewed-by: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 116 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++------------------------ 1 file changed, 92 insertions(+), 24 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index 12f3c0b8e8..b8c356bfe8 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -1647,49 +1647,115 @@ EdkiiSmmClearMemoryAttributes ( } /** - Create page table based on input PagingMode and PhysicalAddressBits in smm. - - @param[in] PagingMode The paging mode. - @param[in] PhysicalAddressBits The bits of physical address to map. + Create page table based on input PagingMode, LinearAddress and Length. - @retval PageTable Address + @param[in, out] PageTable The pointer to the page table. + @param[in] PagingMode The paging mode. + @param[in] LinearAddress The start of the linear address range. + @param[in] Length The length of the linear address range. **/ -UINTN -GenSmmPageTable ( - IN PAGING_MODE PagingMode, - IN UINT8 PhysicalAddressBits +VOID +GenPageTable ( + IN OUT UINTN *PageTable, + IN PAGING_MODE PagingMode, + IN UINT64 LinearAddress, + IN UINT64 Length ) { + RETURN_STATUS Status; UINTN PageTableBufferSize; - UINTN PageTable; VOID *PageTableBuffer; IA32_MAP_ATTRIBUTE MapAttribute; IA32_MAP_ATTRIBUTE MapMask; - RETURN_STATUS Status; - UINTN GuardPage; - UINTN Index; - UINT64 Length; - Length = LShiftU64 (1, PhysicalAddressBits); - PageTable = 0; - PageTableBufferSize = 0; MapMask.Uint64 = MAX_UINT64; - MapAttribute.Uint64 = mAddressEncMask; + MapAttribute.Uint64 = mAddressEncMask|LinearAddress; MapAttribute.Bits.Present = 1; MapAttribute.Bits.ReadWrite = 1; MapAttribute.Bits.UserSupervisor = 1; MapAttribute.Bits.Accessed = 1; MapAttribute.Bits.Dirty = 1; + PageTableBufferSize = 0; + + Status = PageTableMap ( + PageTable, + PagingMode, + NULL, + &PageTableBufferSize, + LinearAddress, + Length, + &MapAttribute, + &MapMask, + NULL + ); + if (Status == RETURN_BUFFER_TOO_SMALL) { + DEBUG ((DEBUG_INFO, "GenSMMPageTable: 0x%x bytes needed for initial SMM page table\n", PageTableBufferSize)); + PageTableBuffer = AllocatePageTableMemory (EFI_SIZE_TO_PAGES (PageTableBufferSize)); + ASSERT (PageTableBuffer != NULL); + Status = PageTableMap ( + PageTable, + PagingMode, + PageTableBuffer, + &PageTableBufferSize, + LinearAddress, + Length, + &MapAttribute, + &MapMask, + NULL + ); + } - Status = PageTableMap (&PageTable, PagingMode, NULL, &PageTableBufferSize, 0, Length, &MapAttribute, &MapMask, NULL); - ASSERT (Status == RETURN_BUFFER_TOO_SMALL); - DEBUG ((DEBUG_INFO, "GenSMMPageTable: 0x%x bytes needed for initial SMM page table\n", PageTableBufferSize)); - PageTableBuffer = AllocatePageTableMemory (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - ASSERT (PageTableBuffer != NULL); - Status = PageTableMap (&PageTable, PagingMode, PageTableBuffer, &PageTableBufferSize, 0, Length, &MapAttribute, &MapMask, NULL); ASSERT (Status == RETURN_SUCCESS); ASSERT (PageTableBufferSize == 0); +} + +/** + Create page table based on input PagingMode and PhysicalAddressBits in smm. + + @param[in] PagingMode The paging mode. + @param[in] PhysicalAddressBits The bits of physical address to map. + + @retval PageTable Address + +**/ +UINTN +GenSmmPageTable ( + IN PAGING_MODE PagingMode, + IN UINT8 PhysicalAddressBits + ) +{ + UINTN PageTable; + RETURN_STATUS Status; + UINTN GuardPage; + UINTN Index; + UINT64 Length; + PAGING_MODE SmramPagingMode; + + PageTable = 0; + Length = LShiftU64 (1, PhysicalAddressBits); + ASSERT (Length > mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize); + + if (sizeof (UINTN) == sizeof (UINT64)) { + SmramPagingMode = m5LevelPagingNeeded ? Paging5Level4KB : Paging4Level4KB; + } else { + SmramPagingMode = PagingPae4KB; + } + + ASSERT (mCpuHotPlugData.SmrrBase % SIZE_4KB == 0); + ASSERT (mCpuHotPlugData.SmrrSize % SIZE_4KB == 0); + GenPageTable (&PageTable, PagingMode, 0, mCpuHotPlugData.SmrrBase); + + // + // Map smram range in 4K page granularity to avoid subsequent page split when smm ready to lock. + // If BSP are splitting the 1G/2M paging entries to 512 2M/4K paging entries, and all APs are + // still running in SMI at the same time, which might access the affected linear-address range + // between the time of modification and the time of invalidation access. That will be a potential + // problem leading exception happen. + // + GenPageTable (&PageTable, SmramPagingMode, mCpuHotPlugData.SmrrBase, mCpuHotPlugData.SmrrSize); + + GenPageTable (&PageTable, PagingMode, mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize, Length - mCpuHotPlugData.SmrrBase - mCpuHotPlugData.SmrrSize); if (FeaturePcdGet (PcdCpuSmmStackGuard)) { // @@ -1698,6 +1764,7 @@ GenSmmPageTable ( for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) { GuardPage = mSmmStackArrayBase + EFI_PAGE_SIZE + Index * (mSmmStackSize + mSmmShadowStackSize); Status = ConvertMemoryPageAttributes (PageTable, PagingMode, GuardPage, SIZE_4KB, EFI_MEMORY_RP, TRUE, NULL); + ASSERT (Status == RETURN_SUCCESS); } } @@ -1706,6 +1773,7 @@ GenSmmPageTable ( // Mark [0, 4k] as non-present // Status = ConvertMemoryPageAttributes (PageTable, PagingMode, 0, SIZE_4KB, EFI_MEMORY_RP, TRUE, NULL); + ASSERT (Status == RETURN_SUCCESS); } return (UINTN)PageTable; -- 2.31.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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