[edk2-devel] [PATCH v2 0/3] RISC-V: Support Svpbmt extension

[edk2-devel] [PATCH v2 0/3] RISC-V: Support Svpbmt extension

[Tuan Phan]

This patchset adds support for RISC-V Svpbmt extension.

The GCD EFI_MEMORY_UC and EFI_MEMORY_WC attributes will
be mapped to IO and NC mode defined in PBMT field.

v2:
  - Generated patch for each package.

Tuan Phan (3):
  MdePkg.dec: RISC-V: Define override bit for Svpbmt extension
  UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension
  OvmfPkg/RiscVVirt: Override Svpbmt extension

 MdePkg/MdePkg.dec                             |  2 ++
 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc           |  2 +-
 .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 25 ++++++++++++++++++-
 .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf       |  1 +
 4 files changed, 28 insertions(+), 2 deletions(-)

-- 
2.25.1



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[edk2-devel] [PATCH v2 1/3] MdePkg.dec: RISC-V: Define override bit for Svpbmt extension

[Tuan Phan]

Define the BIT 2 as the override bit for Svpbmt extension. This will
be used by RISC-V MMU library to support GCD EFI_MEMORY_UC and
EFI_MEMORY_WC attributes.

Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
---
 MdePkg/MdePkg.dec | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index 0459418906f8..6850acb96b92 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -2407,6 +2407,8 @@
   # previous stage has feature enabled and user wants to disable it.
   # BIT 1 = Supervisor Time Compare (Sstc). This bit is relevant only if
   # previous stage has feature enabled and user wants to disable it.
+  # BIT 2 = Page-Based Memory Types (Pbmt). This bit is relevant only if
+  # previous stage has feature enabled and user wants to disable it.
   #
   gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT64|0x69
 
-- 
2.25.1



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[edk2-devel] [PATCH v2 2/3] UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension

[Tuan Phan]

The GCD EFI_MEMORY_UC and EFI_MEMORY_WC attributes will be
supported when Svpbmt extension available.

Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
---
 .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 25 ++++++++++++++++++-
 .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf       |  1 +
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
index 826a1d32a1d4..c50a28e97e4b 100644
--- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
@@ -36,6 +36,15 @@
 #define PTE_PPN_SHIFT         10
 #define RISCV_MMU_PAGE_SHIFT  12
 
+#define RISCV_CPU_FEATURE_PBMT_BITMASK  BIT2
+#define PTE_PBMT_NC                     BIT61
+#define PTE_PBMT_IO                     BIT62
+#define PTE_PBMT_MASK                   (PTE_PBMT_NC | PTE_PBMT_IO)
+
+#define EFI_MEMORY_CACHETYPE_MASK  (EFI_MEMORY_UC | EFI_MEMORY_WC |  \
+                                     EFI_MEMORY_WT | EFI_MEMORY_WB | \
+                                     EFI_MEMORY_UCE)
+
 STATIC UINTN  mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF };
 STATIC UINTN  mMaxRootTableLevel;
 STATIC UINTN  mBitPerLevel;
@@ -514,6 +523,20 @@ GcdAttributeToPageAttribute (
     RiscVAttributes &= ~RISCV_PG_X;
   }
 
+  if ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_PBMT_BITMASK) != 0) {
+    switch (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) {
+      case EFI_MEMORY_UC:
+        RiscVAttributes |= PTE_PBMT_IO;
+        break;
+      case EFI_MEMORY_WC:
+        RiscVAttributes |= PTE_PBMT_NC;
+        break;
+      default:
+        // Default PMA mode
+        break;
+    }
+  }
+
   return RiscVAttributes;
 }
 
@@ -559,7 +582,7 @@ RiscVSetMemoryAttributes (
            BaseAddress,
            Length,
            PageAttributesSet,
-           PTE_ATTRIBUTES_MASK,
+           PTE_ATTRIBUTES_MASK | PTE_PBMT_MASK,
            (UINTN *)RiscVGetRootTranslateTable (),
            TRUE
            );
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
index 51ebe1750e97..1dbaa81f3608 100644
--- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
@@ -28,3 +28,4 @@
 
 [Pcd]
   gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode  ## CONSUMES
+  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride     ## CONSUMES
-- 
2.25.1



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[edk2-devel] [PATCH v2 3/3] OvmfPkg/RiscVVirt: Override Svpbmt extension

[Tuan Phan]

Override Svpbmt extension that be disabled by default.

Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
---
 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
index 6bc7c90f31dc..b8338d2eb5f5 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
+++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
@@ -203,7 +203,7 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
 
 [PcdsFixedAtBuild.common]
-  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFC
+  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFF8
   gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
   gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
   gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
-- 
2.25.1



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Re: [edk2-devel] [PATCH v2 1/3] MdePkg.dec: RISC-V: Define override bit for Svpbmt extension

[Laszlo Ersek]

On 2/7/24 02:29, Tuan Phan wrote:
> Define the BIT 2 as the override bit for Svpbmt extension. This will
> be used by RISC-V MMU library to support GCD EFI_MEMORY_UC and
> EFI_MEMORY_WC attributes.
> 
> Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
> ---
>  MdePkg/MdePkg.dec | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
> index 0459418906f8..6850acb96b92 100644
> --- a/MdePkg/MdePkg.dec
> +++ b/MdePkg/MdePkg.dec
> @@ -2407,6 +2407,8 @@
>    # previous stage has feature enabled and user wants to disable it.
>    # BIT 1 = Supervisor Time Compare (Sstc). This bit is relevant only if
>    # previous stage has feature enabled and user wants to disable it.
> +  # BIT 2 = Page-Based Memory Types (Pbmt). This bit is relevant only if
> +  # previous stage has feature enabled and user wants to disable it.
>    #
>    gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT64|0x69
>  

Reviewed-by: Laszlo Ersek <lersek@redhat.com>



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Re: [edk2-devel] [PATCH v2 2/3] UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension

[Laszlo Ersek]

On 2/7/24 02:29, Tuan Phan wrote:
> The GCD EFI_MEMORY_UC and EFI_MEMORY_WC attributes will be
> supported when Svpbmt extension available.
> 
> Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
> ---
>  .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 25 ++++++++++++++++++-
>  .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf       |  1 +
>  2 files changed, 25 insertions(+), 1 deletion(-)
> 
> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> index 826a1d32a1d4..c50a28e97e4b 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> @@ -36,6 +36,15 @@
>  #define PTE_PPN_SHIFT         10
>  #define RISCV_MMU_PAGE_SHIFT  12
>  
> +#define RISCV_CPU_FEATURE_PBMT_BITMASK  BIT2
> +#define PTE_PBMT_NC                     BIT61
> +#define PTE_PBMT_IO                     BIT62
> +#define PTE_PBMT_MASK                   (PTE_PBMT_NC | PTE_PBMT_IO)
> +
> +#define EFI_MEMORY_CACHETYPE_MASK  (EFI_MEMORY_UC | EFI_MEMORY_WC |  \
> +                                     EFI_MEMORY_WT | EFI_MEMORY_WB | \
> +                                     EFI_MEMORY_UCE)
> +

(1) I've stated this elsewhere -- introducing such a macro is justified,
but calling it EFI_* is not. The EFI_ prefix is reserved for the spec.

>  STATIC UINTN  mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF };
>  STATIC UINTN  mMaxRootTableLevel;
>  STATIC UINTN  mBitPerLevel;
> @@ -514,6 +523,20 @@ GcdAttributeToPageAttribute (
>      RiscVAttributes &= ~RISCV_PG_X;
>    }
>  
> +  if ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_PBMT_BITMASK) != 0) {
> +    switch (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) {
> +      case EFI_MEMORY_UC:
> +        RiscVAttributes |= PTE_PBMT_IO;
> +        break;
> +      case EFI_MEMORY_WC:
> +        RiscVAttributes |= PTE_PBMT_NC;
> +        break;
> +      default:
> +        // Default PMA mode
> +        break;
> +    }
> +  }
> +
>    return RiscVAttributes;
>  }
>  

Several questions / observations:

(2) If the feature is cleared in the PCD, does it deserve a warning that
the attribute setting request cannot be honored?

(3) The memory cacheability attributes are expressed as distinct bits of
a bitmask because, for expressing *capabilities*, they must be possible
to OR together. However, when setting actual attributes, I think the
bitmask should contain *exactly* one bit set -- in other words, the
value of the bitmask should be an integral power of two (that's not hard
to check).

Do you agree about this? If so, I'd suggest rejecting the request (with
an appropriate status code) if zero bits, or multiple bits, are set.

  UINT64  CacheTypeMask;

  CacheType = GcdAttributes & MEMORY_CACHETYPE_MASK;
  if ((CacheType == 0) ||
      (((CacheType - 1) & CacheType) != 0)) {
    return EFI_INVALID_PARAMETER;
  }
  switch (CacheType) {
    ...
  }

This would of course require changing the GcdAttributeToPageAttribute()
prototype, because right now the function cannot return an error.


> @@ -559,7 +582,7 @@ RiscVSetMemoryAttributes (
>             BaseAddress,
>             Length,
>             PageAttributesSet,
> -           PTE_ATTRIBUTES_MASK,
> +           PTE_ATTRIBUTES_MASK | PTE_PBMT_MASK,
>             (UINTN *)RiscVGetRootTranslateTable (),
>             TRUE
>             );

(4) I feel we shouldn't try to clear PTE_PBMT_MASK if
PcdRiscVFeatureOverride tells us that Svpbmt is not available. Just a
thought.

> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> index 51ebe1750e97..1dbaa81f3608 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> @@ -28,3 +28,4 @@
>  
>  [Pcd]
>    gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode  ## CONSUMES
> +  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride     ## CONSUMES

Thanks
Laszlo



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Re: [edk2-devel] [PATCH v2 3/3] OvmfPkg/RiscVVirt: Override Svpbmt extension

[Laszlo Ersek]

On 2/7/24 02:29, Tuan Phan wrote:
> Override Svpbmt extension that be disabled by default.
> 
> Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
> ---
>  OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> index 6bc7c90f31dc..b8338d2eb5f5 100644
> --- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> +++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> @@ -203,7 +203,7 @@
>    gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
>  
>  [PcdsFixedAtBuild.common]
> -  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFC
> +  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFF8
>    gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
>    gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
>    gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0

Reviewed-by: Laszlo Ersek <lersek@redhat.com>

(Meaning that, IMO, the patch does what it says on the tin. *Why* the
disablement is justified / necessary, I can't say, neither does the
commit message. It's probably that QEMU/KVM don't implement Svpbmt.)

Laszlo



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Re: [edk2-devel] [PATCH v2 3/3] OvmfPkg/RiscVVirt: Override Svpbmt extension

[Tuan Phan]

[-- Attachment #1: Type: text/plain, Size: 1848 bytes --]

On Wed, Feb 7, 2024 at 12:02 PM Laszlo Ersek <lersek@redhat.com> wrote:

> On 2/7/24 02:29, Tuan Phan wrote:
> > Override Svpbmt extension that be disabled by default.
> >
> > Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
> > ---
> >  OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> > index 6bc7c90f31dc..b8338d2eb5f5 100644
> > --- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> > +++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> > @@ -203,7 +203,7 @@
> >    gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
> >
> >  [PcdsFixedAtBuild.common]
> > -  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFC
> > +  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFF8
> >    gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
> >    gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
> >    gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
>
> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
>
> (Meaning that, IMO, the patch does what it says on the tin. *Why* the
> disablement is justified / necessary, I can't say, neither does the
> commit message. It's probably that QEMU/KVM don't implement Svpbmt.)
>
> Thanks for reviewing. QEMU doesn't enable Svpbmt by default. Will add to
the message in
next version.

Laszlo
>
>
>
> 
>
>
>


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[-- Attachment #2: Type: text/html, Size: 3103 bytes --]

Re: [edk2-devel] [PATCH v2 0/3] RISC-V: Support Svpbmt extension

[Andrei Warkentin]

Do you mind sharing a GH branch with the patch set?

A

> -----Original Message-----
> From: Tuan Phan <tphan@ventanamicro.com>
> Sent: Tuesday, February 6, 2024 7:29 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>;
> gaoliming@byosoft.com.cn; Liu, Zhiguang <zhiguang.liu@intel.com>;
> kraxel@redhat.com; lersek@redhat.com; Kumar, Rahul R
> <rahul.r.kumar@intel.com>; Ni, Ray <ray.ni@intel.com>;
> sunilvl@ventanamicro.com; Yao, Jiewen <jiewen.yao@intel.com>; Warkentin,
> Andrei <andrei.warkentin@intel.com>; ardb+tianocore@kernel.org; Tuan Phan
> <tphan@ventanamicro.com>
> Subject: [PATCH v2 0/3] RISC-V: Support Svpbmt extension
> 
> This patchset adds support for RISC-V Svpbmt extension.
> 
> The GCD EFI_MEMORY_UC and EFI_MEMORY_WC attributes will be mapped to
> IO and NC mode defined in PBMT field.
> 
> v2:
>   - Generated patch for each package.
> 
> Tuan Phan (3):
>   MdePkg.dec: RISC-V: Define override bit for Svpbmt extension
>   UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension
>   OvmfPkg/RiscVVirt: Override Svpbmt extension
> 
>  MdePkg/MdePkg.dec                             |  2 ++
>  OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc           |  2 +-
>  .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 25 ++++++++++++++++++-
>  .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf       |  1 +
>  4 files changed, 28 insertions(+), 2 deletions(-)
> 
> --
> 2.25.1



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Re: [edk2-devel] [PATCH v2 0/3] RISC-V: Support Svpbmt extension

[Tuan Phan]

[-- Attachment #1: Type: text/plain, Size: 2042 bytes --]

On Wed, Feb 14, 2024 at 9:43 PM Warkentin, Andrei <
andrei.warkentin@intel.com> wrote:

> Do you mind sharing a GH branch with the patch set?
>
https://github.com/pttuan/edk2/tree/tphan/riscv_mmu_svpbmt
Tuan

>
> A
>
> > -----Original Message-----
> > From: Tuan Phan <tphan@ventanamicro.com>
> > Sent: Tuesday, February 6, 2024 7:29 PM
> > To: devel@edk2.groups.io
> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>;
> > gaoliming@byosoft.com.cn; Liu, Zhiguang <zhiguang.liu@intel.com>;
> > kraxel@redhat.com; lersek@redhat.com; Kumar, Rahul R
> > <rahul.r.kumar@intel.com>; Ni, Ray <ray.ni@intel.com>;
> > sunilvl@ventanamicro.com; Yao, Jiewen <jiewen.yao@intel.com>; Warkentin,
> > Andrei <andrei.warkentin@intel.com>; ardb+tianocore@kernel.org; Tuan
> Phan
> > <tphan@ventanamicro.com>
> > Subject: [PATCH v2 0/3] RISC-V: Support Svpbmt extension
> >
> > This patchset adds support for RISC-V Svpbmt extension.
> >
> > The GCD EFI_MEMORY_UC and EFI_MEMORY_WC attributes will be mapped to
> > IO and NC mode defined in PBMT field.
> >
> > v2:
> >   - Generated patch for each package.
> >
> > Tuan Phan (3):
> >   MdePkg.dec: RISC-V: Define override bit for Svpbmt extension
> >   UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension
> >   OvmfPkg/RiscVVirt: Override Svpbmt extension
> >
> >  MdePkg/MdePkg.dec                             |  2 ++
> >  OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc           |  2 +-
> >  .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 25 ++++++++++++++++++-
> >  .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf       |  1 +
> >  4 files changed, 28 insertions(+), 2 deletions(-)
> >
> > --
> > 2.25.1
>
>


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Re: [edk2-devel] [PATCH v2 0/3] RISC-V: Support Svpbmt extension

[Tuan Phan]

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Hi Sunil/ Andrei,
Any comments on this series?

Regards,

On Wed, Feb 14, 2024 at 10:16 PM Tuan Phan via groups.io <tphan=
ventanamicro.com@groups.io> wrote:

>
>
> On Wed, Feb 14, 2024 at 9:43 PM Warkentin, Andrei <
> andrei.warkentin@intel.com> wrote:
>
>> Do you mind sharing a GH branch with the patch set?
>>
> https://github.com/pttuan/edk2/tree/tphan/riscv_mmu_svpbmt
> Tuan
>
>>
>> A
>>
>> > -----Original Message-----
>> > From: Tuan Phan <tphan@ventanamicro.com>
>> > Sent: Tuesday, February 6, 2024 7:29 PM
>> > To: devel@edk2.groups.io
>> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>;
>> > gaoliming@byosoft.com.cn; Liu, Zhiguang <zhiguang.liu@intel.com>;
>> > kraxel@redhat.com; lersek@redhat.com; Kumar, Rahul R
>> > <rahul.r.kumar@intel.com>; Ni, Ray <ray.ni@intel.com>;
>> > sunilvl@ventanamicro.com; Yao, Jiewen <jiewen.yao@intel.com>;
>> Warkentin,
>> > Andrei <andrei.warkentin@intel.com>; ardb+tianocore@kernel.org; Tuan
>> Phan
>> > <tphan@ventanamicro.com>
>> > Subject: [PATCH v2 0/3] RISC-V: Support Svpbmt extension
>> >
>> > This patchset adds support for RISC-V Svpbmt extension.
>> >
>> > The GCD EFI_MEMORY_UC and EFI_MEMORY_WC attributes will be mapped to
>> > IO and NC mode defined in PBMT field.
>> >
>> > v2:
>> >   - Generated patch for each package.
>> >
>> > Tuan Phan (3):
>> >   MdePkg.dec: RISC-V: Define override bit for Svpbmt extension
>> >   UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension
>> >   OvmfPkg/RiscVVirt: Override Svpbmt extension
>> >
>> >  MdePkg/MdePkg.dec                             |  2 ++
>> >  OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc           |  2 +-
>> >  .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 25 ++++++++++++++++++-
>> >  .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf       |  1 +
>> >  4 files changed, 28 insertions(+), 2 deletions(-)
>> >
>> > --
>> > 2.25.1
>>
>> 
>
>


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Re: [edk2-devel] [PATCH v2 0/3] RISC-V: Support Svpbmt extension

[Sunil V L]

Hi Tuan,

On Mon, Feb 26, 2024 at 08:34:22PM -0800, Tuan Phan wrote:
> Hi Sunil/ Andrei,
> Any comments on this series?
> 
Did I miss your response to Laszlo's feedback on PATCH 2 - [1]? Apart
from that, don't we need to handle EFI_MEMORY_WT similar to
EFI_MEMORY_WC?

[1] - https://edk2.groups.io/g/devel/message/115243

Thanks,
Sunil
> Regards,
> 
> On Wed, Feb 14, 2024 at 10:16 PM Tuan Phan via groups.io <tphan=
> ventanamicro.com@groups.io> wrote:
> 
> >
> >
> > On Wed, Feb 14, 2024 at 9:43 PM Warkentin, Andrei <
> > andrei.warkentin@intel.com> wrote:
> >
> >> Do you mind sharing a GH branch with the patch set?
> >>
> > https://github.com/pttuan/edk2/tree/tphan/riscv_mmu_svpbmt
> > Tuan
> >
> >>
> >> A
> >>
> >> > -----Original Message-----
> >> > From: Tuan Phan <tphan@ventanamicro.com>
> >> > Sent: Tuesday, February 6, 2024 7:29 PM
> >> > To: devel@edk2.groups.io
> >> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>;
> >> > gaoliming@byosoft.com.cn; Liu, Zhiguang <zhiguang.liu@intel.com>;
> >> > kraxel@redhat.com; lersek@redhat.com; Kumar, Rahul R
> >> > <rahul.r.kumar@intel.com>; Ni, Ray <ray.ni@intel.com>;
> >> > sunilvl@ventanamicro.com; Yao, Jiewen <jiewen.yao@intel.com>;
> >> Warkentin,
> >> > Andrei <andrei.warkentin@intel.com>; ardb+tianocore@kernel.org; Tuan
> >> Phan
> >> > <tphan@ventanamicro.com>
> >> > Subject: [PATCH v2 0/3] RISC-V: Support Svpbmt extension
> >> >
> >> > This patchset adds support for RISC-V Svpbmt extension.
> >> >
> >> > The GCD EFI_MEMORY_UC and EFI_MEMORY_WC attributes will be mapped to
> >> > IO and NC mode defined in PBMT field.
> >> >
> >> > v2:
> >> >   - Generated patch for each package.
> >> >
> >> > Tuan Phan (3):
> >> >   MdePkg.dec: RISC-V: Define override bit for Svpbmt extension
> >> >   UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension
> >> >   OvmfPkg/RiscVVirt: Override Svpbmt extension
> >> >
> >> >  MdePkg/MdePkg.dec                             |  2 ++
> >> >  OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc           |  2 +-
> >> >  .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 25 ++++++++++++++++++-
> >> >  .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf       |  1 +
> >> >  4 files changed, 28 insertions(+), 2 deletions(-)
> >> >
> >> > --
> >> > 2.25.1
> >>
> >> 
> >
> >


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Re: [edk2-devel] [PATCH v2 0/3] RISC-V: Support Svpbmt extension

[Tuan Phan]

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On Tue, Feb 27, 2024 at 8:42 PM Sunil V L <sunilvl@ventanamicro.com> wrote:

> Hi Tuan,
>
> On Mon, Feb 26, 2024 at 08:34:22PM -0800, Tuan Phan wrote:
> > Hi Sunil/ Andrei,
> > Any comments on this series?
> >
> Did I miss your response to Laszlo's feedback on PATCH 2 - [1]? Apart
> from that, don't we need to handle EFI_MEMORY_WT similar to
> EFI_MEMORY_WC?
>
> Somehow I missed that feedback. Thanks.
About EFI_MEMORY_WT, ARM treats it as EFI_MEMORY_WC under hood but I don't
see RISC-V specs mentions it explicitly so don't feel confident to add
that.

> [1] - https://edk2.groups.io/g/devel/message/115243
>
> Thanks,
> Sunil
> > Regards,
> >
> > On Wed, Feb 14, 2024 at 10:16 PM Tuan Phan via groups.io <tphan=
> > ventanamicro.com@groups.io> wrote:
> >
> > >
> > >
> > > On Wed, Feb 14, 2024 at 9:43 PM Warkentin, Andrei <
> > > andrei.warkentin@intel.com> wrote:
> > >
> > >> Do you mind sharing a GH branch with the patch set?
> > >>
> > > https://github.com/pttuan/edk2/tree/tphan/riscv_mmu_svpbmt
> > > Tuan
> > >
> > >>
> > >> A
> > >>
> > >> > -----Original Message-----
> > >> > From: Tuan Phan <tphan@ventanamicro.com>
> > >> > Sent: Tuesday, February 6, 2024 7:29 PM
> > >> > To: devel@edk2.groups.io
> > >> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>;
> > >> > gaoliming@byosoft.com.cn; Liu, Zhiguang <zhiguang.liu@intel.com>;
> > >> > kraxel@redhat.com; lersek@redhat.com; Kumar, Rahul R
> > >> > <rahul.r.kumar@intel.com>; Ni, Ray <ray.ni@intel.com>;
> > >> > sunilvl@ventanamicro.com; Yao, Jiewen <jiewen.yao@intel.com>;
> > >> Warkentin,
> > >> > Andrei <andrei.warkentin@intel.com>; ardb+tianocore@kernel.org;
> Tuan
> > >> Phan
> > >> > <tphan@ventanamicro.com>
> > >> > Subject: [PATCH v2 0/3] RISC-V: Support Svpbmt extension
> > >> >
> > >> > This patchset adds support for RISC-V Svpbmt extension.
> > >> >
> > >> > The GCD EFI_MEMORY_UC and EFI_MEMORY_WC attributes will be mapped to
> > >> > IO and NC mode defined in PBMT field.
> > >> >
> > >> > v2:
> > >> >   - Generated patch for each package.
> > >> >
> > >> > Tuan Phan (3):
> > >> >   MdePkg.dec: RISC-V: Define override bit for Svpbmt extension
> > >> >   UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension
> > >> >   OvmfPkg/RiscVVirt: Override Svpbmt extension
> > >> >
> > >> >  MdePkg/MdePkg.dec                             |  2 ++
> > >> >  OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc           |  2 +-
> > >> >  .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 25
> ++++++++++++++++++-
> > >> >  .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf       |  1 +
> > >> >  4 files changed, 28 insertions(+), 2 deletions(-)
> > >> >
> > >> > --
> > >> > 2.25.1
> > >>
> > >> 
> > >
> > >
>


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Re: [edk2-devel] [PATCH v2 2/3] UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension

[Tuan Phan]

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On Wed, Feb 7, 2024 at 10:15 AM Laszlo Ersek <lersek@redhat.com> wrote:

> On 2/7/24 02:29, Tuan Phan wrote:
> > The GCD EFI_MEMORY_UC and EFI_MEMORY_WC attributes will be
> > supported when Svpbmt extension available.
> >
> > Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
> > ---
> >  .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 25 ++++++++++++++++++-
> >  .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf       |  1 +
> >  2 files changed, 25 insertions(+), 1 deletion(-)
> >
> > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > index 826a1d32a1d4..c50a28e97e4b 100644
> > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > @@ -36,6 +36,15 @@
> >  #define PTE_PPN_SHIFT         10
> >  #define RISCV_MMU_PAGE_SHIFT  12
> >
> > +#define RISCV_CPU_FEATURE_PBMT_BITMASK  BIT2
> > +#define PTE_PBMT_NC                     BIT61
> > +#define PTE_PBMT_IO                     BIT62
> > +#define PTE_PBMT_MASK                   (PTE_PBMT_NC | PTE_PBMT_IO)
> > +
> > +#define EFI_MEMORY_CACHETYPE_MASK  (EFI_MEMORY_UC | EFI_MEMORY_WC |  \
> > +                                     EFI_MEMORY_WT | EFI_MEMORY_WB | \
> > +                                     EFI_MEMORY_UCE)
> > +
>
> (1) I've stated this elsewhere -- introducing such a macro is justified,
> but calling it EFI_* is not. The EFI_ prefix is reserved for the spec.
>
Will fix it.


>
> >  STATIC UINTN  mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
> SATP_MODE_SV39, SATP_MODE_OFF };
> >  STATIC UINTN  mMaxRootTableLevel;
> >  STATIC UINTN  mBitPerLevel;
> > @@ -514,6 +523,20 @@ GcdAttributeToPageAttribute (
> >      RiscVAttributes &= ~RISCV_PG_X;
> >    }
> >
> > +  if ((PcdGet64 (PcdRiscVFeatureOverride) &
> RISCV_CPU_FEATURE_PBMT_BITMASK) != 0) {
> > +    switch (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) {
> > +      case EFI_MEMORY_UC:
> > +        RiscVAttributes |= PTE_PBMT_IO;
> > +        break;
> > +      case EFI_MEMORY_WC:
> > +        RiscVAttributes |= PTE_PBMT_NC;
> > +        break;
> > +      default:
> > +        // Default PMA mode
> > +        break;
> > +    }
> > +  }
> > +
> >    return RiscVAttributes;
> >  }
> >
>
> Several questions / observations:
>
> (2) If the feature is cleared in the PCD, does it deserve a warning that
> the attribute setting request cannot be honored?
>
Sure, I will add a warning if the feature has not been enabled.

>
> (3) The memory cacheability attributes are expressed as distinct bits of
> a bitmask because, for expressing *capabilities*, they must be possible
> to OR together. However, when setting actual attributes, I think the
> bitmask should contain *exactly* one bit set -- in other words, the
> value of the bitmask should be an integral power of two (that's not hard
> to check).
>
> Do you agree about this? If so, I'd suggest rejecting the request (with
> an appropriate status code) if zero bits, or multiple bits, are set.
>
>   UINT64  CacheTypeMask;
>
>   CacheType = GcdAttributes & MEMORY_CACHETYPE_MASK;
>   if ((CacheType == 0) ||
>       (((CacheType - 1) & CacheType) != 0)) {
>     return EFI_INVALID_PARAMETER;
>   }
>   switch (CacheType) {
>     ...
>   }
>
> This would of course require changing the GcdAttributeToPageAttribute()
> prototype, because right now the function cannot return an error.
>
> That makes sense. Will fix it. Thanks

>
> > @@ -559,7 +582,7 @@ RiscVSetMemoryAttributes (
> >             BaseAddress,
> >             Length,
> >             PageAttributesSet,
> > -           PTE_ATTRIBUTES_MASK,
> > +           PTE_ATTRIBUTES_MASK | PTE_PBMT_MASK,
> >             (UINTN *)RiscVGetRootTranslateTable (),
> >             TRUE
> >             );
>
> (4) I feel we shouldn't try to clear PTE_PBMT_MASK if
> PcdRiscVFeatureOverride tells us that Svpbmt is not available. Just a
> thought.
>
Sure.

>
> > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> > index 51ebe1750e97..1dbaa81f3608 100644
> > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> > @@ -28,3 +28,4 @@
> >
> >  [Pcd]
> >    gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode  ## CONSUMES
> > +  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride     ## CONSUMES
>
> Thanks
> Laszlo
>
>


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Re: [edk2-devel] [PATCH v2 0/3] RISC-V: Support Svpbmt extension

[Andrei Warkentin]

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I don’t think a warning message around EFI_MEMORY_UC is useful… it’s typical to request such a mapping for device MMIO (e.g. PciHostBridgeDxe, NonDiscoverablePciDeviceDxe, etc). On a system without PBMT yeah the M mode firmware will have to enforce the correct type, but that’s been true until now as well. Warning for _WC may make sense as it’s definitely not a “typical” mapping.

A

From: Tuan Phan <tphan@ventanamicro.com>
Sent: Monday, February 26, 2024 10:34 PM
To: Warkentin, Andrei <andrei.warkentin@intel.com>; sunilvl@ventanamicro.com
Cc: devel@edk2.groups.io; Kinney, Michael D <michael.d.kinney@intel.com>; gaoliming@byosoft.com.cn; Liu, Zhiguang <zhiguang.liu@intel.com>; kraxel@redhat.com; lersek@redhat.com; Kumar, Rahul R <rahul.r.kumar@intel.com>; Ni, Ray <ray.ni@intel.com>; Yao, Jiewen <jiewen.yao@intel.com>; ardb+tianocore@kernel.org
Subject: Re: [edk2-devel] [PATCH v2 0/3] RISC-V: Support Svpbmt extension

Hi Sunil/ Andrei,
Any comments on this series?

Regards,

On Wed, Feb 14, 2024 at 10:16 PM Tuan Phan via groups.io<http://groups.io> <tphan=ventanamicro.com@groups.io<mailto:ventanamicro.com@groups.io>> wrote:


On Wed, Feb 14, 2024 at 9:43 PM Warkentin, Andrei <andrei.warkentin@intel.com<mailto:andrei.warkentin@intel.com>> wrote:
Do you mind sharing a GH branch with the patch set?
https://github.com/pttuan/edk2/tree/tphan/riscv_mmu_svpbmt
Tuan

A

> -----Original Message-----
> From: Tuan Phan <tphan@ventanamicro.com<mailto:tphan@ventanamicro.com>>
> Sent: Tuesday, February 6, 2024 7:29 PM
> To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>
> Cc: Kinney, Michael D <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>;
> gaoliming@byosoft.com.cn<mailto:gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com<mailto:zhiguang.liu@intel.com>>;
> kraxel@redhat.com<mailto:kraxel@redhat.com>; lersek@redhat.com<mailto:lersek@redhat.com>; Kumar, Rahul R
> <rahul.r.kumar@intel.com<mailto:rahul.r.kumar@intel.com>>; Ni, Ray <ray.ni@intel.com<mailto:ray.ni@intel.com>>;
> sunilvl@ventanamicro.com<mailto:sunilvl@ventanamicro.com>; Yao, Jiewen <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>; Warkentin,
> Andrei <andrei.warkentin@intel.com<mailto:andrei.warkentin@intel.com>>; ardb+tianocore@kernel.org<mailto:ardb%2Btianocore@kernel.org>; Tuan Phan
> <tphan@ventanamicro.com<mailto:tphan@ventanamicro.com>>
> Subject: [PATCH v2 0/3] RISC-V: Support Svpbmt extension
>
> This patchset adds support for RISC-V Svpbmt extension.
>
> The GCD EFI_MEMORY_UC and EFI_MEMORY_WC attributes will be mapped to
> IO and NC mode defined in PBMT field.
>
> v2:
>   - Generated patch for each package.
>
> Tuan Phan (3):
>   MdePkg.dec: RISC-V: Define override bit for Svpbmt extension
>   UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension
>   OvmfPkg/RiscVVirt: Override Svpbmt extension
>
>  MdePkg/MdePkg.dec                             |  2 ++
>  OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc           |  2 +-
>  .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 25 ++++++++++++++++++-
>  .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf       |  1 +
>  4 files changed, 28 insertions(+), 2 deletions(-)
>
> --
> 2.25.1



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