From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 3336CAC0ACB for ; Wed, 14 Feb 2024 12:44:09 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=Ph/Wug1RZSkFTyNJ0hgoFnPXWnstA0sant832H6z+5s=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1707914647; v=1; b=D4yflK/6zEbMDAqCBZtjiNEQC74tOBelVKgIAL92svRyFgBfDyMEVSraUYyFGuU/OEOgqqRX NnN/lBhqVuN31DRwmBdyaUC8oD9BCBcFQkH/B3mmZQnF8MmElafBzIxFq3MUHNjK7kb912bDSZY Ooo74QQK1ubTSCjo+Xtv+iQY= X-Received: by 127.0.0.2 with SMTP id jssjYY7687511xMTyXg6KfoZ; Wed, 14 Feb 2024 04:44:07 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.40680.1707914647179455265 for ; Wed, 14 Feb 2024 04:44:07 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E36EC1FB; Wed, 14 Feb 2024 04:44:47 -0800 (PST) X-Received: from e126645.home (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 06FBB3F5A1; Wed, 14 Feb 2024 04:44:04 -0800 (PST) From: "PierreGondois" To: devel@edk2.groups.io Cc: Thomas Abraham , Ard Biesheuvel , Leif Lindholm , Sami Mujawar , Pierre Gondois Subject: [edk2-devel] [PATCH 2/3] Platform/ARM: Remove CTA15-A7 platform support Date: Wed, 14 Feb 2024 13:43:47 +0100 Message-Id: <20240214124348.310345-3-Pierre.Gondois@arm.com> In-Reply-To: <20240214124348.310345-1-Pierre.Gondois@arm.com> References: <20240214124348.310345-1-Pierre.Gondois@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pierre.gondois@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: DvqwksDuqrVOyxAZRSKSJ0rzx7686176AA= Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b="D4yflK/6"; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=arm.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io From: Pierre Gondois Remove CTA15-A7 platform support. This effort was started by: https://edk2.groups.io/g/devel/message/115378 Signed-off-by: Pierre Gondois --- .../ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc | 286 ----------------- .../ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf | 299 ------------------ .../Include/Platform/CTA15-A7/ArmPlatform.h | 148 --------- .../ArmVExpressLibCTA15-A7/ArmVExpressLib.inf | 44 --- .../Library/ArmVExpressLibCTA15-A7/CTA15-A7.c | 176 ----------- .../ArmVExpressLibCTA15-A7/CTA15-A7Helper.S | 75 ----- .../ArmVExpressLibCTA15-A7/CTA15-A7Mem.c | 172 ---------- 7 files changed, 1200 deletions(-) delete mode 100644 Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc delete mode 100644 Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf delete mode 100644 Platform/ARM/VExpressPkg/Include/Platform/CTA15-A7/Ar= mPlatform.h delete mode 100644 Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-= A7/ArmVExpressLib.inf delete mode 100644 Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-= A7/CTA15-A7.c delete mode 100644 Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-= A7/CTA15-A7Helper.S delete mode 100644 Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-= A7/CTA15-A7Mem.c diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc b/Platform= /ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc deleted file mode 100644 index 6495e08db590..000000000000 --- a/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc +++ /dev/null @@ -1,286 +0,0 @@ -# -# Copyright (c) 2012-2018, ARM Limited. All rights reserved. -# Copyright (c) 2015, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# - -########################################################################= ######## -# -# Defines Section - statements that will be processed to create a Makefi= le. -# -########################################################################= ######## -[Defines] - PLATFORM_NAME =3D ArmVExpressPkg-CTA15-A7 - PLATFORM_GUID =3D 0b511920-978d-4b34-acc0-3d9f8e6f9d8= 1 - PLATFORM_VERSION =3D 0.1 - DSC_SPECIFICATION =3D 0x00010005 -!ifdef $(EDK2_OUT_DIR) - OUTPUT_DIRECTORY =3D $(EDK2_OUT_DIR) -!else - OUTPUT_DIRECTORY =3D Build/ArmVExpress-CTA15-A7 -!endif - SUPPORTED_ARCHITECTURES =3D ARM - BUILD_TARGETS =3D DEBUG|RELEASE - SKUID_IDENTIFIER =3D DEFAULT - FLASH_DEFINITION =3D Platform/ARM/VExpressPkg/ArmVExpres= s-CTA15-A7.fdf - - DEFINE EDK2_SKIP_PEICORE =3D 1 - DEFINE ARM_BIGLITTLE_TC2 =3D 1 # We build for the TC2 hardware by defa= ult - -!include Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc -!include MdePkg/MdeLibs.dsc.inc - -[LibraryClasses.common] - ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf - ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf - ArmPlatformLib|Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7= /ArmVExpressLib.inf - - ArmPlatformSysConfigLib|Platform/ARM/VExpressPkg/Library/ArmVExpressSy= sConfigLib/ArmVExpressSysConfigLib.inf - - #DebugAgentTimerLib|Platform/ARM/VExpressPkg/Library/DebugAgentTimerLi= b/DebugAgentTimerLib.inf - - # ARM General Interrupt Driver in Secure and Non-secure - ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf - - LcdHwLib|ArmPlatformPkg/Library/HdLcd/HdLcd.inf - LcdPlatformLib|Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/Hd= LcdArmVExpressLib.inf - - ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf - -[LibraryClasses.common.DXE_RUNTIME_DRIVER] - ArmPlatformSysConfigLib|Platform/ARM/VExpressPkg/Library/ArmVExpressSy= sConfigRuntimeLib/ArmVExpressSysConfigRuntimeLib.inf - -[LibraryClasses.ARM] - ArmSoftFloatLib|ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.inf - # - # PSCI support in EL3 may not be available if we are not running under= a PSCI - # compliant secure firmware. Assume PSCI on AARCH64, and fall back to = the - # syscfg MMIO register implementation on ARM. - # This will not work at actual runtime. - # - ResetSystemLib|Platform/ARM/VExpressPkg/Library/ResetSystemLib/ResetSy= stemLib.inf - -[BuildOptions] -!ifdef ARM_BIGLITTLE_TC2 - *_*_ARM_PP_FLAGS =3D -DARM_BIGLITTLE_TC2=3D1 -!endif - - GCC:*_*_ARM_PLATFORM_FLAGS =3D=3D -mcpu=3Dcortex-a15 -I$(WORKSPACE)/Pl= atform/ARM/VExpressPkg/Include/Platform/CTA15-A7 - - XCODE:*_*_ARM_PLATFORM_FLAGS =3D -I$(WORKSPACE)/Platform/ARM/VExpressP= kg/Include/Platform/CTA15-A7 - -########################################################################= ######## -# -# Pcd Section - list of all EDK II PCD Entries defined by this Platform -# -########################################################################= ######## - -[PcdsFeatureFlag.common] - gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|TRUE - gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE - - ## If TRUE, Graphics Output Protocol will be installed on virtual hand= le created by ConsplitterDxe. - # It could be set FALSE to save size. - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE - -[PcdsFixedAtBuild.common] - gArmVExpressTokenSpaceGuid.PcdAndroidFastbootProductName|"ARM Versatil= e Express" - - gArmPlatformTokenSpaceGuid.PcdCoreCount|5 - - # - # NV Storage PCDs. Use base of 0x0C000000 for NOR1 - # - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FFC000= 0 - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x0001000= 0 - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FFD0= 000 - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010= 000 - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE000= 0 - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x0001000= 0 - - gArmTokenSpaceGuid.PcdVFPEnabled|1 - - # System Memory (1GB) - An additional 1GB will be added if UEFI is run= ning on a 2GB Test Chip - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 - gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 - -!ifdef ARM_BIGLITTLE_TC2 - # TC2 Dual-Cluster profile - gArmPlatformTokenSpaceGuid.PcdClusterCount|2 - - # Core Ids and Gic values - # A15_0 =3D 0x000, GicCoreId =3D 0 - # A15_1 =3D 0x001, GicCoreId =3D 1 - # A7_0 =3D 0x100, GicCoreId =3D 2 - # A7_1 =3D 0x101, GicCoreId =3D 3 - # A7_2 =3D 0x102, GicCoreId =3D 4 - gArmTokenSpaceGuid.PcdArmPrimaryCore|0x100 -!endif - - # - # ARM PrimeCell - # - - ## SP805 Watchdog - Motherboard Watchdog - gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x1C0F0000 - - ## PL011 - Serial Terminal - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1C090000 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 - - ## PL031 RealTimeClock - gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000 - -!ifdef ARM_BIGLITTLE_TC2 - ## PL111 Lcd & HdLcd - gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000 - gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x2B000000 - gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId|5 -!endif - - # - # PL180 MMC/SD card controller - # - gArmVExpressTokenSpaceGuid.PcdPL180SysMciRegAddress|0x1C010048 - gArmVExpressTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000 - - - # - # ARM Generic Interrupt Controller - # - gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000 - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000 - - # ISP1761 USB OTG Controller - gArmVExpressTokenSpaceGuid.PcdIsp1761BaseAddress|0x1B000000 - - # Ethernet (SMSC LAN9118) - gArmVExpressTokenSpaceGuid.PcdLan9118DxeBaseAddress|0x1A000000 - gArmVExpressTokenSpaceGuid.PcdLan9118DefaultNegotiationTimeout|400000 - - # - # Define the device path to the FDT for the platform - # - gFdtPlatformDxeTokenSpaceGuid.PcdFdtDevicePaths|L"VenHw(DE6AE758-D662-= 4E17-A97C-4C5964DA4C41,00)/ca15a7" - - # - # ARM Architectural Timer Frequency - # -!ifdef ARM_BIGLITTLE_TC2 - gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|24000000 -!else - gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|10000000 -!endif - -########################################################################= ######## -# -# Components Section - list of all EDK II Modules needed by this Platfor= m -# -########################################################################= ######## -[Components.common] - # - # PEI Phase modules - # - ArmPlatformPkg/PrePi/PeiMPCore.inf { - - ArmPlatformLib|Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA1= 5-A7/ArmVExpressLib.inf - } - - # - # DXE - # - MdeModulePkg/Core/Dxe/DxeMain.inf { - - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32= GuidedSectionExtractLib.inf - } - - # - # Architectural Protocols - # - ArmPkg/Drivers/CpuDxe/CpuDxe.inf - MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf - MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { - - NULL|EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormatte= dLib.inf - NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf - BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf - } - MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf - MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRunt= imeDxe.inf - MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf - EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf - EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf - - MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf - MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf - MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.i= nf - MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf - MdeModulePkg/Universal/SerialDxe/SerialDxe.inf - - MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf - - ArmPkg/Drivers/ArmGic/ArmGicDxe.inf - Platform/ARM/Drivers/NorFlashDxe/NorFlashDxe.inf - ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf - ArmPkg/Drivers/TimerDxe/TimerDxe.inf - ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf - - # - # Platform - # - Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmHwDxe.inf - - # - # Filesystems - # -!ifndef ARM_BIGLITTLE_TC2 - ArmPkg/Filesystem/SemihostFs/SemihostFs.inf -!endif - - # - # Multimedia Card Interface - # - EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf - Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180MciDxe.inf - - # SMSC LAN 9118 - Platform/ARM/VExpressPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf - - # - # FAT filesystem + GPT/MBR partitioning - # - MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf - MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf - MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf - FatPkg/EnhancedFatDxe/Fat.inf - MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf - - # - # Bds - # - MdeModulePkg/Universal/BootManagerPolicyDxe/BootManagerPolicyDxe.inf - MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf - MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf - MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - MdeModulePkg/Universal/BdsDxe/BdsDxe.inf - MdeModulePkg/Application/UiApp/UiApp.inf { - - NULL|MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPo= licyUiLib.inf - NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.in= f - NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf - NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintena= nceManagerUiLib.inf - } - - # - # FDT installation - # - Platform/ARM/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf { - - BdsLib|Platform/ARM/Library/BdsLib/BdsLib.inf - } diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf b/Platform= /ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf deleted file mode 100644 index 73c4ddb0995b..000000000000 --- a/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf +++ /dev/null @@ -1,299 +0,0 @@ -# -# Copyright (c) 2012-2015, ARM Limited. All rights reserved. -# Copyright (c) 2015, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# - -########################################################################= ######## -# -# FD Section -# The [FD] Section is made up of the definition statements and a -# description of what goes into the Flash Device Image. Each FD sectio= n -# defines one flash "device" image. A flash device image may be one of -# the following: Removable media bootable image (like a boot floppy -# image,) an Option ROM image (that would be "flashed" into an add-in -# card,) a System "Flash" image (that would be burned into a system's -# flash) or an Update ("Capsule") image that will be used to update and -# existing system flash. -# -########################################################################= ######## - -[FD.ARM_VEXPRESS_CTA15A7_EFI] -BaseAddress =3D 0xB0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The = base address of the Firmware in remapped DRAM. -Size =3D 0x000E0000|gArmTokenSpaceGuid.PcdFdSize # The = size in bytes of the FLASH Device -ErasePolarity =3D 1 -BlockSize =3D 0x00001000 -NumBlocks =3D 0xE0 - -0x00000000|0x000E0000 -gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize -FV =3D FVMAIN_COMPACT - -########################################################################= ######## -# -# FV Section -# -# [FV] section is used to define what components or modules are placed w= ithin a flash -# device file. This section also defines order the components and modul= es are positioned -# within the image. The [FV] section consists of define statements, set= statements and -# module statements. -# -########################################################################= ######## -[FV.FvMain] -BlockSize =3D 0x40 -NumBlocks =3D 0 # This FV gets compressed so make it ju= st big enough -FvAlignment =3D 8 # FV alignment and FV attributes settin= g. -ERASE_POLARITY =3D 1 -MEMORY_MAPPED =3D TRUE -STICKY_WRITE =3D TRUE -LOCK_CAP =3D TRUE -LOCK_STATUS =3D TRUE -WRITE_DISABLED_CAP =3D TRUE -WRITE_ENABLED_CAP =3D TRUE -WRITE_STATUS =3D TRUE -WRITE_LOCK_CAP =3D TRUE -WRITE_LOCK_STATUS =3D TRUE -READ_DISABLED_CAP =3D TRUE -READ_ENABLED_CAP =3D TRUE -READ_STATUS =3D TRUE -READ_LOCK_CAP =3D TRUE -READ_LOCK_STATUS =3D TRUE -FvNameGuid =3D 73dcb643-3862-4904-9076-a94af1890243 - - INF MdeModulePkg/Core/Dxe/DxeMain.inf - - # - # PI DXE Drivers producing Architectural Protocols (EFI Services) - # - INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf - INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf - INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf - INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe= .inf - INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounter= RuntimeDxe.inf - INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe= .inf - INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf - INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf - - INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf - - # - # Multiple Console IO support - # - INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf - INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf - INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleD= xe.inf - INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf - INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf - - INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf - INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf - INF Platform/ARM/Drivers/NorFlashDxe/NorFlashDxe.inf - INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.i= nf - INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf - - # - # Platform - # - INF Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmHwDxe.inf - - # - # Multimedia Card Interface - # - INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf - INF Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180MciDxe.inf - - # - # Filesystems - # -!ifndef $(ARM_BIGLITTLE_TC2) - INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf -!endif - - # - # FAT filesystem + GPT/MBR partitioning - # - INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf - INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf - INF FatPkg/EnhancedFatDxe/Fat.inf - INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe= .inf - - # Versatile Express FileSystem - INF Platform/ARM/Drivers/BootMonFs/BootMonFs.inf - - # - # USB support - # - INF Platform/ARM/VExpressPkg/Drivers/Isp1761UsbDxe/Isp1761UsbDxe.inf - - # - # Android Fastboot - # - INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf - INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTranspo= rtUsbDxe.inf - INF Platform/ARM/VExpressPkg/Drivers/ArmVExpressFastBootDxe/ArmVExpres= sFastBootDxe.inf - - # ACPI Support - INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf - - # - # Networking stack - # -!include Platform/ARM/VExpressPkg/ArmVExpress-networking.fdf.inc - - INF Platform/ARM/VExpressPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf - - # - # UEFI application - # - INF ShellPkg/Application/Shell/Shell.inf - - # - # Bds - # - INF MdeModulePkg/Universal/BootManagerPolicyDxe/BootManagerPolicyDxe.i= nf - INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf - INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf - INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf - INF MdeModulePkg/Application/UiApp/UiApp.inf - - # FV Filesystem - INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe= .inf - - # - # FDT installation - # - # The UEFI driver is at the end of the list of the driver to be dispat= ched - # after the device drivers (eg: Ethernet) to ensure we have support fo= r them. - INF Platform/ARM/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf - - # Example to add a Device Tree to the Firmware Volume - #FILE FREEFORM =3D PCD(gArmVExpressTokenSpaceGuid.PcdFdtVExpressHwA15x= 2A7x3) { - # SECTION RAW =3D Platform/ARM/VExpressPkg/Fdts/vexpress-v2p-ca15_a7.= dtb - #} - -[FV.FVMAIN_COMPACT] -FvBaseAddress =3D 0xB0000000 -FvForceRebase =3D TRUE -FvAlignment =3D 8 -ERASE_POLARITY =3D 1 -MEMORY_MAPPED =3D TRUE -STICKY_WRITE =3D TRUE -LOCK_CAP =3D TRUE -LOCK_STATUS =3D TRUE -WRITE_DISABLED_CAP =3D TRUE -WRITE_ENABLED_CAP =3D TRUE -WRITE_STATUS =3D TRUE -WRITE_LOCK_CAP =3D TRUE -WRITE_LOCK_STATUS =3D TRUE -READ_DISABLED_CAP =3D TRUE -READ_ENABLED_CAP =3D TRUE -READ_STATUS =3D TRUE -READ_LOCK_CAP =3D TRUE -READ_LOCK_STATUS =3D TRUE - - INF ArmPlatformPkg/PrePi/PeiMPCore.inf - - FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUI= RED =3D TRUE { - SECTION FV_IMAGE =3D FVMAIN - } - } - - -########################################################################= ######## -# -# Rules are use with the [FV] section's module INF type to define -# how an FFS file is created for a given INF file. The following Rule ar= e the default -# rules for the different module type. User can add the customized rules= to define the -# content of the FFS file. -# -########################################################################= ######## - - -########################################################################= #### -# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section= # -########################################################################= #### -# -#[Rule.Common.DXE_DRIVER] -# FILE DRIVER =3D $(NAMED_GUID) { -# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODUL= E_NAME).depex -# COMPRESS PI_STD { -# GUIDED { -# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).e= fi -# UI STRING=3D"$(MODULE_NAME)" Optional -# VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD= _NUMBER) -# } -# } -# } -# -########################################################################= #### - -[Rule.Common.SEC] - FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED { - TE TE Align =3D 32 $(INF_OUTPUT)/$(MODULE_NAME).e= fi - } - -[Rule.Common.PEI_CORE] - FILE PEI_CORE =3D $(NAMED_GUID) { - TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING =3D"$(MODULE_NAME)" Optional - } - -[Rule.Common.PEIM] - FILE PEIM =3D $(NAMED_GUID) { - PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).dep= ex - TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING=3D"$(MODULE_NAME)" Optional - } - -[Rule.Common.DXE_CORE] - FILE DXE_CORE =3D $(NAMED_GUID) { - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING=3D"$(MODULE_NAME)" Optional - } - -[Rule.Common.UEFI_DRIVER] - FILE DRIVER =3D $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_= NAME).depex - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING=3D"$(MODULE_NAME)" Optional - } - -[Rule.Common.DXE_DRIVER] - FILE DRIVER =3D $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_= NAME).depex - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING=3D"$(MODULE_NAME)" Optional - } - -[Rule.Common.DXE_RUNTIME_DRIVER] - FILE DRIVER =3D $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_= NAME).depex - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING=3D"$(MODULE_NAME)" Optional - } - -[Rule.Common.UEFI_APPLICATION] - FILE APPLICATION =3D $(NAMED_GUID) { - UI STRING =3D"$(MODULE_NAME)" Optional - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - } - -[Rule.Common.UEFI_DRIVER.BINARY] - FILE DRIVER =3D $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional |.depex - PE32 PE32 |.efi - UI STRING=3D"$(MODULE_NAME)" Optional - VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUM= BER) - } - -[Rule.Common.UEFI_APPLICATION.BINARY] - FILE APPLICATION =3D $(NAMED_GUID) { - PE32 PE32 |.efi - UI STRING=3D"$(MODULE_NAME)" Optional - VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUM= BER) - } diff --git a/Platform/ARM/VExpressPkg/Include/Platform/CTA15-A7/ArmPlatfo= rm.h b/Platform/ARM/VExpressPkg/Include/Platform/CTA15-A7/ArmPlatform.h deleted file mode 100644 index db6303a05f2a..000000000000 --- a/Platform/ARM/VExpressPkg/Include/Platform/CTA15-A7/ArmPlatform.h +++ /dev/null @@ -1,148 +0,0 @@ -/** @file -* Header defining Versatile Express constants (Base addresses, sizes, f= lags) -* -* Copyright (c) 2012, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef __ARM_VEXPRESS_CTA15A7_H__ -#define __ARM_VEXPRESS_CTA15A7_H__ - -#include - -/***********************************************************************= ************ -// Platform Memory Map -************************************************************************= ************/ - -// Motherboard Peripheral and On-chip peripheral -#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000 - -#ifdef ARM_BIGLITTLE_TC2 - -// Secure NOR Flash -#define ARM_VE_SEC_NOR0_BASE 0x00000000 -#define ARM_VE_SEC_NOR0_SZ SIZE_64MB - -// Secure RAM -#define ARM_VE_SEC_RAM0_BASE 0x04000000 -#define ARM_VE_SEC_RAM0_SZ SIZE_64MB - -#endif - -// NOR Flash 0 -#define ARM_VE_SMB_NOR0_BASE 0x08000000 -#define ARM_VE_SMB_NOR0_SZ SIZE_64MB -// NOR Flash 1 -#define ARM_VE_SMB_NOR1_BASE 0x0C000000 -#define ARM_VE_SMB_NOR1_SZ SIZE_64MB - -// SRAM -#define ARM_VE_SMB_SRAM_BASE 0x14000000 -#define ARM_VE_SMB_SRAM_SZ SIZE_32MB - -// USB, Ethernet, VRAM -#ifdef ARM_BIGLITTLE_TC2 -#define ARM_VE_SMB_PERIPH_BASE 0x18000000 -#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_32MB + S= IZE_16MB) -#else -#define ARM_VE_SMB_PERIPH_BASE 0x1C000000 -#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_16MB) -#endif -#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE - -// On-Chip non-secure ROM -#ifdef ARM_BIGLITTLE_TC2 -#define ARM_VE_TC2_NON_SECURE_ROM_BASE 0x1F000000 -#define ARM_VE_TC2_NON_SECURE_ROM_SZ SIZE_16MB -#endif - -// On-Chip Peripherals -#define ARM_VE_ONCHIP_PERIPH_BASE 0x20000000 -#define ARM_VE_ONCHIP_PERIPH_SZ 0x10000000 - -// On-Chip non-secure SRAM -#ifdef ARM_BIGLITTLE_TC2 -#define ARM_VE_TC2_NON_SECURE_SRAM_BASE 0x2E000000 -#define ARM_VE_TC2_NON_SECURE_SRAM_SZ SIZE_64KB -#endif - -// Allocate a section for the VRAM (Video RAM) -// If 0 then allow random memory allocation -#define LCD_VRAM_CORE_TILE_BASE 0 - -// Define SEC phase sync point -#define ARM_SEC_EVENT_BOOT_IMAGE_TABLE_IS_AVAILABLE (ARM_SEC_EVENT_MAX= + 1) - -/***********************************************************************= ************ - Core Tile memory-mapped Peripherals -************************************************************************= ************/ - -// PL354 Static Memory Controller Base -#ifdef ARM_BIGLITTLE_TC2 -#define ARM_VE_SMC_CTRL_BASE 0x7FFD0000 -#else -#define ARM_VE_SMC_CTRL_BASE (ARM_VE_BOARD_PERIPH_BAS= E + 0xE1000) -#endif - -#define ARM_CTA15A7_SCC_BASE 0x7FFF0000 -#define ARM_CTA15A7_SCC_CFGREG48 (ARM_CTA15A7_SCC_BASE + = 0x700) - -#define ARM_CTA15A7_SCC_SYSINFO ARM_CTA15A7_SCC_CFGREG48 - -#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A7_NUM_CPU(val) (((val) = >> 20) & 0xF) -#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A15_NUM_CPU(val) (((val) = >> 16) & 0xF) -#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A15 (1 << 0) -#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A7 (1 << 1) -#define ARM_CTA15A7_SCC_SYSINFO_UEFI_RESTORE_DEFAULT_NORFLASH (1 << 4) - -#define ARM_CTA15A7_SPC_BASE 0x7FFF0B00 -#define ARM_CTA15A7_SPC_WAKE_INT_MASK (ARM_CTA15A7_SPC_BASE + = 0x24) -#define ARM_CTA15A7_SPC_STANDBYWFI_STAT (ARM_CTA15A7_SPC_BASE + = 0x3C) -#define ARM_CTA15A7_SPC_A15_BX_ADDR0 (ARM_CTA15A7_SPC_BASE + = 0x68) -#define ARM_CTA15A7_SPC_A15_BX_ADDR1 (ARM_CTA15A7_SPC_BASE + = 0x6C) -#define ARM_CTA15A7_SPC_A15_BX_ADDR2 (ARM_CTA15A7_SPC_BASE + = 0x70) -#define ARM_CTA15A7_SPC_A15_BX_ADDR3 (ARM_CTA15A7_SPC_BASE + = 0x74) -#define ARM_CTA15A7_SPC_A7_BX_ADDR0 (ARM_CTA15A7_SPC_BASE + = 0x78) -#define ARM_CTA15A7_SPC_A7_BX_ADDR1 (ARM_CTA15A7_SPC_BASE + = 0x7C) -#define ARM_CTA15A7_SPC_A7_BX_ADDR2 (ARM_CTA15A7_SPC_BASE + = 0x80) -#define ARM_CTA15A7_SPC_A7_BX_ADDR3 (ARM_CTA15A7_SPC_BASE + = 0x84) - -#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_0 (1 << 0) -#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_1 (1 << 1) -#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_0 (1 << 2) -#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_1 (1 << 3) -#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_0 (1 << 4) -#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_1 (1 << 5) -#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_2 (1 << 6) -#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_0 (1 << 7) -#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_1 (1 << 8) -#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_2 (1 << 9) - -#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_0 (1 << 0) -#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_1 (1 << 1) -#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_L2 (1 << 2) -#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_0 (1 << 3) -#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_1 (1 << 4) -#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_2 (1 << 5) -#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_L2 (1 << 6) - - -/***********************************************************************= ************ -// Memory-mapped peripherals -************************************************************************= ************/ - -/*// SP810 Controller -#undef SP810_CTRL_BASE -#define SP810_CTRL_BASE 0x1C020000 - -// PL111 Colour LCD Controller -#define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE -#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1 -#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1 - -// VRAM offset for the PL111 Colour LCD Controller on the motherboard -#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BAS= E + 0x00000)*/ - -#endif diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmV= ExpressLib.inf b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/= ArmVExpressLib.inf deleted file mode 100644 index dbe4cb88fd21..000000000000 --- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpress= Lib.inf +++ /dev/null @@ -1,44 +0,0 @@ -#/* @file -# -# Copyright (c) 2011-2012, ARM Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#*/ - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D CTA15A7ArmVExpressLib - FILE_GUID =3D b98a6cb7-d472-4128-ad62-a7347f85ce1= 3 - MODULE_TYPE =3D BASE - VERSION_STRING =3D 1.0 - LIBRARY_CLASS =3D ArmPlatformLib - -[Packages] - ArmPlatformPkg/ArmPlatformPkg.dec - ArmPkg/ArmPkg.dec - EmbeddedPkg/EmbeddedPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - Platform/ARM/VExpressPkg/ArmVExpressPkg.dec - -[LibraryClasses] - IoLib - ArmLib - MemoryAllocationLib - SerialPortLib - -[Sources.common] - CTA15-A7.c - CTA15-A7Mem.c - CTA15-A7Helper.S - -[FixedPcd] - gArmPlatformTokenSpaceGuid.PcdCoreCount - - gArmTokenSpaceGuid.PcdSystemMemoryBase - gArmTokenSpaceGuid.PcdSystemMemorySize - gArmTokenSpaceGuid.PcdFvBaseAddress - -[Ppis] - gArmMpCoreInfoPpiGuid diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA1= 5-A7.c b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7= .c deleted file mode 100644 index d51784a47c0e..000000000000 --- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7.c +++ /dev/null @@ -1,176 +0,0 @@ -/** @file -* -* Copyright (c) 2012, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include - -#include - -#include - -ARM_CORE_INFO mVersatileExpressCTA15A7InfoTable[] =3D { - { - // Cluster 0, Core 0 - 0x000, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0, - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0, - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0, - (UINT64)0 - }, - { - // Cluster 0, Core 1 - 0x001, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1, - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1, - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1, - (UINT64)0 - }, -#ifndef ARM_BIGLITTLE_TC2 - { - // Cluster 0, Core 2 - 0x002, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2, - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2, - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2, - (UINT64)0 - }, - { - // Cluster 0, Core 3 - 0x003, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3, - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3, - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3, - (UINT64)0 - }, -#endif - { - // Cluster 1, Core 0 - 0x100, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0, - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0, - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0, - (UINT64)0 - }, - { - // Cluster 1, Core 1 - 0x101, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1, - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1, - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1, - (UINT64)0 - }, - { - // Cluster 1, Core 2 - 0x102, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2, - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2, - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2, - (UINT64)0 - } -#ifndef ARM_BIGLITTLE_TC2 - ,{ - // Cluster 1, Core 3 - 0x103, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3, - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3, - (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3, - (UINT64)0 - } -#endif -}; - -/** - Return the current Boot Mode - - This function returns the boot reason on the platform - - @return Return the current Boot Mode of the platform - -**/ -EFI_BOOT_MODE -ArmPlatformGetBootMode ( - VOID - ) -{ - if (MmioRead32(ARM_CTA15A7_SCC_SYSINFO) & ARM_CTA15A7_SCC_SYSINFO_UEFI= _RESTORE_DEFAULT_NORFLASH) { - return BOOT_WITH_DEFAULT_SETTINGS; - } else { - return BOOT_WITH_FULL_CONFIGURATION; - } -} - -/** - Initialize controllers that must setup in the normal world - - This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pe= i/PlatformPeim - in the PEI phase. - -**/ -RETURN_STATUS -ArmPlatformInitialize ( - IN UINTN MpId - ) -{ - if (!ArmPlatformIsPrimaryCore (MpId)) { - return RETURN_SUCCESS; - } - - // Nothing to do here - - return RETURN_SUCCESS; -} - -EFI_STATUS -PrePeiCoreGetMpCoreInfo ( - OUT UINTN *CoreCount, - OUT ARM_CORE_INFO **ArmCoreTable - ) -{ - // Only support one cluster - *CoreCount =3D sizeof(mVersatileExpressCTA15A7InfoTable) / sizeof(A= RM_CORE_INFO); - *ArmCoreTable =3D mVersatileExpressCTA15A7InfoTable; - return EFI_SUCCESS; -} - -ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; - -EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { - { - EFI_PEI_PPI_DESCRIPTOR_PPI, - &gArmMpCoreInfoPpiGuid, - &mMpCoreInfoPpi - } -}; - -VOID -ArmPlatformGetPlatformPpiList ( - OUT UINTN *PpiListSize, - OUT EFI_PEI_PPI_DESCRIPTOR **PpiList - ) -{ - *PpiListSize =3D sizeof(gPlatformPpiTable); - *PpiList =3D gPlatformPpiTable; -} diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA1= 5-A7Helper.S b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CT= A15-A7Helper.S deleted file mode 100644 index b7ee78aa094a..000000000000 --- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Hel= per.S +++ /dev/null @@ -1,75 +0,0 @@ -// -// Copyright (c) 2012-2013, ARM Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// - -#include -#include - -#include - -ASM_FUNC(ArmPlatformPeiBootAction) - bx lr - -//UINTN -//ArmPlatformGetCorePosition ( -// IN UINTN MpId -// ); -ASM_FUNC(ArmPlatformGetCorePosition) - and r1, r0, #ARM_CORE_MASK - and r0, r0, #ARM_CLUSTER_MASK - add r0, r1, r0, LSR #7 - bx lr - -//UINTN -//ArmPlatformIsPrimaryCore ( -// IN UINTN MpId -// ); -ASM_FUNC(ArmPlatformIsPrimaryCore) - // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48 - // with cpu_id[0:3] and cluster_id[4:7] - MOV32 (r1, ARM_CTA15A7_SCC_CFGREG48) - ldr r1, [r1] - lsr r1, #24 - - // Shift the SCC value to get the cluster ID at the offset #8 - lsl r2, r1, #4 - and r2, r2, #0xF00 - - // Keep only the cpu ID from the original SCC - and r1, r1, #0x0F - // Add the Cluster ID to the Cpu ID - orr r1, r1, r2 - - // Keep the Cluster ID and Core ID from the MPID - MOV32 (r2, ARM_CLUSTER_MASK | ARM_CORE_MASK) - and r0, r0, r2 - - // Compare mpid and boot cpu from ARM_SCC_CFGREG48 - cmp r0, r1 - moveq r0, #1 - movne r0, #0 - bx lr - -//UINTN -//ArmPlatformGetPrimaryCoreMpId ( -// VOID -// ); -ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) - // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48 - // with cpu_id[0:3] and cluster_id[4:7] - MOV32 (r0, ARM_CTA15A7_SCC_CFGREG48) - ldr r0, [r0] - lsr r0, #24 - - // Shift the SCC value to get the cluster ID at the offset #8 - lsl r1, r0, #4 - and r1, r1, #0xF00 - - // Keep only the cpu ID from the original SCC - and r0, r0, #0x0F - // Add the Cluster ID to the Cpu ID - orr r0, r0, r1 - bx lr diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA1= 5-A7Mem.c b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15= -A7Mem.c deleted file mode 100644 index 66dfda660f56..000000000000 --- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem= .c +++ /dev/null @@ -1,172 +0,0 @@ -/** @file -* -* Copyright (c) 2012, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include -#include -#include - -#include - -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 14 - -// DDR attributes -#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRIT= E_BACK -#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCA= CHED_UNBUFFERED - -/** - Return the Virtual Memory Map of your platform - - This Virtual Memory Map is used by MemoryInitPei Module to initialize = the MMU on your platform. - - @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTO= R describing a Physical-to- - Virtual Memory mapping. This array m= ust be ended by a zero-filled - entry - -**/ -VOID -ArmPlatformGetVirtualMemoryMap ( - IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap - ) -{ - ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; - UINTN Index =3D 0; - ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; - - ASSERT (VirtualMemoryMap !=3D NULL); - - VirtualMemoryTable =3D (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EF= I_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMOR= Y_MAP_DESCRIPTORS)); - if (VirtualMemoryTable =3D=3D NULL) { - return; - } - - CacheAttributes =3D DDR_ATTRIBUTES_CACHED; - -#ifdef ARM_BIGLITTLE_TC2 - // Secure NOR0 Flash - VirtualMemoryTable[Index].PhysicalBase =3D ARM_VE_SEC_NOR0_BASE; - VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_SEC_NOR0_BASE; - VirtualMemoryTable[Index].Length =3D ARM_VE_SEC_NOR0_SZ; - VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; - // Secure RAM - VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_SEC_RAM0_BASE; - VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_SEC_RAM0_BASE; - VirtualMemoryTable[Index].Length =3D ARM_VE_SEC_RAM0_SZ; - VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; -#endif - - // SMB CS0 - NOR0 Flash - VirtualMemoryTable[Index].PhysicalBase =3D ARM_VE_SMB_NOR0_BASE; - VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_SMB_NOR0_BASE; - VirtualMemoryTable[Index].Length =3D SIZE_256KB * 255; - VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; - // Environment Variables region - VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_SMB_NOR0_BASE + (= SIZE_256KB * 255); - VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_SMB_NOR0_BASE + (= SIZE_256KB * 255); - VirtualMemoryTable[Index].Length =3D SIZE_64KB * 4; - VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; - - // SMB CS1 or CS4 - NOR1 Flash - VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_SMB_NOR1_BASE; - VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_SMB_NOR1_BASE; - VirtualMemoryTable[Index].Length =3D SIZE_256KB * 255; - VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; - // Environment Variables region - VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_SMB_NOR1_BASE + (= SIZE_256KB * 255); - VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_SMB_NOR1_BASE + (= SIZE_256KB * 255); - VirtualMemoryTable[Index].Length =3D SIZE_64KB * 4; - VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; - - // SMB CS3 or CS1 - PSRAM - VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_SMB_SRAM_BASE; - VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_SMB_SRAM_BASE; - VirtualMemoryTable[Index].Length =3D ARM_VE_SMB_SRAM_SZ; - VirtualMemoryTable[Index].Attributes =3D CacheAttributes; - - // Motherboard peripherals - VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_SMB_PERIPH_BASE; - VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_SMB_PERIPH_BASE; - VirtualMemoryTable[Index].Length =3D ARM_VE_SMB_PERIPH_SZ; - VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; - -#ifdef ARM_BIGLITTLE_TC2 - // Non-secure ROM - VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_TC2_NON_SECURE_RO= M_BASE; - VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_TC2_NON_SECURE_RO= M_BASE; - VirtualMemoryTable[Index].Length =3D ARM_VE_TC2_NON_SECURE_RO= M_SZ; - VirtualMemoryTable[Index].Attributes =3D CacheAttributes; -#endif - - // OnChip peripherals - VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_ONCHIP_PERIPH_BAS= E; - VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_ONCHIP_PERIPH_BAS= E; - VirtualMemoryTable[Index].Length =3D ARM_VE_ONCHIP_PERIPH_SZ; - VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; - - // SCC Region - VirtualMemoryTable[++Index].PhysicalBase =3D ARM_CTA15A7_SCC_BASE; - VirtualMemoryTable[Index].VirtualBase =3D ARM_CTA15A7_SCC_BASE; - VirtualMemoryTable[Index].Length =3D SIZE_64KB; - VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; - -#ifdef ARM_BIGLITTLE_TC2 - // TC2 OnChip non-secure SRAM - VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_TC2_NON_SECURE_SR= AM_BASE; - VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_TC2_NON_SECURE_SR= AM_BASE; - VirtualMemoryTable[Index].Length =3D ARM_VE_TC2_NON_SECURE_SR= AM_SZ; - VirtualMemoryTable[Index].Attributes =3D CacheAttributes; -#endif - -#ifndef ARM_BIGLITTLE_TC2 - // Workaround for SRAM bug in RTSM - if (PcdGet64 (PcdSystemMemoryBase) !=3D 0x80000000) { - VirtualMemoryTable[++Index].PhysicalBase =3D 0x80000000; - VirtualMemoryTable[Index].VirtualBase =3D 0x80000000; - VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdSystemMem= oryBase) - 0x80000000; - VirtualMemoryTable[Index].Attributes =3D CacheAttributes; - } -#endif - - // DDR - VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdSystemMemor= yBase); - VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdSystemMemor= yBase); - VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdSystemMemor= ySize); - VirtualMemoryTable[Index].Attributes =3D CacheAttributes; - - // Detect if it is a 1GB or 2GB Test Chip - // [16:19]: 0=3D1GB TC2, 1=3D2GB TC2 - if (MmioRead32(ARM_VE_SYS_PROCID0_REG) & (0xF << 16)) { - DEBUG((EFI_D_ERROR,"Info: 2GB Test Chip 2 detected.\n")); - BuildResourceDescriptorHob ( - EFI_RESOURCE_SYSTEM_MEMORY, - EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALI= ZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | EFI_RESOURCE_ATTRIB= UTE_WRITE_THROUGH_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE= | - EFI_RESOURCE_ATTRIBUTE_TESTED, - PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize), - SIZE_1GB - ); - - // Map the additional 1GB into the MMU - VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdSystemMem= oryBase) + PcdGet64 (PcdSystemMemorySize); - VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdSystemMem= oryBase) + PcdGet64 (PcdSystemMemorySize); - VirtualMemoryTable[Index].Length =3D SIZE_1GB; - VirtualMemoryTable[Index].Attributes =3D CacheAttributes; - } - - // End of Table - VirtualMemoryTable[++Index].PhysicalBase =3D 0; - VirtualMemoryTable[Index].VirtualBase =3D 0; - VirtualMemoryTable[Index].Length =3D 0; - VirtualMemoryTable[Index].Attributes =3D (ARM_MEMORY_REGION_ATTRI= BUTES)0; - - ASSERT((Index + 1) <=3D MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); - - *VirtualMemoryMap =3D VirtualMemoryTable; -} --=20 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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