From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 209FCD8003E for ; Tue, 20 Feb 2024 03:37:00 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=/z0ni7M2NBqZNnGiR2+WIqeGLR50oHc9sDl3tAae3iY=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1708400219; v=1; b=WQ/p9LtILcRVsjFSufJbmurLe6qxbBxvhFDFmzQCS/LUHG18CW7mHHf7LvcYQZfNghXy+FGJ zvjA+1eMR16A6qZeUXTuwLD11DCuVMD/rZ0UuDsvrtuiHH7tS4JoTey/osJC9wMGbvnFOC2OIP6 a7xd8ExjDdrrtBa006w2NSyI= X-Received: by 127.0.0.2 with SMTP id OZ2VYY7687511xToYSOobHQ1; Mon, 19 Feb 2024 19:36:59 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by mx.groups.io with SMTP id smtpd.web11.5738.1708400218672382844 for ; Mon, 19 Feb 2024 19:36:58 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10989"; a="2632963" X-IronPort-AV: E=Sophos;i="6.06,171,1705392000"; d="scan'208";a="2632963" X-Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2024 19:36:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,171,1705392000"; d="scan'208";a="4622225" X-Received: from shwdesssddpdwei.ccr.corp.intel.com ([10.239.157.28]) by fmviesa009.fm.intel.com with ESMTP; 19 Feb 2024 19:36:56 -0800 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Ray Ni , Rangasai V Chaganty , Jenny Huang Subject: [edk2-devel] [PATCH] IntelSiliconPkg/VTd: Reset the one-shot bits before modifing GCMD_REG Date: Tue, 20 Feb 2024 11:36:51 +0800 Message-Id: <20240220033651.1437-1-w.sheng@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,w.sheng@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: nOgJczINNgBhbqIufsTyC4uMx7686176AA= Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b="WQ/p9LtI"; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none) Here is the process of modify GCMD_REG. Read GSTS_REG Reset the one-shot bits. Modify the target comamnd value. Write the command value to GCMD_REG. Wait until GSTS_REG indicates command is serviced. Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Jenny Huang Signed-off-by: Sheng Wei --- .../Feature/VTd/IntelVTdCoreDxe/VtdReg.c | 13 ++---- .../VTd/IntelVTdCorePei/IntelVTdDmar.c | 9 +--- .../VTd/IntelVTdDmarPei/IntelVTdDmar.c | 43 +++++++++--------- .../Feature/VTd/IntelVTdDxe/VtdReg.c | 44 +++++++++---------- .../Feature/VTd/IntelVTdPmrPei/VtdReg.c | 1 + .../IntelVTdPeiDxeLib/IntelVTdPeiDxeLib.c | 12 ++--- 6 files changed, 51 insertions(+), 71 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdCoreDxe/VtdR= eg.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdCoreDxe/VtdReg.c index edeb4b3ff..21e2d5f1b 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdCoreDxe/VtdReg.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdCoreDxe/VtdReg.c @@ -112,13 +112,8 @@ PerpareCacheInvalidationInterface ( // Enable the queued invalidation interface through the Global Command R= egister.=0D // When enabled, hardware sets the QIES field in the Global Status Regis= ter.=0D //=0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - Reg32 |=3D B_GMCD_REG_QIE;=0D - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32);=0D - DEBUG ((DEBUG_INFO, "Enable Queued Invalidation Interface. GCMD_REG =3D = 0x%x\n", Reg32));=0D - do {=0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - } while ((Reg32 & B_GSTS_REG_QIES) =3D=3D 0);=0D + DEBUG ((DEBUG_INFO, "Enable Queued Invalidation Interface.\n"));=0D + VtdLibSetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_QIE);= =0D =0D VTdLogAddEvent (VTDLOG_DXE_QUEUED_INVALIDATION, VTD_LOG_QI_ENABLE, VtdUn= itBaseAddress);=0D =0D @@ -577,7 +572,7 @@ DumpVtdCapRegs ( IN VTD_CAP_REG *CapReg=0D )=0D {=0D - DEBUG((DEBUG_INFO, " CapReg - 0x%x\n", CapReg->Uint64));=0D + DEBUG((DEBUG_INFO, " CapReg - 0x%lx\n", CapReg->Uint64));=0D DEBUG((DEBUG_INFO, " ND - 0x%x\n", CapReg->Bits.ND));=0D DEBUG((DEBUG_INFO, " AFL - 0x%x\n", CapReg->Bits.AFL));=0D DEBUG((DEBUG_INFO, " RWBF - 0x%x\n", CapReg->Bits.RWBF));=0D @@ -737,7 +732,7 @@ DumpVtdIfError ( if (HasError) {=0D REPORT_STATUS_CODE (EFI_ERROR_CODE, PcdGet32 (PcdErrorCodeVTdError))= ;=0D DEBUG((DEBUG_INFO, "\n#### ERROR ####\n"));=0D - DumpVtdRegs (mVtdUnitInformation[Num].VtdUnitBaseAddress); + DumpVtdRegs (mVtdUnitInformation[Num].VtdUnitBaseAddress);=0D DEBUG((DEBUG_INFO, "#### ERROR ####\n\n"));=0D //=0D // Clear=0D diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdCorePei/Inte= lVTdDmar.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdCorePei/Inte= lVTdDmar.c index 93207ba52..549313dbf 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdCorePei/IntelVTdDma= r.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdCorePei/IntelVTdDma= r.c @@ -120,13 +120,8 @@ PerpareCacheInvalidationInterface ( // Enable the queued invalidation interface through the Global Command R= egister.=0D // When enabled, hardware sets the QIES field in the Global Status Regis= ter.=0D //=0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - Reg32 |=3D B_GMCD_REG_QIE;=0D - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32);=0D - DEBUG ((DEBUG_INFO, "Enable Queued Invalidation Interface. GCMD_REG =3D = 0x%x\n", Reg32));=0D - do {=0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - } while ((Reg32 & B_GSTS_REG_QIES) =3D=3D 0);=0D + DEBUG ((DEBUG_INFO, "Enable Queued Invalidation Interface.\n"));=0D + VtdLibSetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_QIE);= =0D =0D VTdLogAddEvent (VTDLOG_PEI_QUEUED_INVALIDATION, VTD_LOG_QI_ENABLE, VtdUn= itBaseAddress);=0D =0D diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmar.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmar.c index e1b867973..533fb2b9a 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= r.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= r.c @@ -20,6 +20,18 @@ #include =0D #include "IntelVTdDmarPei.h"=0D =0D +VOID=0D +SetGlobalCommandRegisterBits (=0D + IN UINTN VtdUnitBaseAddress,=0D + IN UINT32 BitMask=0D + );=0D +=0D +VOID=0D +ClearGlobalCommandRegisterBits (=0D + IN UINTN VtdUnitBaseAddress,=0D + IN UINT32 BitMask=0D + );=0D +=0D /**=0D Flush VTD page table and context table memory.=0D =0D @@ -58,6 +70,7 @@ FlushWriteBuffer ( =0D if (CapReg.Bits.RWBF !=3D 0) {=0D Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D + Reg32 =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits=0D MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_WBF);= =0D do {=0D Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D @@ -104,11 +117,7 @@ PerpareCacheInvalidationInterface ( Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D if ((Reg32 & B_GSTS_REG_QIES) !=3D 0) {=0D DEBUG ((DEBUG_INFO,"Queued Invalidation Interface was enabled.\n"));=0D - Reg32 &=3D (~B_GSTS_REG_QIES);=0D - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32);=0D - do {=0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - } while ((Reg32 & B_GSTS_REG_QIES) !=3D 0);=0D + ClearGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_QIE);=0D MmioWrite64 (VtdUnitBaseAddress + R_IQA_REG, 0);=0D }=0D =0D @@ -144,13 +153,8 @@ PerpareCacheInvalidationInterface ( // Enable the queued invalidation interface through the Global Command R= egister.=0D // When enabled, hardware sets the QIES field in the Global Status Regis= ter.=0D //=0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - Reg32 |=3D B_GMCD_REG_QIE;=0D - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32);=0D - DEBUG ((DEBUG_INFO, "Enable Queued Invalidation Interface. GCMD_REG =3D = 0x%x\n", Reg32));=0D - do {=0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - } while ((Reg32 & B_GSTS_REG_QIES) =3D=3D 0);=0D + DEBUG ((DEBUG_INFO, "Enable Queued Invalidation Interface.\n"));=0D + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_QIE);=0D =0D return EFI_SUCCESS;=0D }=0D @@ -165,16 +169,9 @@ DisableQueuedInvalidationInterface ( IN VTD_UNIT_INFO *VTdUnitInfo=0D )=0D {=0D - UINT32 Reg32;=0D -=0D if (VTdUnitInfo->EnableQueuedInvalidation !=3D 0) {=0D - Reg32 =3D MmioRead32 (VTdUnitInfo->VtdUnitBaseAddress + R_GSTS_REG);=0D - Reg32 &=3D (~B_GMCD_REG_QIE);=0D - MmioWrite32 (VTdUnitInfo->VtdUnitBaseAddress + R_GCMD_REG, Reg32);=0D - DEBUG ((DEBUG_INFO, "Disable Queued Invalidation Interface. GCMD_REG = =3D 0x%x\n", Reg32));=0D - do {=0D - Reg32 =3D MmioRead32 (VTdUnitInfo->VtdUnitBaseAddress + R_GSTS_REG);= =0D - } while ((Reg32 & B_GSTS_REG_QIES) !=3D 0);=0D + DEBUG ((DEBUG_INFO, "Disable Queued Invalidation Interface.\n"));=0D + ClearGlobalCommandRegisterBits (VTdUnitInfo->VtdUnitBaseAddress, B_GMC= D_REG_QIE);=0D =0D if (VTdUnitInfo->QiDescBuffer !=3D NULL) {=0D FreePages(VTdUnitInfo->QiDescBuffer, EFI_SIZE_TO_PAGES (VTdUnitInfo-= >QiDescBufferSize));=0D @@ -206,7 +203,7 @@ QueuedInvalidationCheckFault ( if (FaultReg & (B_FSTS_REG_IQE | B_FSTS_REG_ITE | B_FSTS_REG_ICE)) {=0D IqercdReg.Uint64 =3D MmioRead64 (VTdUnitInfo->VtdUnitBaseAddress + R_I= QERCD_REG);=0D =0D - DEBUG((DEBUG_ERROR, "Detect Queue Invalidation Error [0x%08x] - IQERCD= [0x%016lx]\n", FaultReg, IqercdReg.Uint64));=0D + DEBUG((DEBUG_ERROR, "VTD 0x%x Detect Queue Invalidation Error [0x%08x]= - IQERCD [0x%016lx]\n", VTdUnitInfo->VtdUnitBaseAddress, FaultReg, IqercdR= eg.Uint64));=0D =0D MmioWrite32 (VTdUnitInfo->VtdUnitBaseAddress + R_FSTS_REG, FaultReg);= =0D return RETURN_DEVICE_ERROR;=0D @@ -763,7 +760,7 @@ EnableVTdTranslationProtection ( =0D if (VtdUnitInfo->ExtRootEntryTable !=3D 0) {=0D DEBUG ((DEBUG_INFO, "EnableVtdDmar (%d) ExtRootEntryTable 0x%x\n", I= ndex, VtdUnitInfo->ExtRootEntryTable));=0D - Status =3D EnableDmar (VtdUnitInfo, VtdUnitInfo->ExtRootEntryTable |= BIT11); + Status =3D EnableDmar (VtdUnitInfo, VtdUnitInfo->ExtRootEntryTable |= BIT11);=0D } else {=0D DEBUG ((DEBUG_INFO, "EnableVtdDmar (%d) RootEntryTable 0x%x\n", Inde= x, VtdUnitInfo->RootEntryTable));=0D Status =3D EnableDmar (VtdUnitInfo, VtdUnitInfo->RootEntryTable);=0D diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c= b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c index 30dab4a64..2c48eefe9 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c @@ -12,6 +12,18 @@ VTD_UNIT_INFORMATION *mVtdUnitInformation; =0D BOOLEAN mVtdEnabled;=0D =0D +VOID=0D +SetGlobalCommandRegisterBits (=0D + IN UINTN VtdUnitBaseAddress,=0D + IN UINT32 BitMask=0D + );=0D +=0D +VOID=0D +ClearGlobalCommandRegisterBits (=0D + IN UINTN VtdUnitBaseAddress,=0D + IN UINT32 BitMask=0D + );=0D +=0D /**=0D Flush VTD page table and context table memory.=0D =0D @@ -47,6 +59,7 @@ FlushWriteBuffer ( =0D if (mVtdUnitInformation[VtdIndex].CapReg.Bits.RWBF !=3D 0) {=0D Reg32 =3D MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress= + R_GSTS_REG);=0D + Reg32 =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits=0D MmioWrite32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GCMD= _REG, Reg32 | B_GMCD_REG_WBF);=0D do {=0D Reg32 =3D MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddre= ss + R_GSTS_REG);=0D @@ -93,11 +106,7 @@ PerpareCacheInvalidationInterface ( Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D if ((Reg32 & B_GSTS_REG_QIES) !=3D 0) {=0D DEBUG ((DEBUG_ERROR,"Queued Invalidation Interface was enabled.\n"));= =0D - Reg32 &=3D (~B_GSTS_REG_QIES);=0D - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32);=0D - do {=0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - } while ((Reg32 & B_GSTS_REG_QIES) !=3D 0);=0D + ClearGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_QIE);=0D }=0D =0D //=0D @@ -132,13 +141,8 @@ PerpareCacheInvalidationInterface ( // Enable the queued invalidation interface through the Global Command R= egister.=0D // When enabled, hardware sets the QIES field in the Global Status Regis= ter.=0D //=0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - Reg32 |=3D B_GMCD_REG_QIE;=0D - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32);=0D - DEBUG ((DEBUG_INFO, "Enable Queued Invalidation Interface. GCMD_REG =3D = 0x%x\n", Reg32));=0D - do {=0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - } while ((Reg32 & B_GSTS_REG_QIES) =3D=3D 0);=0D + DEBUG ((DEBUG_INFO, "Enable Queued Invalidation Interface.\n"));=0D + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_QIE);=0D =0D return EFI_SUCCESS;=0D }=0D @@ -153,19 +157,13 @@ DisableQueuedInvalidationInterface ( IN UINTN VtdIndex=0D )=0D {=0D - UINT32 Reg32;=0D VTD_UNIT_INFORMATION *VTdUnitInfo;=0D =0D VTdUnitInfo =3D &mVtdUnitInformation[VtdIndex];=0D =0D if (VTdUnitInfo->EnableQueuedInvalidation !=3D 0) {=0D - Reg32 =3D MmioRead32 (VTdUnitInfo->VtdUnitBaseAddress + R_GSTS_REG);=0D - Reg32 &=3D (~B_GMCD_REG_QIE);=0D - MmioWrite32 (VTdUnitInfo->VtdUnitBaseAddress + R_GCMD_REG, Reg32);=0D - DEBUG ((DEBUG_INFO, "Disable Queued Invalidation Interface. GCMD_REG = =3D 0x%x\n", Reg32));=0D - do {=0D - Reg32 =3D MmioRead32 (VTdUnitInfo->VtdUnitBaseAddress + R_GSTS_REG);= =0D - } while ((Reg32 & B_GSTS_REG_QIES) !=3D 0);=0D + DEBUG ((DEBUG_INFO, "Disable Queued Invalidation Interface.\n"));=0D + ClearGlobalCommandRegisterBits (VTdUnitInfo->VtdUnitBaseAddress, B_GMC= D_REG_QIE);=0D =0D if (VTdUnitInfo->QiDescBuffer !=3D NULL) {=0D FreePages(VTdUnitInfo->QiDescBuffer, EFI_SIZE_TO_PAGES (VTdUnitInfo-= >QiDescBufferSize));=0D @@ -198,7 +196,7 @@ QueuedInvalidationCheckFault ( if (FaultReg & (B_FSTS_REG_IQE | B_FSTS_REG_ITE | B_FSTS_REG_ICE)) {=0D IqercdReg.Uint64 =3D MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnit= BaseAddress + R_IQERCD_REG);=0D =0D - DEBUG((DEBUG_ERROR, "Detect Queue Invalidation Error [0x%08x] - IQERCD= [0x%016lx]\n", FaultReg, IqercdReg.Uint64));=0D + DEBUG((DEBUG_ERROR, "VTD 0x%x Detect Queue Invalidation Error [0x%08x]= - IQERCD [0x%016lx]\n", mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress, = FaultReg, IqercdReg.Uint64));=0D =0D MmioWrite32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FSTS= _REG, FaultReg);=0D return RETURN_DEVICE_ERROR;=0D @@ -802,7 +800,7 @@ DumpVtdCapRegs ( IN VTD_CAP_REG *CapReg=0D )=0D {=0D - DEBUG((DEBUG_INFO, " CapReg - 0x%x\n", CapReg->Uint64));=0D + DEBUG((DEBUG_INFO, " CapReg - 0x%016lx\n", CapReg->Uint64));=0D DEBUG((DEBUG_INFO, " ND - 0x%x\n", CapReg->Bits.ND));=0D DEBUG((DEBUG_INFO, " AFL - 0x%x\n", CapReg->Bits.AFL));=0D DEBUG((DEBUG_INFO, " RWBF - 0x%x\n", CapReg->Bits.RWBF));=0D @@ -833,7 +831,7 @@ DumpVtdECapRegs ( IN VTD_ECAP_REG *ECapReg=0D )=0D {=0D - DEBUG((DEBUG_INFO, " ECapReg - 0x%x\n", ECapReg->Uint64));=0D + DEBUG((DEBUG_INFO, " ECapReg - 0x%016lx\n", ECapReg->Uint64));=0D DEBUG((DEBUG_INFO, " C - 0x%x\n", ECapReg->Bits.C));=0D DEBUG((DEBUG_INFO, " QI - 0x%x\n", ECapReg->Bits.QI));=0D DEBUG((DEBUG_INFO, " DT - 0x%x\n", ECapReg->Bits.DT));=0D diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdRe= g.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c index 2e252fe5b..03b39d183 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c @@ -54,6 +54,7 @@ FlushWriteBuffer ( =0D if (CapReg.Bits.RWBF !=3D 0) {=0D Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D + Reg32 =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits=0D MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_WBF);= =0D do {=0D Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D diff --git a/Silicon/Intel/IntelSiliconPkg/Library/IntelVTdPeiDxeLib/IntelV= TdPeiDxeLib.c b/Silicon/Intel/IntelSiliconPkg/Library/IntelVTdPeiDxeLib/Int= elVTdPeiDxeLib.c index 3e22c3d92..135e740d6 100644 --- a/Silicon/Intel/IntelSiliconPkg/Library/IntelVTdPeiDxeLib/IntelVTdPeiDx= eLib.c +++ b/Silicon/Intel/IntelSiliconPkg/Library/IntelVTdPeiDxeLib/IntelVTdPeiDx= eLib.c @@ -1497,6 +1497,7 @@ VtdLibFlushWriteBuffer ( =0D if (CapReg.Bits.RWBF !=3D 0) {=0D Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D + Reg32 =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits=0D MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_WBF);= =0D do {=0D Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D @@ -1664,7 +1665,6 @@ VtdLibDisableQueuedInvalidationInterface ( IN UINTN VtdUnitBaseAddress=0D )=0D {=0D - UINT32 Reg32;=0D QI_256_DESC QiDesc;=0D =0D QiDesc.Uint64[0] =3D QI_IWD_TYPE;=0D @@ -1674,14 +1674,8 @@ VtdLibDisableQueuedInvalidationInterface ( =0D VtdLibSubmitQueuedInvalidationDescriptor (VtdUnitBaseAddress, &QiDesc, T= RUE);=0D =0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - Reg32 &=3D (~B_GMCD_REG_QIE);=0D - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32);=0D -=0D - DEBUG ((DEBUG_INFO, "Disable Queued Invalidation Interface. [%x] GCMD_RE= G =3D 0x%x\n", VtdUnitBaseAddress, Reg32));=0D - do {=0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - } while ((Reg32 & B_GSTS_REG_QIES) !=3D 0);=0D + DEBUG ((DEBUG_INFO, "Disable Queued Invalidation Interface. [%x]\n", Vtd= UnitBaseAddress));=0D + VtdLibClearGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_QIE= );=0D =0D MmioWrite64 (VtdUnitBaseAddress + R_IQA_REG, 0);=0D }=0D --=20 2.26.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#115617): https://edk2.groups.io/g/devel/message/115617 Mute This Topic: https://groups.io/mt/104461797/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-