From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 26800D8030B for ; Tue, 20 Feb 2024 07:48:09 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=RkJWZEn9Iqb/qzzHNR/z5zrhfS4ObB31MMd8kI3Cy54=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1708415288; v=1; b=QHrDyZbd3DXVkoHWkwKWCAXXML6s8wfhtGqGTlKuj1rNzicyNmkmdelJ/2+QPGKbHpp6Oml1 iif6wKauvyGfXMyV6DVaeq3MbIBNJqEa+5FiZXn0zIO+z70eP3ngJ0Y8hfV0Anmbbnednj8U/5f rFh2q62X/S3E53nvseIatGfY= X-Received: by 127.0.0.2 with SMTP id hiCdYY7687511xxxa7O53kuC; Mon, 19 Feb 2024 23:48:08 -0800 X-Received: from sgoci-sdnproxy-4.icoremail.net (sgoci-sdnproxy-4.icoremail.net [129.150.39.64]) by mx.groups.io with SMTP id smtpd.web10.8651.1708415287146195633 for ; Mon, 19 Feb 2024 23:48:08 -0800 X-Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-6 (Coremail) with SMTP id AQAAfwAXHwsxWdRl7uWPBQ--.58176S2; Tue, 20 Feb 2024 15:48:01 +0800 (CST) X-Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAfwDneYUtWdRl2j8AAA--.298S4; Tue, 20 Feb 2024 15:47:58 +0800 (CST) From: "Xiong Yining" To: devel@edk2.groups.io Cc: quic_llindhol@quicinc.com, ardb+tianocore@kernel.org, graeme@xora.org.uk, marcin.juszkiewicz@linaro.org, chenbaozi@phytium.com.cn, Xiong Yining Subject: [edk2-devel] [PATCH v2 1/1] SbsaQemu: AcpiDxe: Create SRAT table at runtime Date: Tue, 20 Feb 2024 07:47:36 +0000 Message-Id: <20240220074736.3249691-2-xiongyining1480@phytium.com.cn> In-Reply-To: <20240220074736.3249691-1-xiongyining1480@phytium.com.cn> References: <20240220074736.3249691-1-xiongyining1480@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAfwDneYUtWdRl2j8AAA--.298S4 X-CM-SenderInfo: x0lr0wp1lqx0bjrumio6sk53xlxphulrpou0/1tbiAQABBmXTrXETWwABsl X-Coremail-Antispam: 1Uk129KBjvJXoWxtr1xuryruw13GrWUGw43Awb_yoW3Wr1fpF n2vFZYkr18Jry2kr4fGa1rur1rWFy3GayUGFZxXr1UtF47AFykZw45Jr97X3WDJwsF939x uF4kXay7uFn5GFJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj DUYxn0WfASr-VFAU7a7-sFnT9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUU UUUUU Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,xiongyining1480@phytium.com.cn List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: MoRaR4JtcIb5fAnfipx68xjSx7686176AA= Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=QHrDyZbd; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=none Add support to create SRAT(System resource affinity table) for sbsa platform at runtime. Signed-off-by: Xiong Yining Signed-off-by: Chen Baozi Reviewed-by: Marcin Juszkiewicz --- .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 27 ++++++ .../Include/Library/SbsaQemuHardwareInfoLib.h | 11 +++ .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 92 +++++++++++++++++++ .../SbsaQemuHardwareInfoLib.c | 36 ++++++++ 4 files changed, 166 insertions(+) diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h index 7595df4c8a2d..83a085cd86f4 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h @@ -63,4 +63,31 @@ typedef struct { #define GTDT_WDTIMER_FLAGS (GTDT_WDTIMER_ACTIVE_HIGH | GTDT_WDTIMER_LEVEL_TRIGGERED) +#define SBSAQEMU_ACPI_MEMORY_AFFINITY_STRUCTURE_INIT( \ + ProximityDomain, Base, Length, Flags) \ + { \ + 1, /* Type */ \ + sizeof (EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE), /* Length */ \ + ProximityDomain, /* Proximity Domain */ \ + 0, /* Reserved */ \ + (Base) & 0xffffffff, /* Base Address Low */ \ + ((Base) >> 32) & 0xffffffff , /* Base Address High */ \ + (Length) & 0xffffffff, /* Length Low */ \ + ((Length) >> 32) & 0xffffffff, /* Length High */ \ + 0, /* Reserved */ \ + Flags, /* Flags */ \ + 0 /* Reserved */ \ + } + +#define SBSAQEMU_ACPI_GICC_AFFINITY_STRUCTURE_INIT( \ + ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) \ + { \ + 3, /* Type */ \ + sizeof (EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE), /* Length */ \ + ProximityDomain, /* Proximity Domain */ \ + ACPIProcessorUID, /* ACPI Processor UID */ \ + Flags, /* Flags */ \ + ClockDomain /* Clock Domain */ \ + } + #endif diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuHardwareInfoLib.h b/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuHardwareInfoLib.h index 0b71a3f7e6eb..831efe2e8d1d 100644 --- a/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuHardwareInfoLib.h +++ b/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuHardwareInfoLib.h @@ -70,4 +70,15 @@ SbsaQemuGetMemInfo ( IN UINTN MemoryId ); +/** + Get the number of numa node from device tree passed by Qemu. + + @retval the number of numa node. +**/ +UINT64 +SbsaQemuGetNumaNodeCount ( + VOID + ); + + #endif /* SBSA_QEMU_HARDWARE_INFO_ */ diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index 03f7a34977a0..2685d4b00426 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -682,6 +682,91 @@ AddGtdtTable ( return Status; } +/* + * A function that adds the SRAT ACPI table. + */ +EFI_STATUS +AddSratTable ( + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable + ) +{ + EFI_STATUS Status; + UINT8 *New; + EFI_PHYSICAL_ADDRESS PageAddress; + UINTN TableHandle; + UINT32 TableSize; + UINT32 Index; + UINT32 NodeId; + UINT32 NumMemNodes; + MemoryInfo MemInfo; + UINT32 NumCores = PcdGet32 (PcdCoreCount); + + // Initialize SRAT ACPI Header + EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header = { + SBSAQEMU_ACPI_HEADER (EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE, + EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER, + EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION), + 1, 0 }; + + NumMemNodes = SbsaQemuGetMemNodeCount(); + + // Calculate the new table size based on the number of cores + TableSize = sizeof (EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER) + + (sizeof (EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE) * NumMemNodes ) + + (sizeof (EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE) * NumCores); + + Status = gBS->AllocatePages ( + AllocateAnyPages, + EfiACPIReclaimMemory, + EFI_SIZE_TO_PAGES (TableSize), + &PageAddress + ); + + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "Failed to allocate pages for SRAT table\n")); + return EFI_OUT_OF_RESOURCES; + } + + New = (UINT8 *)(UINTN) PageAddress; + ZeroMem (New, TableSize); + + // Add the ACPI Description table header + CopyMem (New, &Header, sizeof (EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER)); + ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize; + New += sizeof (EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER); + + // Add memory structures + for (Index = 0; Index < NumMemNodes ; Index++) { + MemInfo = SbsaQemuGetMemInfo (Index); + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE memory = SBSAQEMU_ACPI_MEMORY_AFFINITY_STRUCTURE_INIT (MemInfo.NodeId, MemInfo.AddressBase, MemInfo.AddressSize, 1); + CopyMem (New, &memory, sizeof (EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE)); + New += sizeof (EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE); + } + + // Add processor structures for the cores + for (Index = 0; Index < NumCores; Index++) { + NodeId = SbsaQemuGetCpuNumaNode(Index); + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE gicc = SBSAQEMU_ACPI_GICC_AFFINITY_STRUCTURE_INIT(NodeId, Index, 1, 0); + CopyMem (New, &gicc, sizeof (EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE)); + New += sizeof (EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE); + } + + // Perform Checksum + AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize); + + Status = AcpiTable->InstallAcpiTable ( + AcpiTable, + (EFI_ACPI_COMMON_HEADER *)PageAddress, + TableSize, + &TableHandle + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "Failed to install SRAT table\n")); + } + + return Status; +} + /* * A function to disable XHCI node on Platform Version lower than 0.3 */ @@ -793,6 +878,13 @@ InitializeSbsaQemuAcpiDxe ( DEBUG ((DEBUG_ERROR, "Failed to add PPTT table\n")); } + if (SbsaQemuGetNumaNodeCount() > 0){ + Status = AddSratTable (AcpiTable); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to add SRAT table\n")); + } + } + Status = AddGtdtTable (AcpiTable); if (EFI_ERROR (Status)) { DEBUG ((DEBUG_ERROR, "Failed to add GTDT table\n")); diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c index 03e33c544ee0..04a8a076ab64 100644 --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c @@ -352,3 +352,39 @@ SbsaQemuGetMemInfo ( return MemInfo; } + +UINT64 +SbsaQemuGetNumaNodeCount ( + VOID +) +{ + UINT64 Arg; + UINT32 Index; + UINT32 NumNumaCount; + UINT32 NumMemCount; + UINT32 NumCores = PcdGet32 (PcdCoreCount); + MemoryInfo MemInfo; + + NumNumaCount = 0; + NumMemCount = SbsaQemuGetMemNodeCount(); + + if (NumCores > 0){ + for (Index = 0; Index < NumCores; Index ++){ + Arg = SbsaQemuGetCpuNumaNode(Index); + if (NumNumaCount == 0 || NumNumaCount < (Arg + 1)){ + NumNumaCount = Arg + 1; + } + } + } + + if (NumMemCount > 0){ + for (Index = 0; Index < NumMemCount; Index ++){ + MemInfo = SbsaQemuGetMemInfo(Index); + if (NumNumaCount == 0 || NumNumaCount < (MemInfo.NodeId + 1)){ + NumNumaCount = MemInfo.NodeId + 1; + } + } + } + + return NumNumaCount; +} -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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