[edk2-devel] [PATCH 2/3] RiscVPlatformPkg: introduce more Pcds for PCI initialization

["Chai, Evan" <evan.chai@intel.com>]

It is assumed that the current system only supports a single RC
model.

Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Yong Li <yong.li@intel.com>
Signed-off-by: Evan Chai <evan.chai@intel.com>
---
 Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
index b45f48fd..8eeafb2b 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
@@ -1,6 +1,7 @@
 ## @file  RiscVPlatformPkg.dec
 # This Package provides UEFI RISC-V platform modules and libraries.
 #
+# Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
 # Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -89,6 +90,21 @@
 [PcdsFeatureFlag]
 
 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
+  #
+  # RC initialization
+  #
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00001200
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00001201
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00001202
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00001203
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00001204
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00001205
+
+  #
+  # Inclusive range of allowed PCI buses.
+  #
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00001206
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x00001207
 
 [UserExtensions.TianoCore."ExtraFiles"]
   RiscVPlatformPkgExtra.uni
-- 
2.34.1



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