From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 3AD987803DB for ; Thu, 29 Feb 2024 15:30:01 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=8j3Va7h5EQxggtaC2MgX+/u8vBkzJyMZwbwTmHn/Kto=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20140610; t=1709220599; v=1; b=Jd89C+pomz+n7qixFM0DOXgI4tsPjp6am1oxQHieHOQFGrX1PnGclrMkiSAWmPO7H1ZhrKI5 dA2jEYAv1VvXK0ataLt6ztimvvZrMKv/U67V9+OdFeHgNu2EpQ7etMy5nFb+F8Zd5a7uN3MPoaw i8grphi5TMezTLsEp8D1UptU= X-Received: by 127.0.0.2 with SMTP id j3D9YY7687511xLN9Mh0lISR; Thu, 29 Feb 2024 07:29:59 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) by mx.groups.io with SMTP id smtpd.web10.28012.1709220598133199782 for ; Thu, 29 Feb 2024 07:29:58 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10999"; a="3540039" X-IronPort-AV: E=Sophos;i="6.06,194,1705392000"; d="scan'208";a="3540039" X-Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Feb 2024 07:29:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,194,1705392000"; d="scan'208";a="12544581" X-Received: from evancy.sh.intel.com ([10.239.159.137]) by orviesa003.jf.intel.com with ESMTP; 29 Feb 2024 07:29:54 -0800 From: "Chai, Evan" To: devel@edk2.groups.io Cc: Andrei Warkentin , Sunil V L , Yong Li Subject: [edk2-devel] [PATCH 3/3] RiscVQemuServerPlatform: create qemu-based server reference board Date: Thu, 29 Feb 2024 23:24:52 +0800 Message-Id: <20240229152452.1096498-4-evan.chai@intel.com> In-Reply-To: <20240229152452.1096498-1-evan.chai@intel.com> References: <20240229152452.1096498-1-evan.chai@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,evan.chai@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 6jXFZ4moyQ3uYHAKByGpF1EJx7686176AA= Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=Jd89C+po; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io 1.Reimplemented SecMain to create a Hob for the entire Variable region, preventing unauthorized access to this area. As a result, VirtNorFlashDxe has been reimplemented without the need for GCD mapping of Variable. The change addresses the dependency issue between VirtNorFlashDxe and VariableRuntimeDxe. 2.Define PcdPciExpressBaseAddress =3D 0x30000000 by the default dtb created by Qemu 'ssoc_ref'(server soc reference model), then PciExpressLib can be replaced by the MdePkg version. 3.Reconstructed PciHostBridgeLib based on generic ECAM topology, removing dependencies on Fdtlib and adopting PCD more extensively for configuration parameters. The current PCI configuration information for ECAM still relies on the device tree established by Qemu. 4.Reimplemented VirtNorFlashPlatformLib with static value. Cc: Andrei Warkentin Cc: Sunil V L Cc: Yong Li Signed-off-by: Evan Chai --- Platform/Qemu/RiscVQemuServerPlatform/Documents/Media/Hand-Off-Block-Hob-L= ist.jpg | Bin 0 -> 16901 bytes Platform/Qemu/RiscVQemuServerPlatform/Documents/Media/PI_Boot_Phases.jpg = | Bin 0 -> 196120 bytes Platform/Qemu/RiscVQemuServerPlatform/Documents/Media/RISC-V_Platform_EDK2= _Firmware_Enabling_Philosophy.jpg | Bin 0 -> 329871 bytes Platform/Qemu/RiscVQemuServerPlatform/Documents/Media/V2_DXE_Foundation-3.= jpg | Bin 0 -> 51521 bytes Platform/Qemu/RiscVQemuServerPlatform/Library/PciHostBridgeLibEcam/PciHost= BridgeLibEcam.c | 386 +++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++ Platform/Qemu/RiscVQemuServerPlatform/Library/PciHostBridgeLibEcam/PciHost= BridgeLibEcam.inf | 49 +++++++++++++++++++++++++++++++++++= +++++++++++++ Platform/Qemu/RiscVQemuServerPlatform/Library/VirtNorFlashPlatformLib/Virt= NorFlashStaticLib.c | 42 +++++++++++++++++++++++++++++++++++= +++++++ Platform/Qemu/RiscVQemuServerPlatform/Library/VirtNorFlashPlatformLib/Virt= NorFlashStaticLib.inf | 32 ++++++++++++++++++++++++++++++++ Platform/Qemu/RiscVQemuServerPlatform/Readme.md = | 327 +++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.dsc = | 703 +++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.fdf = | 284 +++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++ Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.fdf.inc = | 42 +++++++++++++++++++++++++++++++++++= +++++++ Platform/Qemu/RiscVQemuServerPlatform/Sec/Cpu.c = | 33 +++++++++++++++++++++++++++++++++ Platform/Qemu/RiscVQemuServerPlatform/Sec/Memory.c = | 318 +++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Qemu/RiscVQemuServerPlatform/Sec/Platform.c = | 160 +++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++ Platform/Qemu/RiscVQemuServerPlatform/Sec/SecEntry.S = | 19 +++++++++++++++++++ Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.c = | 110 +++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.h = | 104 +++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.inf = | 67 +++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++ Platform/Qemu/RiscVQemuServerPlatform/VarStore.fdf.inc = | 72 +++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++ Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlash.c = | 742 +++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++ Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlash.h = | 345 +++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++ Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashDxe.c = | 447 +++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++ Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashDxe.inf = | 69 +++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++ Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashFvb.c = | 904 +++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= 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BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#pragma pack(1) +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} MY_PCI_ROOT_BRIDGE_DEVICE_PATH; +#pragma pack () + +MY_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate =3D { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) + } + }, + EISA_PNP_ID (0x0A08), // PCI Express + 0 + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] =3D { + L"Mem", L"I/O", L"Bus" +}; + +// +// They depend on the 'reg' property of the default DT provided by qemu +// +#define GENERIC_ECAM_CONFIGURATION_BASE 0x30000000 +#define GENERIC_ECAM_CONFIGURATION_SIZE 0x10000000 + +/** + Apply EFI_MEMORY_UC attributees to the range [Base, Base + Size). + + @param Base Range base. + @param Size Range size. + + @return EFI_STATUS EFI_SUCCESS or others. +**/ +STATIC +EFI_STATUS +EFIAPI +MapGcdMmioSpace ( + IN UINT64 Base, + IN UINT64 Size + ) +{ + EFI_STATUS Status; + + Status =3D gDS->AddMemorySpace ( + EfiGcdMemoryTypeMemoryMappedIo, + Base, + Size, + EFI_MEMORY_UC + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: failed to add GCD memory space for region [0x%Lx+0x%Lx)\n", + __func__, + Base, + Size + )); + return Status; + } + + Status =3D gDS->SetMemorySpaceAttributes (Base, Size, EFI_MEMORY_UC); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: failed to set memory space attributes for region [0x%Lx+0x%Lx)\= n", + __func__, + Base, + Size + )); + } + + return Status; +} + +/** + Process a PCI_ROOT_BRIDGE by the default Device Tree. + + @param DtIo For a pci-host-ecam-generic node. + @param Bridge PCI_ROOT_BRIDGE to fill. + + @return EFI_STATUS EFI_SUCCESS or others. +**/ +STATIC +EFI_STATUS +EFIAPI +ProcessPciHost ( + IN PCI_ROOT_BRIDGE *Bridge + ) +{ + UINT64 ConfigBase; + UINT64 ConfigSize; + EFI_STATUS Status; + UINT32 BusMin; + UINT32 BusMax; + PCI_ROOT_BRIDGE_APERTURE Io; + PCI_ROOT_BRIDGE_APERTURE Mem; + PCI_ROOT_BRIDGE_APERTURE MemAbove4G; + PCI_ROOT_BRIDGE_APERTURE PMem; + PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; + UINT64 Attributes; + UINT64 AllocationAttributes; + + ZeroMem (&Io, sizeof (Io)); + ZeroMem (&Mem, sizeof (Mem)); + ZeroMem (&MemAbove4G, sizeof (MemAbove4G)); + ZeroMem (&PMem, sizeof (PMem)); + ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G)); + + PMem.Base =3D 1; + PMemAbove4G.Base =3D MAX_UINT64; + + BusMin =3D PcdGet32 (PcdPciBusMin); + BusMax =3D PcdGet32 (PcdPciBusMax); + + // + // IO, MMIO32, MMIO64 + // + Io.Base =3D PcdGet64 (PcdPciIoBase); + Io.Limit =3D PcdGet64 (PcdPciIoBase) + PcdGet64 (PcdPciIoSize) - 1; + + Mem.Base =3D PcdGet32 (PcdPciMmio32Base); + Mem.Limit =3D PcdGet32 (PcdPciMmio32Base) + + PcdGet32 (PcdPciMmio32Size) - 1; + + MemAbove4G.Base =3D PcdGet64 (PcdPciMmio64Base); + MemAbove4G.Limit =3D PcdGet64 (PcdPciMmio64Base) + + PcdGet64 (PcdPciMmio64Size) - 1; + + // + // Fetch the ECAM window + // + ConfigBase =3D GENERIC_ECAM_CONFIGURATION_BASE; + ConfigSize =3D GENERIC_ECAM_CONFIGURATION_SIZE; + + DEBUG (( + DEBUG_INFO, + "%a: Config[0x%Lx+0x%Lx)\n", + __func__, + ConfigBase, + ConfigSize + )); + + // + // Map the ECAM space in the GCD memory map + // + Status =3D MapGcdMmioSpace (ConfigBase, ConfigSize); + if ((Status !=3D EFI_SUCCESS) && (Status !=3D EFI_UNSUPPORTED)) { + DEBUG (( + DEBUG_ERROR, + "%a: MapGcdMmioSpace[0x%Lx-0x%Lx]: %r\n", + ConfigBase, + ConfigSize, + Status + )); + } + + if (Io.Base <=3D Io.Limit) { + // + // Map the MMIO window that provides I/O access - the PCI host bridge = code + // is not aware of this translation and so it will only map the I/O vi= ew + // in the GCD I/O map. + // + Status =3D MapGcdMmioSpace (Io.Base - Io.Translation, Io.Limit - Io.Ba= se + 1); + if ((Status !=3D EFI_SUCCESS) && (Status !=3D EFI_UNSUPPORTED)) { + DEBUG (( + DEBUG_ERROR, + "%a: MapGcdMmioSpace[0x%Lx-0x%Lx]: %r\n", + Status, + Io.Base - Io.Translation, + Io.Limit - Io.Base + 1 + )); + } + } + + Attributes =3D EFI_PCI_ATTRIBUTE_ISA_IO_16 | + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | + EFI_PCI_ATTRIBUTE_VGA_IO_16 | + EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16; + + AllocationAttributes =3D 0; + if ((PMem.Base > PMem.Limit) && + (PMemAbove4G.Base > PMemAbove4G.Limit)) + { + AllocationAttributes |=3D EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM; + } + + if ((MemAbove4G.Base <=3D MemAbove4G.Limit) || + (PMemAbove4G.Limit <=3D PMemAbove4G.Limit)) + { + AllocationAttributes |=3D EFI_PCI_HOST_BRIDGE_MEM64_DECODE; + } + + Bridge->DmaAbove4G =3D TRUE; + Bridge->Supports =3D Attributes; + Bridge->Attributes =3D Attributes; + Bridge->AllocationAttributes =3D AllocationAttributes; + Bridge->Bus.Base =3D BusMin; + Bridge->Bus.Limit =3D BusMax; + Bridge->NoExtendedConfigSpace =3D FALSE; + + CopyMem (&Bridge->Io, &Io, sizeof (Io)); + CopyMem (&Bridge->Mem, &Mem, sizeof (Mem)); + CopyMem (&Bridge->MemAbove4G, &MemAbove4G, sizeof (MemAbove4G)); + CopyMem (&Bridge->PMem, &PMem, sizeof (PMem)); + CopyMem (&Bridge->PMemAbove4G, &PMemAbove4G, sizeof (PMemAbove4G)); + + return EFI_SUCCESS; +} + +/** + Populate and return all the root bridge instances in an array. + + @param Count Where to store the number of returned PCI_ROOT_BRIDGE str= ucts. + + @return A Count-sized array of PCI_ROOT_BRIDGE on success. NULL otherwis= e. +**/ +PCI_ROOT_BRIDGE * +EFIAPI +PciHostBridgeGetRootBridges ( + OUT UINTN *Count + ) +{ + EFI_STATUS Status; + PCI_ROOT_BRIDGE *Bridges; + MY_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath; + + // + // Only support one RootBridge with single PcdPciExpressBaseAddress + // + *Count =3D 1; + + Bridges =3D AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE) * (*Count)); + if (Bridges =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: %r\n", __func__, EFI_OUT_OF_RESOURCES)); + return NULL; + } + + DevicePath =3D AllocateCopyPool ( + sizeof mRootBridgeDevicePathTemplate, + &mRootBridgeDevicePathTemplate + ); + if (DevicePath =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: %r\n", __func__, EFI_OUT_OF_RESOURCES)); + return NULL; + } + + DevicePath->AcpiDevicePath.UID =3D 0; + Bridges[0].Segment =3D 0; + Bridges[0].DevicePath =3D (VOID *)DevicePath; + + Status =3D ProcessPciHost (&Bridges[0]); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: ProcessPciHost[0]: %r\n", + __func__, + Status + )); + FreePool (DevicePath); + } + + return Bridges; +} + +/** + Free the root bridge instances array returned from PciHostBridgeGetRootB= ridges(). + + @param Bridges The root bridge instances array. + @param Count The count of the array. +**/ +VOID +EFIAPI +PciHostBridgeFreeRootBridges ( + PCI_ROOT_BRIDGE *Bridges, + UINTN Count + ) +{ + UINTN Index; + + for (Index =3D 0; Index < Count; Index++, Bridges++) { + FreePool (Bridges->DevicePath); + } + + FreePool (Bridges); +} + +/** + Inform the platform that a resource conflict happens. + + @param HostBridgeHandle Handle of the Host Bridge. + @param Configuration Pointer to PCI I/O and PCI memory resource + descriptors. The Configuration contains the reso= urces + for all the root bridges. The resource for each = root + bridge is terminated with END descriptor and an + additional END is appended indicating the end of= the + entire resources. The resource descriptor field + values follow the description in + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + .SubmitResources(). +**/ +VOID +EFIAPI +PciHostBridgeResourceConflict ( + EFI_HANDLE HostBridgeHandle, + VOID *Configuration + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + UINTN RootBridgeIndex; + + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n")); + + RootBridgeIndex =3D 0; + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration; + while (Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); + for ( ; Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR; Descrip= tor++) { + ASSERT ( + Descriptor->ResType < + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr) + ); + DEBUG (( + DEBUG_ERROR, + " %s: Length/Alignment =3D 0x%lx / 0x%lx\n", + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], + Descriptor->AddrLen, + Descriptor->AddrRangeMax + )); + if (Descriptor->ResType =3D=3D ACPI_ADDRESS_SPACE_TYPE_MEM) { + DEBUG (( + DEBUG_ERROR, + " Granularity/SpecificFlag =3D %ld / %02x%s\n", + Descriptor->AddrSpaceGranularity, + Descriptor->SpecificFlag, + ((Descriptor->SpecificFlag & + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE + ) !=3D 0) ? L" (Prefetchable)" : L"" + )); + } + } + + // + // Skip the END descriptor for root bridge + // + ASSERT (Descriptor->Desc =3D=3D ACPI_END_TAG_DESCRIPTOR); + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( + (EFI_ACPI_END_TAG_D= ESCRIPTOR *)Descriptor + 1 + ); + } +} diff --git a/Platform/Qemu/RiscVQemuServerPlatform/Library/PciHostBridgeLib= Ecam/PciHostBridgeLibEcam.inf b/Platform/Qemu/RiscVQemuServerPlatform/Libra= ry/PciHostBridgeLibEcam/PciHostBridgeLibEcam.inf new file mode 100755 index 00000000..971a1b56 --- /dev/null +++ b/Platform/Qemu/RiscVQemuServerPlatform/Library/PciHostBridgeLibEcam/Pc= iHostBridgeLibEcam.inf @@ -0,0 +1,49 @@ +## @file +# +# PCI Host Bridge Library instance for pci-host-ecam-generic +# compatible RC implementations. +# +# Copyright (c) 2024, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D PciHostBridgeLibEcam + FILE_GUID =3D E88D8506-4701-45BE-A116-B3260679CDB3 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciHostBridgeLib|DXE_DRIVER + +# +# The following information is for reference only and not required by the = build +# tools. +# +# VALID_ARCHITECTURES =3D ARM AARCH64 RISCV64 +# + +[Sources] + PciHostBridgeLibEcam.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec + +[LibraryClasses] + DebugLib + DevicePathLib + MemoryAllocationLib + PcdLib + +[Pcd] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciBusMin + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciBusMax + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciIoBase + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciIoSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio32Base + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio32Size + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio64Base + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio64Size diff --git a/Platform/Qemu/RiscVQemuServerPlatform/Library/VirtNorFlashPlat= formLib/VirtNorFlashStaticLib.c b/Platform/Qemu/RiscVQemuServerPlatform/Lib= rary/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c new file mode 100755 index 00000000..d86cffae --- /dev/null +++ b/Platform/Qemu/RiscVQemuServerPlatform/Library/VirtNorFlashPlatformLib= /VirtNorFlashStaticLib.c @@ -0,0 +1,42 @@ +/** @file + + Copyright (c) 2019, Linaro Ltd. All rights reserved + Copyright (c) 2024, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + **/ + +#include +#include +#include + +#define QEMU_NOR_BLOCK_SIZE SIZE_256KB + +EFI_STATUS +VirtNorFlashPlatformInitialization ( + VOID + ) +{ + return EFI_SUCCESS; +} + +VIRT_NOR_FLASH_DESCRIPTION mNorFlashDevice =3D +{ + FixedPcdGet32 (PcdVariableFdBaseAddress), + FixedPcdGet64 (PcdFlashNvStorageVariableBase), + FixedPcdGet32 (PcdVariableFdSize) - + (FixedPcdGet64 (PcdFlashNvStorageVariableBase) - FixedPcdGet32 (PcdVaria= bleFdBaseAddress)), + QEMU_NOR_BLOCK_SIZE +}; + +EFI_STATUS +VirtNorFlashPlatformGetDevices ( + OUT VIRT_NOR_FLASH_DESCRIPTION **NorFlashDescriptions, + OUT UINT32 *Count + ) +{ + *NorFlashDescriptions =3D &mNorFlashDevice; + *Count =3D 1; + return EFI_SUCCESS; +} diff --git a/Platform/Qemu/RiscVQemuServerPlatform/Library/VirtNorFlashPlat= formLib/VirtNorFlashStaticLib.inf b/Platform/Qemu/RiscVQemuServerPlatform/L= ibrary/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.inf new file mode 100755 index 00000000..16eac026 --- /dev/null +++ b/Platform/Qemu/RiscVQemuServerPlatform/Library/VirtNorFlashPlatformLib= /VirtNorFlashStaticLib.inf @@ -0,0 +1,32 @@ +#/** @file +# +# Component description file for VirtNorFlashStaticLib module +# +# Copyright (c) 2014, Linaro Ltd. All rights reserved.
+# Copyright (c) 2024, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D VirtNorFlashStaticLib + FILE_GUID =3D 9A42D578-7E22-40F8-A587-4759F0DC93BA + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D VirtNorFlashPlatformLib + +[Sources.common] + VirtNorFlashStaticLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + OvmfPkg/OvmfPkg.dec + Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec + +[Pcd] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase diff --git a/Platform/Qemu/RiscVQemuServerPlatform/Readme.md b/Platform/Qem= u/RiscVQemuServerPlatform/Readme.md new file mode 100755 index 00000000..eaab90e9 --- /dev/null +++ b/Platform/Qemu/RiscVQemuServerPlatform/Readme.md @@ -0,0 +1,327 @@ +# RISC-V UEFI PI Reference Board Port Guide +The goal of this document is to provide a generic server platform firmware= solution applicable to systems built on the RISC-V architecture SOC. + +## INDEX +* 1 [Overview](#1-Overview) +* 2 [Server SOC Reference Model](#2-Server-SOC-Reference-Model) +* 3 [Boot Flow](#3-Boot-Flow) +* 4 [Verification](#4-Verification) +* 5 [Pending Tasks](#5-Pending-Tasks) +* 6 [Known Issues](#6-Known-Issues) +* 7 [Appendix](#7-Appendix) + + +## 1 Overview +### 1.1 References +* UEFI Specification v2.10: https://uefi.org/sites/default/files/resources= /UEFI_Spec_2_10_Aug29.pdf +* UEFI PI Specification v1.8.0: https://uefi.org/sites/default/files/resou= rces/UEFI_PI_Spec_1_8_March3.pdf +* ACPI Specification v6.5: https://uefi.org/sites/default/files/resources/= ACPI_Spec_6_5_Aug29.pdf +* OpenSbi Specification: https://github.com/riscv-software-src/opensbi +* BRS Specification: https://github.com/riscv-non-isa/riscv-brs=20 +* Device Tree Specification v0.4: https://www.devicetree.org/ +* Smbios Specification v3.7.0: https://www.dmtf.org/sites/default/files/st= andards/documents/DSP0134_3.7.0.pdf +* Server Soc Specification: https://github.com/riscv-non-isa/server-soc + +### 1.2 Target Audience +This document is intended for the following readers: +* IHVs and OSVs who actively engaged in the building of the RISC-V ecosyst= em, serving as a vital component in the vertical integration of systems. +* Bios developers, either those who create general-purpose BIOS and other = firmware products or those who modify these products for use in various ven= dor architecture-based products. +* Other stakeholders who are interested in the RISC-V platform and have fi= rmware development needs. + +### 1.3 Terminology + +| Term | Description +|:-------------------- |:------------------------- +| UEFI | Unified Extensible Firmware Interface +| SBI | Supervisor Binary Interface +| BRS | Boot and Runtime Services +| BMC | Baseboard Management Component BMC's main functio= n is to automatically monitor the system platform management events, the ev= ents recorded in the system event log. +| OOB | Out of Band +| RVI | [RISC-V International](https://riscv.org/) +| RISE | [RISC-V Software Ecosystem](https://wiki.riseproj= ect.dev/display/HOME/About+RISE) +| BRS | Boot and Runtime Services +| SCT | UEFI Self Certification Tests=20 +| FWTS | Firmware Test Suite +| SPL | U-Boot Second Program Loader +| SAL | System Abstraction Layer + + +## 2 Server SOC Reference Model + +### 2.1 Requirements +This qemu virtual machine (server soc reference board) is required to be c= ompliant with RISC-V [Server SOC Spec](https://github.com/riscv-non-isa/ser= ver-soc) (the commit id at writing this doc is aec20046c35b108f76a11a751f75= 4505aaad7800) as much as possible. + +#### Table 1 Server SOC Requirement + +| Items | Requirements | On qemu reference board (1st version)| F= uture Plan +|:-------------------- |:-------------------------|:-------------------- |= :------------------------- +| 2.1. Clocks and Timers | time CSR | supported=20 +| 2.2. External Interrupt Controllers | AIA | supported with non-upstream = patches=20 +| 2.3. Input-Output Memory Management Unit (IOMMU) | RISC-V IOMMU spec | n= o support (need qemu/linux patches) | Yes +| 2.4. PCIe Subsystem Integration | PCIe features | supported using existi= ng qemu implementation |=20 +| 2.5. Reliability, Availability, and Serviceability (RAS) | The level of = RAS implemented by the SoC is UNSPECIFIED | not considered +| 2.6. Quality of Service | capacity and bandwidth controller register int= erface (CBQRI), etc. | not considered |=20 +| 2.7. Manageability | BMC | no support | TBD +| 2.8. Performance Monitoring | HPM counters | supported |=20 +| 2.9. Security Requirements | On PCIe, off-chip DRAM and TPM | no support= (follow qemu existing features) | Yes (for TPM) +| Harts features | (removed from this spec) | support the previous stated = hart features |=20 + + +### 2.2 High Level Design +The Implementation Choices +* Make the configuration as fixed as possible so that this new machine is = easy-to-go and less confusing. +* Remove the unnecessary devices as many as possible, e.g. CLINT/PLIC are = removed. +* Keep the MemMap entries as similar as RiscVVirt vm for easy adoption at = the early stage. +* Keep dtb entries as small as possible. +#### Table 2 Devices and Memory Mappings + +| Devices | Base Addr | Size | Comment=20 +|:-------------------- |:-------------------------|:-------------------- |= :------------------------- +| MROM | 0x1000 | 0xf000 |=20 +| TEST | 0x100000 | 0x1000 | For reset function (name misleading?) +| RTC | 0x101000 | 0x1000 |=20 +| ACLINT | 0x2000000 | 0x10000 | aclint mtimer (spec definition missed) +| PCIE_PIO | 0x3000000 | 0x10000 |=20 +| APLIC_M | 0xc000000 | APLIC_SIZE(SSOC_CPUS_MAX) | fixed AIA +| APLIC_S | 0xd000000 | APLIC_SIZE(SSOC_CPUS_MAX) |=20 +| UART0 | 0x10000000 | 0x100 |=20 +| FW_CFG | 0x10200000 | 0x18 | depend on ACPI support on firmware +| FLASH | 0x20000000 | 0x4000000 |=20 +| IMSIC_M | 0x24000000 | SSOC_IMSIC_MAX_SIZE |=20 +| IMSIC_S | 0x28000000 | SSOC_IMSIC_MAX_SIZE |=20 +| PCIE_ECAM | 0x30000000 | 0x10000000 |=20 +| PCIE_MMIO | 0x40000000 | 0x40000000 |=20 +| DRAM | 0x80000000 | 0xff80000000ull (max) | still one continuous range +| VIRT64_HIGH_PCIE_MMIO | 0x10000000000ull | 0x10000000000ull | different = from RiscVVirt +| AHCI | Handled as the PCIe device | |=20 +| EHCI | Handled as the PCIe device | |=20 +| IOMMU | to be decided | | patch yet to integrate (kernel/qemu/=E2=80= =A6) + +### 2.3 Qemu/Guest FW Interface +#### Hardcode Addresses +It's possible qemu and guest have no explicit interface about some informa= tion, e.g. address of specific devices, but both of them hardcodes the same= address to access the device. + +## 3 Boot Flow +The following diagram illustrates various platform initialization scenario= s. This document will not cover the detailed work of initializing on real h= ardware platforms, as it is beyond its scope. Our focus will be on the more= general firmware initialization tasks performed on the qemu emulator. See = the part of the diagram indicated by the blue color, which corresponds to Q= emuServerPlatform Boot Flow. + +Note: _For specifics on the qemu Server SOC reference model in this docume= nt, it is essential to consult both the latest developments in the qemu sou= rce code and the definition in the server platform specifications. Relevant= information for both can be obtained from Server SOC TG and Server Platfor= m TG of RVI.c_ + +#### Figuire 1 RISC-V Platform EDK2 Firmware Enabling Philosophy + +![RISC-V_Platform_EDK2_Firmware_Enabling_Philosophy](https://github.com/Ch= aiEvan/edk2-platforms/blob/RV_ServerPlatformRef_v1/Platform/Qemu/RiscVQemuS= erverPlatform/Documents/Media/RISC-V_Platform_EDK2_Firmware_Enabling_Philos= ophy.jpg) + +### 3.1 The Traditional Boot Flow + +[PI Architecture Firmware Phases](https://uefi.org/specs/PI/1.8/V2_Overvie= w.html#pi-architecture-firmware-phases) shows the phases that a platform wi= th PI Architecture firmware will execute. + +#### Figuire 2 PI Architecture Firmware Phases + +![PI_Boot_Phases](https://github.com/ChaiEvan/edk2-platforms/blob/RV_Serve= rPlatformRef_v1/Platform/Qemu/RiscVQemuServerPlatform/Documents/Media/PI_Bo= ot_Phases.jpg) + +_In a PI Architecture firmware implementation, the phase executed prior to= DXE is PEI. This specification covers the transition from the PEI to the D= XE phase, the DXE phase, and the DXE phase=E2=80=99s interaction with the B= DS phase. The DXE phase does not require a PEI phase to be executed. The on= ly requirement for the DXE phase to execute is the presence of a valid HOB = list. There are many different implementations that can produce a valid HOB= list for the DXE phase to execute. The PEI phase in a PI Architecture firm= ware implementation is just one of many possible implementations._ + +Based on the content quoted from the PI specification above, it is evident= that the PEI phase is merely a traditional and integral part of the UEFI b= oot flow. In actual PI Architecture firmware implementations, it is not man= datory. Currently, the primary purpose of the PEI Phase is to perform memor= y initialization and pass necessary HOBs to DXE.=20 + +For the former, the alternative solution for the former involves the imple= mentation of OOB firmware, which is currently beyond the scope of this docu= ment. Regarding the latter, we can move more works for building Hand-Off Bl= ocks (HOBs) to the SEC phase. All of these considerations collectively cont= ribute to providing additional insights and flexibility for the practical i= nitiation of hardware. + +### 3.2 Alternative Boot Flow +The boot flow without the PEI phase, also known as the Pei-Less flow, is t= he initialization approach that will be further discussed in this document.= Detailed standards for Pei-Less can be obtained from RISE's Firmware TG. + +#### 3.2.1 SEC Phase +See [HOB Translations](https://uefi.org/specs/PI/1.8/V2_DXE_Foundation.htm= l#hob-translations) for more information on HOB types. + +#### Figuire 3 HOB List +![V2_DXE_Foundation-2](https://github.com/ChaiEvan/edk2-platforms/blob/RV_= ServerPlatformRef_v1/Platform/Qemu/RiscVQemuServerPlatform/Documents/Media/= Hand-Off-Block-Hob-List.jpg) + +The HOBs list, as mandated by the PI specification, is illustrated in Figu= re 2.3. It is recommended to refer to the SecMain structure in RiscVVirt fo= r guidance. + +Figure 2.3 displays the HOBs list, a prerequisite set by the PI specificat= ion for readiness before entering the DXE phase. For additional insights, i= t is recommended to refer to the SecMain module in RiscVVirt. + +Regarding memory initialization, specific details are intentionally omitte= d in this document. The recommended strategy involves the use of OOB firmwa= re, like SPL. This provides input to the System Memory HOB generated by the= UEFI firmware during the SEC phase, and the input for HOB is extracted fro= m static data in the device tree, including entries like 'memory' by AddMem= oryBaseSizeHob() and 'reserved-memory BuildMemoryAllocationHob().'=20 + +The creation of HOBs for IO, MMIO, and other resources provides SOC vendor= s with the flexibility to customize according to their chip specifications.= The PopulateIoResources() function provides a straightforward approach to = achieve this customization. + +It is essential to emphasize that RiscVVirt adopts a separate Flash Descri= ptor (FD) approach for firmware code and Variables. The advantage is clear = as it allows for the protection of the firmware code by setting it as read-= only, while conferring write permissions exclusively to the Variable FD, ef= fectively ensuring the security of the firmware. Particularly, this approac= h provides convenient and flexible control, especially when dealing with fi= rmware upgrade actions in the future. Of course, in qemu-based firmware dev= elopment, virtualizing two or even more flashes is extremely straightforwar= d. However, it's worth mentioning that in many real hardware platforms, the= single-flash configuration is more common, and further elaboration on this= point is not necessary here. + +In the upcoming server platform solution, we will continue to adopt a simi= lar approach as RiscVVirt. However, there is a slight difference in the tre= atment of the Variable FD. We prefer to establish a corresponding Memory HO= B for the Variable's scope during the SEC phase,=20 + +The advantage of this adjustment is that there is no longer a strong depen= dency between VariableRuntimeDxe and VirtNorFlashDxe. We no longer need to = ensure that VirtNorFlashDxe is dispatched before VariableRuntimeDxe. To ach= ieve this purpose, the following two steps must be taken:=20 +* Build Memory Hob for variable region by BuildResourceDescriptorHob() in = SEC phase. +* Replace the version of Ovfm with a new VirtNorFlashDxe driver or remove = its GCD mapping related code. To avoid compatibility issues with other plat= forms, the first implementation approach is adopted in this document. + +#### 3.2.2 DXE Phase +The following table supplements the missing implementation details in Tabl= e 2.5 of the PI specification. The DXE Foundation is abstracted from the pl= atform through the DXE Architectural Protocols. The DXE Architectural Proto= cols manifest the platform-specific components of the DXE Foundation. DXE d= rivers that are loaded and executed by the DXE Dispatcher component of the = DXE Foundation must produce these protocols. + +For implementations outside of the EmbeddedPkg solutions, please follow th= e guidance outlined in the table. + + +#### Table 3 DXE Architectural Protocols +Protocol Name|Driver Path in use|Driver Compatibility __1__|Task required +|:--------------------|:-------------------------|:--------------------|:-= ------------------- +|Security Architectural|MdeModulePkg/Universal/SecurityStubDxe/SecurityStu= bDxe.inf|Platform independent|no extra work +|CPU Architectural|UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf|Platform dep= endent|no extra work +|Metronome Architectural|EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf (__Note= __: Precision in the EmbeddedPkg version is limited to microseconds, wherea= s the MdeModulePkg version offers precision down to nanoseconds.)|Platform = dependent|no extra work +|Timer Architectural|UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf = (__Note__: In S mode, utilize the TIME CSR for implementing GetTimer, and a= chieve SetTimer by the =E2=80=98Set Timer=E2=80=99 interface of SBI Timer E= xtension 6.1. Please note that the Runtime type of timer service isn=E2=80= =99t presently supported yet. Runtime type of timer service will be produce= d by RealTimeClock.)|Platform dependent|no extra work +|BDS Architectural|MdeModulePkg/Universal/BdsDxe/BdsDxe.inf|Platform indep= endent|no extra work +|Watchdog Timer Architectural|MdeModulePkg/Universal/WatchdogTimerDxe/Watc= hdogTimer.inf (__Note__: It depends on TimerLib and ResetLib, the implement= ation of which is typically determined by the different CPU architectures.)= |Platform independent|no extra work +|Runtime Architectural|MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf (__Note= __: Some functionalities in the RISC-V version of CacheMaintenanceLib are s= till under development.)|Platform independent|need to complete the remainin= g functions of CacheMaintenanceLib. +|Variable Architectural|MdeModulePkg/Universal/Variable/RuntimeDxe/Variabl= eRuntimeDxe.inf (__Note__: The dependency issue on VirtNorFlashDxe in RiscV= Virt has been clarified in the preceding chapters. Please refer to Section = 2.10 for details.)|Platform independent|no extra work +|Variable Write ArchitecturalProtocol|MdeModulePkg/Universal/Variable/Runt= imeDxe/VariableRuntimeDxe.inf | Platform independent|no extra work +|Monotonic Counter Architectural|MdeModulePkg/Universal/MonotonicCounterRu= ntimeDxe/MonotonicCounterRuntimeDxe.inf|Platform independent|no extra work +|Reset Architectural|MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSys= temRuntimeDxe.inf (__Note__: ResetSystemLib implements warm reset, cold res= et, and shutdown through the SBI interface.)|Platform independent|no extra = work +|Real Time Clock Architectural|EmbeddedPkg/RealTimeClockRuntimeDxe/RealTim= eClockRuntimeDxe.inf (__Note__: Some features in RealTimeClockLib remain un= implemented, including GetWakeUpTime/SetWakeUpTime. The present RealTimeClo= ckLib is specifically designed for qemu; future adaptations should implemen= t their own RTC timer based on the platform's needs.)|Platform dependent|no= extra work +|Capsule Architectural Protocol|MdeModulePkg/Universal/CapsuleRuntimeDxe/C= apsuleRuntimeDxe.inf (__Note__: It depends on CacheMaintenanceLib and Reset= Lib.)|Platform independent|no extra work + +Note: +_1.The 'Driver Compatibility, task required' column addresses platform dep= endencies exclusively at the DXE driver level. The platform-specificity of = the consumed libraries does not influence the conclusion._ + +#### 3.2.3 Network Stack +The Server SOC model currently in use, 'ssoc_ref,' comes with e1000 as the= default NIC device. However, as this device lacks an integrated UEFI UNDI = driver, it cannot provide the foundational services to enable the network. = >From a testing perspective, here are two recommended steps=EF=BC=9A +* Build UndiRuntimeDxe to your firmware FD, with the following patch: edk2= -platforms/Drivers/OptionRomPkg/UndiRuntimeDxe/UndiRuntimeDxe.inf +* Append NIC =E2=80=98i82557b=E2=80=99 to the qemu command line. See the r= eference command in Chapter 4. + +From a product implementation perspective, it is not recommended to direct= ly use UndiRuntimeDxe as the provider for the UNDI services. It is more app= ropriate to provide the UNDI services based on the NIC device integrated in= to the platform. + +### 3.3 Extra work for Fdt-to-OS +The DXE Foundation produces the UEFI System Table, and the UEFI System Tab= le is consumed by every DXE driver and executable image invoked by the DXE = Dispatcher and BDS. It contains all the information required for these comp= onents to utilize the services provided by the DXE Foundation and the servi= ces provided by any previously loaded DXE driver. [UEFI System Table and Re= lated Components](https://uefi.org/specs/PI/1.8/V2_DXE_Foundation.html#uefi= -system-table-and-related-components) shows the various components that are= available through the UEFI System Table. + +#### Figuire 4 UEFI System Table and Related Components +![V2_DXE_Foundation-3](https://github.com/ChaiEvan/edk2-platforms/blob/RV_= ServerPlatformRef_v1/Platform/Qemu/RiscVQemuServerPlatform/Documents/Media/= V2_DXE_Foundation-3.jpg) + +As shown in figure 9.2, the UEFI Configuration Tables are an extensible li= st of tables that describe the configuration of the platform. Today, this i= ncludes pointers to tables such as DXE Services, the HOB list, ACPI table, = SMBIOS table, and the SAL System Table. This list may be expanded in the fu= ture as new table types are defined.=20 + +Due to the broad usage of device trees in embedded firmware products, seve= ral chip manufacturers in the upstream and downstream supply chains use sta= tic data from the device tree to initialize specific peripherals. For compa= tibility reasons, it is essential to install the device tree pointer into t= he system configuration table. Two DXE drivers are available as references: + +#### Table 4 The Proposal for FdtTabGuid +|Table Guid |Driver Path in use |Comments +|:-------------------- |:-------------------------|:-------------------- +|gFdtTableGuid |EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf |Using i= n RiscVVirt +|gFdtTableGuid |Silicon/RISCV/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf |Re= commend using the streamlined DXE driver if no required for FdtClientProtoc= l + +### 3.4 DT File Decoding=20 +The DXE driver FdtClientDxe, mentioned in the previous section, supplies a= limited set of APIs for parsing DT binary, handling fundamental DT data ex= traction tasks.=20 + +Users with more advanced demands can turn to another DXE service produced = by [FdtBusPkg](https://github.com/intel/FdtBusPkg), which offers an extensi= ve array of APIs to meet the requirements of more complex scenarios. Detail= ed information is accessible in the firmware TG of RISE community (Project = No. [EDK2_00_03](https://wiki.riseproject.dev/display/HOME/Firmware+Project= s)), and the source code is available from [FdtBusPkg](https://github.com/i= ntel/FdtBusPkg) repository. It will be upstreamed to the [edk2](https://git= hub.com/tianocore/edk2) repository in the future, and any suggestions or re= quirements for improvement are encouraged before this transition. + +### 3.5 OpenSbi +It is recommended to align with the version of OpenSBI in the [RISC-V BRS = Development Suite Repository](https://github.com/intel/rv-brs-test-suite). = The binary file can be found at the following path: ./rv-brs-test-suite/br= si/scripts/opensbi/build/platform/generic/firmware/fw_dynamic.bin + +__Or build it by the command example1__: +``` +cd opensbi +make ARCH=3Driscv CROSS_COMPILE=3Driscv64-linux-gnu- PLATFORM=3Dgeneric +``` +### 3.6 OS Image=20 +Similarly, the BRS Repo offers an OS image based on RISC-V. To validate th= e boot flow, you can make use of the prebuilt images located in the test su= ite at /rv-brs-test-suite/brsi/prebuilt_images/. For those interested in bu= ilding their own image, please refer to the repository guidance for detaile= d steps. + +## 4 Verification +The tests covered in this document are based on the BRS spec, focusing on = two primary modules: SCT and FWTS. The relevant test scripts, pre-build ima= ge and guidance can be obtained from the [RISC-V BRS Development Suite Repo= sitory](https://github.com/intel/rv-brs-test-suite): + +__Command example2__: +``` =20 + ./qemu-system-riscv64 -nographic -m 8G -smp 2 \ + -machine ssoc_ref,pflash0=3Dpflash0,pflash1=3Dpflash1 \ + -blockdev node-name=3Dpflash0,driver=3Dfile,read- only=3Don,filename=3D$F= W_DIR/RISCV_SP_CODE.fd \ + -blockdev node-name=3Dpflash1,driver=3Dfile,filename=3D=3D$FW_DIR/RISCV_S= P_VARS.fd \ + -bios $Sbi_DIR/fw_dynamic.bin \ + -drive file=3D$Img_DIR/brs_live_image.img,if=3Dide,format=3Draw +``` + +__Note__: +* _=E2=80=98ssoc_ref=E2=80=99 is a specified qemu-based SOC model, whose s= ource code is still under development and will be accessible from the RVI s= taging repository later._ +* _The Pre-build image =E2=80=98brs_live_image.img,if=E2=80=99 can be down= loaded in RISC-V BRS Development Suite repository, or you can build it by y= ourself. See 3.6_ +* _=E2=80=98-bios $Sbi_DIR/fw_dynamic.bin=E2=80=99 the parameter points to= the opensbi path. See more in 3.5._ + +In general, a series of modules related to Network are enabled by default.= However, during SCT test execution, it is noticed that most Network test i= tems fail to pass. The most likely reason is the lack of a UNDI driver buil= t in the current platform firmware codebase. So, if you intend to enable th= e edk2 network stack with QEMU in the boot flow, it is suggested to use the= following command: + +__Command example3__: +``` + Command example2 \ + -device i82557b,netdev=3Dnet2 \ + -netdev type=3Duser,id=3Dnet2 +``` + +## 5 Pending Tasks +The listed items in the table represent ongoing firmware development tasks= that are still unfinished. Some specifications are in the process of refin= ement, and a few are yet to be drafted. Please refer to subsequent updates = from the RISE community for more information. +### 5.1 Bios Requirements + +#### Table 5 Bios Requirements +ID | Requirement | Comment +|:-------------------- |:-------------------------|:-------------------- +|1 | ACPI enabling | The establishment of all ACPI tables is currently ach= ieved through qemu, leveraging a series of libraries such as QemuFwCfgLib t= o interact with the Linux kernel. The following task is to implement the pu= blishment of all ACPI tables solely through firmware. +|2 | Smbios | The upcoming tasks for SMBIOS should be handled exclusively = through firmware publishment, replacing the existing qemu method entirely. +|4 | FWTS test | Upon the completion of tasks 1 and 2, the pass ratio for = FWTS should be maintained at a specific benchmark. +|5 | Security | Not started=20 +|6 | TPM | Not started=20 + +## 6 Known Issues +The following table outlines the current known issues, which will be resol= ved gradually during the subsequent phases of development. + +#### Table 6 Known Issues +No. | Issue Description | Cause | Comment +|:--------------------|:-------------------------|:--------------------|:-= ------------------- +|1 | Graphic device doesn=E2=80=99t work | =E2=80=98Ssoc_ref=E2=80=99 does= n=E2=80=99t provide a default GPU yet | Will do in next phase +|2 | ACPI/Smbios don=E2=80=99t work | Not firmware implementation | Will d= o in next phase + +## 7 Appendix + + + +### 7.1 Building and running based on BRS environment + +1. Build brs test suit +``` +git clone https://github.com/intel/rv-brs-test-suite.git +``` + +Please refer to detailed build steps from [README.md](https://github.com/i= ntel/rv-brs-test-suite/blob/main/README.md), then you will get the followin= g stuff: +``` + QEMU_DIR=3D$WORKSPACE/rv-brs-test-suite/brsi/scripts/qemu/build + BRS_IMG_DIR=3D$WORKSPACE/rv-brs-test-suite/brsi/scripts/output + OPENSBI_DIR=3D$WORKSPACE/rv-brs-test-suite/brsi/scripts/opensbi/build/pla= tform/generic/firmware + EDK2_DIR=3D$WORKSPACE/rv-brs-test-suite/brsi/scripts/Build/RiscVQemuServe= rPlatform/DEBUG_GCC5/FV +``` + +2. Boot Execution(See Command example2) +``` +$QEMU_DIR/qemu-system-riscv64 \ + -machine ssoc_ref,pflash0=3Dpflash0,pflash1=3Dpflash1 \ + -blockdev node-name=3Dpflash0,driver=3Dfile,read-only=3Don,filename=3D$ED= K2_DIR/RISCV_SP_CODE.fd \ + -blockdev node-name=3Dpflash1,driver=3Dfile,filename=3D$EDK2_DIR/RISCV_SP= _VARS.fd \ + -bios $OPENSBI_DIR/fw_dynamic.bin \ + -drive file=3D$BRS_IMG_DIR/brs_live_image.img,if=3Dide,format=3Draw +``` +### 7.2 Compiling edk2 firmware separately outside of BRS +1. Building the RISC-V edk2 server platform=20 + +``` +git clone https://github.com/tianocore/edk2.git +cd edk2 +git submodule update --init +cd .. + +git clone https://github.com/tianocore/edk2-platforms.git +cd edk2-platforms +git submodule update --init +cd .. + +export WORKSPACE=3D`pwd` +export GCC5_RISCV64_PREFIX=3Driscv64-linux-gnu- +export PACKAGES_PATH=3D$WORKSPACE/edk2:$WORKSPACE/edk2-platforms + +cd edk2 +make -C BaseTools clean +make -C BaseTools +source edksetup.sh +./edksetup.sh + +build -a RISCV64 -t GCC5 -p Platform/Qemu/RiscVQemuServerPlatform/RiscVQem= uServerPlatform.dsc +``` +2. Convert FD files +``` + truncate -s 32M Build/RiscVQemuServerPlatform/DEBUG_GCC5/FV/RISCV_SP_CODE= .fd + truncate -s 32M Build/RiscVQemuServerPlatform/DEBUG_GCC5/FV/RISCV_SP_VARS= .fd +``` + +## Contributors +- Evan Chai diff --git a/Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.= dsc b/Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.dsc new file mode 100755 index 00000000..45501b35 --- /dev/null +++ b/Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.dsc @@ -0,0 +1,703 @@ +## @file +# RISC-V EFI on Qemu Server Platform +# +# Copyright (c) 2024, Intel Corporation. All rights reserved.
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + PLATFORM_NAME =3D RiscVQemuServerPlatform + PLATFORM_GUID =3D A5FAC672-1D51-4461-AB37-B7DB202F34BA + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x0001001c + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES =3D RISCV64 + BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Platform/Qemu/RiscVQemuServerPlatform= /RiscVQemuServerPlatform.fdf + + # + # Enable below options may cause build error or may not work on + # the initial version of RISC-V package + # Defines for default states. These can be changed on the command line. + # -D FLAG=3DVALUE + # + DEFINE TTY_TERMINAL =3D FALSE + DEFINE SECURE_BOOT_ENABLE =3D FALSE + DEFINE TPM2_ENABLE =3D FALSE + DEFINE TPM2_CONFIG_ENABLE =3D FALSE + DEFINE DEBUG_ON_SERIAL_PORT =3D TRUE + + # + # Network definition + # + DEFINE NETWORK_IP6_ENABLE =3D FALSE + DEFINE NETWORK_HTTP_BOOT_ENABLE =3D FALSE + DEFINE NETWORK_SNP_ENABLE =3D FALSE + DEFINE NETWORK_TLS_ENABLE =3D FALSE + DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS =3D TRUE + DEFINE NETWORK_ISCSI_ENABLE =3D FALSE + + DEFINE DEBUG_PRINT_ERROR_LEVEL =3D 0x80000047 + +!if $(NETWORK_SNP_ENABLE) =3D=3D TRUE + !error "NETWORK_SNP_ENABLE is IA32/X64/EBC only" +!endif + +!include MdePkg/MdeLibs.dsc.inc +!include NetworkPkg/Network.dsc.inc + +[BuildOptions] + GCC:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG +!ifdef $(SOURCE_DEBUG_ENABLE) + GCC:*_*_RISCV64_GENFW_FLAGS =3D --keepexceptiontable +!endif + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + GCC: *_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 + MSFT: *_*_*_DLINK_FLAGS =3D /ALIGN:4096 + +##########################################################################= ###### +# +# Library Class section - list of all Library Classes needed by this Platf= orm. +# +##########################################################################= ###### +!include MdePkg/MdeLibs.dsc.inc + +[LibraryClasses.common] +!ifdef $(SOURCE_DEBUG_ENABLE) + PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDeb= ug/PeCoffExtraActionLibDebug.inf + DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibS= erialPort/DebugCommunicationLibSerialPort.inf +!else + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif +!if $(DEBUG_ON_SERIAL_PORT) =3D=3D TRUE + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.in= f +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf + BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.i= nf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza= tionLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain= tenanceLib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDev= icePathLibDevicePathProtocol.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableL= ib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServic= esLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib= /BaseOrderedCollectionRedBlackTreeLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + + # + # Ramdisk Requirements + # + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + + # + # Add support for GCC stack protector + # + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf + + # + # RISC-V Architectural Libraries + # + CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandler= Lib/BaseRiscV64CpuExceptionHandlerLib.inf + RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf + RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf + ResetSystemLib|Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetS= ystemLib.inf + + RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualReal= TimeClockLib.inf + TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf + SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPort= Lib16550.inf + + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf + DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgent= TimerLibNull.inf + + # + # Flattened Device Tree (FDT) access library + # + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + + # + # PCI Libraries + # + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + + # + # USB Libraries + # + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + + # + # CryptoPkg libraries needed by multiple firmware features + # + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf +!if $(NETWORK_TLS_ENABLE) =3D=3D TRUE + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf +!else + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf +!endif + RngLib|MdePkg/Library/BaseRngLibTimerLib/BaseRngLibTimerLib.inf + + # + # Secure Boot dependencies + # +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf + SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBo= otVariableLib.inf + SecureBootVariableProvisionLib|SecurityPkg/Library/SecureBootVariablePro= visionLib/SecureBootVariableProvisionLib.inf + PlatformPKProtectionLib|SecurityPkg/Library/PlatformPKProtectionLibVarPo= licy/PlatformPKProtectionLibVarPolicy.inf + + # re-use the UserPhysicalPresent() dummy implementation from the ovmf tr= ee + PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.in= f +!else + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLib= Null.inf +!endif + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseV= ariableFlashInfoLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL= ib.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Var= iablePolicyHelperLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + + TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLi= b.inf + VirtNorFlashPlatformLib|Platform/Qemu/RiscVQemuServerPlatform/Library/Vi= rtNorFlashPlatformLib/VirtNorFlashStaticLib.inf + + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootM= anagerLib/PlatformBootManagerLib.inf + PlatformMemoryTestLib|Platform/RISC-V/PlatformPkg/Library/PlatformMemory= TestLibNull/PlatformMemoryTestLibNull.inf + PlatformUpdateProgressLib|Platform/RISC-V/PlatformPkg/Library/PlatformUp= dateProgressLibNull/PlatformUpdateProgressLibNull.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf + FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf + PciHostBridgeLib|Platform/Qemu/RiscVQemuServerPlatform/Library/PciHostBr= idgeLibEcam/PciHostBridgeLibEcam.inf + PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatfor= mHookLibNull.inf + ImagePropertiesRecordLib|MdeModulePkg/Library/ImagePropertiesRecordLib/I= magePropertiesRecordLib.inf + +!if $(TPM2_ENABLE) =3D=3D TRUE + Tpm2CommandLib|SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandLib.inf + Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeT= cg2PhysicalPresenceLib.inf + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure= mentLib.inf + TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi= b/PeiDxeTpmPlatformHierarchyLib.inf +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi= bNull/PeiDxeTpmPlatformHierarchyLib.inf +!endif + + RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.= inf + +[LibraryClasses.common.SEC] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibN= ull.inf + ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseE= xtractGuidedSectionLib.inf + PlatformSecLib|UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.= inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMe= moryAllocationLib.inf + +[LibraryClasses.common.DXE_CORE] + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerform= anceLib.inf + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC= oreMemoryAllocationLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + +[LibraryClasses.common.UEFI_APPLICATION] + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf +!if $(DEBUG_ON_SERIAL_PORT) =3D=3D TRUE + DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibS= erialPort.inf +!endif + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL= ibRuntimeDxe.inf + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf +!endif + +[LibraryClasses.common.DXE_DRIVER] + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + AcpiPlatformLib|OvmfPkg/Library/AcpiPlatformLib/DxeAcpiPlatformLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + +!if $(TPM2_ENABLE) =3D=3D TRUE + Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibTcg2/Tpm2DeviceLibTcg2.in= f +!endif + +[LibraryClasses.common.UEFI_DRIVER] + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +##########################################################################= ###### +[PcdsFeatureFlag.common] + # + # Activate AcpiSdtProtocol + # + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + + gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE + + # + # If TRUE, Graphics Output Protocol will be installed on virtual handle = created by ConsplitterDxe. + # It could be set FALSE to save size. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + +[PcdsFixedAtBuild.common] + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFC + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0 + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 + + # DEBUG_ASSERT_ENABLED 0x01 + # DEBUG_PRINT_ENABLED 0x02 + # DEBUG_CODE_ENABLED 0x04 + # CLEAR_MEMORY_ENABLED 0x08 + # ASSERT_BREAKPOINT_ENABLED 0x10 + # ASSERT_DEADLOOP_ENABLED 0x20 +!if $(DEBUG_ON_SERIAL_PORT) !=3D TRUE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f +!endif + + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free (pool) + # DEBUG_PAGE 0x00000020 // Alloc & Free (page) + # DEBUG_INFO 0x00000040 // Informational debug messages + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNP Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // LoadFile + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may + # // significantly impact boot performance + # DEBUG_ERROR 0x80000000 // Error +!if $(DEBUG_ON_SERIAL_PORT) =3D=3D TRUE + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|$(DEBUG_PRINT_ERROR_LEV= EL) +!endif + + # + # Optional feature to help prevent EFI memory map fragments + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob + # Values are in EFI Pages (4K). DXE Core will make sure that + # at least this much of each type of memory can be allocated + # from a single memory range. This way you only end up with + # maximum of two fragments for each type in the memory map + # (the memory used, and the free memory that was prereserved + # but not used). + # + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|600 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|400 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|1500 +!else + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|300 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|150 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|1000 +!endif + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|6000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 + + # + # Enable strict image permissions for all images. (This applies + # only to images that were built with >=3D 4 KB section alignment.) + # + gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3 + + # + # Enable NX memory protection for all non-code regions, including OEM an= d OS + # reserved ones, with the exception of LoaderData regions, of which OS l= oaders + # (i.e., GRUB) may assume that its contents are executable. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC0000000= 00007FD5 + + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 +!if $(NETWORK_TLS_ENABLE) =3D=3D TRUE + # + # The cumulative and individual VOLATILE variable size limits should be = set + # high enough for accommodating several and/or large CA certificates. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0x80000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVolatileVariableSize|0x40000 +!endif + + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"2.7" + + # + # Serial Port + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x10000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|9600 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|3686400 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|1 + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + # + # override the default values from SecurityPkg to ensure images from all= sources are verified in secure boot + # + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0= x04 +!endif + + gEfiShellPkgTokenSpaceGuid.PcdShellFileOperationSize|0x20000 + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x02 + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1 + + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 + + # + # Reference the value in default DT passed from Qemu=20 + # + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x30000000 + +[PcdsDynamicDefault.common] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3 + + # + # If TRUE, OvmfPkg/AcpiPlatformDxe will not wait for PCI + # enumeration to complete before installing ACPI tables. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE + + gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation|0x0 + + # + # Set video resolution for boot options and for text setup. + # PlatformDxe can set the former at runtime. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1280 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|800 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0 + + # + # SMBIOS entry point version + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0300 + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0 + + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0 + + # + # TPM2 support + # +!if $(TPM2_ENABLE) =3D=3D TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdTpmBaseAddress|0x0 + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x00, 0x00, 0x00, 0x00= , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2HashMask|0 +!endif + +[PcdsPatchableInModule] + # + # PCI Root Complex - ECAM + # + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciBusMin|0 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciBusMax|255 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciIoBase|0x0 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciIoSize|0x00010000 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio32Base|0x40000000 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio32Size|0x40000000 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio64Base|0x400000000 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio64Size|0x400000000 + +[PcdsDynamicHii] +!if $(TPM2_CONFIG_ENABLE) =3D=3D TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|L"TCG2_= VERSION"|gTcg2ConfigFormSetGuid|0x0|"1.3"|NV,BS + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableRev|L"TCG2_VERSION"|gTcg2C= onfigFormSetGuid|0x8|3|NV,BS +!endif + + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|5 + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +##########################################################################= ###### +[Components.common] + # + # SEC Phase modules + # + Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.inf { + + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectio= nLib/PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaC= ustomDecompressLib.inf + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + PrePiHobListPointerLib|OvmfPkg/RiscVVirt/Library/PrePiHobListPointer= Lib/PrePiHobListPointerLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/Pre= PiMemoryAllocationLib.inf + } + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32Gu= idedSectionExtractLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + } + + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + } + + # + # Architectural Protocols + # + UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + # do not use unaligned CopyMem () on the UEFI varstore NOR flash reg= ion + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + } + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificatio= nLib.inf +!if $(TPM2_ENABLE) =3D=3D TRUE + NULL|SecurityPkg/Library/DxeTpm2MeasureBootLib/DxeTpm2MeasureBootLib= .inf +!endif + } + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx= e.inf +!else + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +!endif + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf + Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashDxe.in= f + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + + # + # Status Code Routing + # + MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCod= eRouterRuntimeDxe.inf + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRun= timeDxe.inf + + # + # Silicon Driver + # + Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + UDF filesystem + virtio-fs + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + FatPkg/EnhancedFatDxe/Fat.inf + MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf { + + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + } + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Logo/LogoDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } + + # + # SCSI Bus and Disk Driver + # + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + + # + # SATA + # + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + + # + # NVME Driver + # + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + # + # SMBIOS Support + # + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + + # + # PCI support + # + UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + # + # Video support + # + OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf + + # + # USB Support + # + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # TPM2 support + # +!if $(TPM2_ENABLE) =3D=3D TRUE + SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf { + + HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCrypt= oRouterDxe.inf + Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibR= outerDxe.inf + NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf + NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf + NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256= .inf + NULL|SecurityPkg/Library/HashInstanceLibSha384/HashInstanceLibSha384= .inf + NULL|SecurityPkg/Library/HashInstanceLibSha512/HashInstanceLibSha512= .inf + NULL|SecurityPkg/Library/HashInstanceLibSm3/HashInstanceLibSm3.inf + } +!if $(TPM2_CONFIG_ENABLE) =3D=3D TRUE + SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigDxe.inf +!endif +!endif + + # + # ACPI Support + # + MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsRes= ourceTableDxe.inf + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf { + + NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf + } + + # + # Ramdisk support + # + MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + + # + # UEFI Shell + # + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman= dLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co= mmandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm= andsLib.inf +!if $(ACPIVIEW_ENABLE) =3D=3D TRUE + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewC= ommandLib.inf +!endif + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1= CommandsLib.inf +!if $(NETWORK_IP6_ENABLE) =3D=3D TRUE + NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2= CommandsLib.inf +!endif + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePar= singLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcf= gCommandLib.inf + + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } diff --git a/Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.= fdf b/Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.fdf new file mode 100755 index 00000000..caa41462 --- /dev/null +++ b/Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.fdf @@ -0,0 +1,284 @@ +## @file +# RISC-V EFI on Qemu Server Platform +# +# Copyright (c) 2024, Intel Corporation. All rights reserved.
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +!include RiscVQemuServerPlatform.fdf.inc + +##########################################################################= ###### +[FD.RISCV_SP_CODE] +BaseAddress =3D $(CODE_BASE_ADDRESS)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfF= dBaseAddress +Size =3D $(CODE_SIZE)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareF= dSize +ErasePolarity =3D 1 +BlockSize =3D $(BLOCK_SIZE) +NumBlocks =3D $(CODE_BLOCKS) + +0x00000000|$(CODE_SIZE) +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|gUefiRiscVPlatformPk= gTokenSpaceGuid.PcdRiscVDxeFvSize +FV =3D FVMAIN_COMPACT + +##########################################################################= ###### +[FD.RISCV_SP_VARS] +BaseAddress =3D $(VARS_BASE_ADDRESS) +Size =3D $(VARS_SIZE) +ErasePolarity =3D 1 +BlockSize =3D $(VARS_BLOCK_SIZE) +NumBlocks =3D $(VARS_BLOCKS) + +!include VarStore.fdf.inc +##########################################################################= ###### + +[FV.DXEFV] +BlockSize =3D 0x10000 +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +# +# DXE Phase modules +# +INF MdeModulePkg/Core/Dxe/DxeMain.inf +INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf +INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf +INF Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf + +# +# PI DXE Drivers producing Architectural Protocols (EFI Services) +# +INF UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf +INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf +INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf +INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.in= f +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootCon= figDxe.inf +!endif +INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRun= timeDxe.inf +INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.in= f +INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf +INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf +INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + +# +# Multiple Console IO support +# +INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf +INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf +INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.= inf +INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf +INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + +# RISC-V Core Drivers +INF UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf +INF Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashDxe= .inf +INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + +# +# FAT filesystem + GPT/MBR partitioning + UDF filesystem + virtio-fs +# +INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf +INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf +INF FatPkg/EnhancedFatDxe/Fat.inf +INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.in= f +INF MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf + +# +# Status Code Routing +# +INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatus= CodeRouterRuntimeDxe.inf +INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandler= RuntimeDxe.inf + +# +# UEFI Shell +# +INF ShellPkg/Application/Shell/Shell.inf + +# +# Bds +# +INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf +INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf +INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.= inf +INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf +INF MdeModulePkg/Application/UiApp/UiApp.inf + +# +# Networking stack +# +!include NetworkPkg/Network.fdf.inc + +# +# SCSI Bus and Disk Driver +# +INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf +INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + +# +# SATA +# +INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf +INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf +INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + +# +# NVME Driver +# +INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + +# +# SMBIOS Support +# +INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + +# +# ACPI Support +# +INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf +INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphics= ResourceTableDxe.inf + +# +# PCI support +# +INF UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf +INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf +INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + +# +# Video support +# +INF OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf + +# +# Usb Support +# +INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf +INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf +INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf +INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf +INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf +INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + +# +# TianoCore logo (splash screen) +# +INF MdeModulePkg/Logo/LogoDxe.inf + +# +# Ramdisk support +# +INF MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + +##########################################################################= ###### + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 27A72E80-3118-4c0c-8673-AA5B4EFA9613 + +INF Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.inf + +FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED= =3D TRUE { + SECTION FV_IMAGE =3D DXEFV + } + } + +[Rule.Common.SEC] + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED FIXED { + PE32 PE32 Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + VERSION STRING =3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE =3D $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER= ) + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depe= x + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER= ) + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depe= x + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER= ) + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depe= x + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER= ) + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER= ) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + UI STRING=3D"$(MODULE_NAME)" Optional + } diff --git a/Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.= fdf.inc b/Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.fdf= .inc new file mode 100755 index 00000000..63c601d1 --- /dev/null +++ b/Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.fdf.inc @@ -0,0 +1,42 @@ +## @file +# Definitions of Flash definition file on RISC-V Qemu Server Platform +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# Copyright (c) 2024, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +[Defines] +DEFINE BLOCK_SIZE =3D 0x1000 + +DEFINE PFLASH0_BASE =3D 0x20000000 +DEFINE PFLASH1_BASE =3D 0x22000000 + +DEFINE CODE_BASE_ADDRESS =3D $(PFLASH0_BASE) +DEFINE CODE_SIZE =3D 0x00800000 +DEFINE CODE_BLOCKS =3D 0x800 + +DEFINE VARS_BASE_ADDRESS =3D $(PFLASH1_BASE) +DEFINE VARS_SIZE =3D 0x000C0000 +DEFINE VARS_BLOCK_SIZE =3D 0x40000 +DEFINE VARS_BLOCKS =3D 0x3 + +# +# EFI Variable memory region. +# The total size of EFI Variable FD must include +# all of sub regions of EFI Variable +# +DEFINE VARS_OFFSET =3D 0x00000000 +DEFINE VARS_LIVE_SIZE =3D 0x00040000 +DEFINE VARS_FTW_WORKING_OFFSET =3D $(VARS_OFFSET) + $(VARS_LIVE_SIZE= ) +DEFINE VARS_FTW_WORKING_SIZE =3D 0x00040000 +DEFINE VARS_FTW_SPARE_OFFSET =3D $(VARS_FTW_WORKING_OFFSET) + $(VA= RS_FTW_WORKING_SIZE) +DEFINE VARS_FTW_SPARE_SIZE =3D 0x00040000 + +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency =3D 10000= 000 +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvBase =3D 0x83F= F0000 +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvSize =3D 0x000= 10000 +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress =3D $(PFL= ASH1_BASE) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize =3D $(VAR= S_SIZE) diff --git a/Platform/Qemu/RiscVQemuServerPlatform/Sec/Cpu.c b/Platform/Qem= u/RiscVQemuServerPlatform/Sec/Cpu.c new file mode 100755 index 00000000..2c16df69 --- /dev/null +++ b/Platform/Qemu/RiscVQemuServerPlatform/Sec/Cpu.c @@ -0,0 +1,33 @@ +/** @file +The library call to pass the device tree to DXE via HOB. + +Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights = reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +//// The package level header files this module uses +//// +#include + +#include +#include + +/** + Cpu Peim initialization. + +**/ +EFI_STATUS +CpuPeimInitialization ( + VOID + ) +{ + // + // for MMU type >=3D sv39 + // + BuildCpuHob (56, 32); + + return EFI_SUCCESS; +} diff --git a/Platform/Qemu/RiscVQemuServerPlatform/Sec/Memory.c b/Platform/= Qemu/RiscVQemuServerPlatform/Sec/Memory.c new file mode 100755 index 00000000..7c6d920b --- /dev/null +++ b/Platform/Qemu/RiscVQemuServerPlatform/Sec/Memory.c @@ -0,0 +1,318 @@ +/** @file + Memory Detection for Virtual Machines. + + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +Module Name: + + MemDetect.c + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +BuildMemoryTypeInformationHob ( + VOID + ); + +/** + Create memory range resource HOB using the memory base + address and size. + + @param MemoryBase Memory range base address. + @param MemorySize Memory range size. + +**/ +STATIC +VOID +AddMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +/** + Create memory range resource HOB using memory base + address and top address of the memory range. + + @param MemoryBase Memory range base address. + @param MemoryLimit Memory range size. + +**/ +STATIC +VOID +AddMemoryRangeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); +} + +/** + Publish system RAM and reserve memory regions. + +**/ +STATIC +VOID +InitializeRamRegions ( + IN EFI_PHYSICAL_ADDRESS SystemMemoryBase, + IN UINT64 SystemMemorySize + ) +{ + AddMemoryRangeHob ( + SystemMemoryBase, + SystemMemoryBase + SystemMemorySize + ); +} + +/** Get the number of cells for a given property + + @param[in] Fdt Pointer to Device Tree (DTB) + @param[in] Node Node + @param[in] Name Name of the property + + @return Number of cells. +**/ +STATIC +INT32 +GetNumCells ( + IN VOID *Fdt, + IN INT32 Node, + IN CONST CHAR8 *Name + ) +{ + CONST INT32 *Prop; + INT32 Len; + UINT32 Val; + + Prop =3D fdt_getprop (Fdt, Node, Name, &Len); + if (Prop =3D=3D NULL) { + return Len; + } + + if (Len !=3D sizeof (*Prop)) { + return -FDT_ERR_BADNCELLS; + } + + Val =3D fdt32_to_cpu (*Prop); + if (Val > FDT_MAX_NCELLS) { + return -FDT_ERR_BADNCELLS; + } + + return (INT32)Val; +} + +/** Mark reserved memory ranges in the EFI memory map + + * As per DT spec v0.4 Section 3.5.4, + * "Reserved regions with the no-map property must be listed in the + * memory map with type EfiReservedMemoryType. All other reserved + * regions must be listed with type EfiBootServicesData." + + @param FdtPointer Pointer to FDT + +**/ +STATIC +VOID +AddReservedMemoryMap ( + IN VOID *FdtPointer + ) +{ + CONST INT32 *RegProp; + INT32 Node; + INT32 SubNode; + INT32 Len; + EFI_PHYSICAL_ADDRESS Addr; + UINT64 Size; + INTN NumRsv, i; + INT32 NumAddrCells, NumSizeCells; + + NumRsv =3D fdt_num_mem_rsv (FdtPointer); + + /* Look for an existing entry and add it to the efi mem map. */ + for (i =3D 0; i < NumRsv; i++) { + if (fdt_get_mem_rsv (FdtPointer, i, &Addr, &Size) !=3D 0) { + continue; + } + + BuildMemoryAllocationHob ( + Addr, + Size, + EfiReservedMemoryType + ); + } + + /* process reserved-memory */ + Node =3D fdt_subnode_offset (FdtPointer, 0, "reserved-memory"); + if (Node >=3D 0) { + NumAddrCells =3D GetNumCells (FdtPointer, Node, "#address-cells"); + if (NumAddrCells <=3D 0) { + return; + } + + NumSizeCells =3D GetNumCells (FdtPointer, Node, "#size-cells"); + if (NumSizeCells <=3D 0) { + return; + } + + fdt_for_each_subnode (SubNode, FdtPointer, Node) { + RegProp =3D fdt_getprop (FdtPointer, SubNode, "reg", &Len); + + if ((RegProp !=3D 0) && (Len =3D=3D ((NumAddrCells + NumSizeCells) *= sizeof (INT32)))) { + Addr =3D fdt32_to_cpu (RegProp[0]); + + if (NumAddrCells > 1) { + Addr =3D (Addr << 32) | fdt32_to_cpu (RegProp[1]); + } + + RegProp +=3D NumAddrCells; + Size =3D fdt32_to_cpu (RegProp[0]); + + if (NumSizeCells > 1) { + Size =3D (Size << 32) | fdt32_to_cpu (RegProp[1]); + } + + DEBUG (( + DEBUG_INFO, + "%a: Adding Reserved Memory Addr =3D 0x%llx, Size =3D 0x%llx\n", + __func__, + Addr, + Size + )); + + if (fdt_getprop (FdtPointer, SubNode, "no-map", &Len)) { + BuildMemoryAllocationHob ( + Addr, + Size, + EfiReservedMemoryType + ); + } else { + BuildMemoryAllocationHob ( + Addr, + Size, + EfiBootServicesData + ); + } + } + } + } +} + +/** + Initialize memory hob based on the DTB information. + + @return EFI_SUCCESS The memory hob added successfully. + +**/ +EFI_STATUS +MemoryPeimInitialization ( + VOID + ) +{ + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + CONST UINT64 *RegProp; + CONST CHAR8 *Type; + UINT64 CurBase, CurSize; + INT32 Node, Prev; + INT32 Len; + VOID *FdtPointer; + + FirmwareContext =3D NULL; + GetFirmwareContextPointer (&FirmwareContext); + + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __func__)); + return EFI_UNSUPPORTED; + } + + FdtPointer =3D (VOID *)FirmwareContext->FlattenedDeviceTree; + if (FdtPointer =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __func__)); + return EFI_UNSUPPORTED; + } + + // Look for the lowest memory node + for (Prev =3D 0; ; Prev =3D Node) { + Node =3D fdt_next_node (FdtPointer, Prev, NULL); + if (Node < 0) { + break; + } + + // Check for memory node + Type =3D fdt_getprop (FdtPointer, Node, "device_type", &Len); + if (Type && (AsciiStrnCmp (Type, "memory", Len) =3D=3D 0)) { + // Get the 'reg' property of this node. For now, we will assume + // two 8 byte quantities for base and size, respectively. + RegProp =3D fdt_getprop (FdtPointer, Node, "reg", &Len); + if ((RegProp !=3D 0) && (Len =3D=3D (2 * sizeof (UINT64)))) { + CurBase =3D fdt64_to_cpu (ReadUnaligned64 (RegProp)); + CurSize =3D fdt64_to_cpu (ReadUnaligned64 (RegProp + 1)); + + DEBUG (( + DEBUG_INFO, + "%a: System RAM @ 0x%lx - 0x%lx\n", + __func__, + CurBase, + CurBase + CurSize - 1 + )); + + InitializeRamRegions ( + CurBase, + CurSize + ); + } else { + DEBUG (( + DEBUG_ERROR, + "%a: Failed to parse FDT memory node\n", + __func__ + )); + } + } + } + + AddReservedMemoryMap (FdtPointer); + + /* Make sure SEC is booting with bare mode */ + ASSERT ((RiscVGetSupervisorAddressTranslationRegister () & SATP64_MODE) = =3D=3D (SATP_MODE_OFF << SATP64_MODE_SHIFT)); + + BuildMemoryTypeInformationHob (); + + return EFI_SUCCESS; +} diff --git a/Platform/Qemu/RiscVQemuServerPlatform/Sec/Platform.c b/Platfor= m/Qemu/RiscVQemuServerPlatform/Sec/Platform.c new file mode 100755 index 00000000..47827ab7 --- /dev/null +++ b/Platform/Qemu/RiscVQemuServerPlatform/Sec/Platform.c @@ -0,0 +1,160 @@ +/** @file +The library call to pass the device tree to DXE via HOB. + +Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights = reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +//// The package level header files this module uses +//// +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Build memory map I/O range resource HOB using the + base address and size. + + @param MemoryBase Memory map I/O base. + @param MemorySize Memory map I/O size. + +**/ +STATIC +VOID +AddIoMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + /* Align to EFI_PAGE_SIZE */ + MemorySize =3D ALIGN_VALUE (MemorySize, EFI_PAGE_SIZE); + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +/** + Populate IO resources from FDT that not added to GCD by its + driver in the DXE phase. + + @param FdtBase Fdt base address + @param Compatible Compatible string + +**/ +STATIC +VOID +PopulateIoResources ( + VOID *FdtBase, + CONST CHAR8 *Compatible + ) +{ + UINT64 *Reg; + INT32 Node, LenP; + + Node =3D fdt_node_offset_by_compatible (FdtBase, -1, Compatible); + while (Node !=3D -FDT_ERR_NOTFOUND) { + Reg =3D (UINT64 *)fdt_getprop (FdtBase, Node, "reg", &LenP); + if (Reg) { + ASSERT (LenP =3D=3D (2 * sizeof (UINT64))); + AddIoMemoryBaseSizeHob (SwapBytes64 (Reg[0]), SwapBytes64 (Reg[1])); + } + + Node =3D fdt_node_offset_by_compatible (FdtBase, Node, Compatible); + } +} + +/** + @retval EFI_SUCCESS The address of FDT is passed in HOB. + EFI_UNSUPPORTED Can't locate FDT. +**/ +EFI_STATUS +EFIAPI +PlatformPeimInitialization ( + VOID + ) +{ + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + VOID *FdtPointer; + VOID *Base; + VOID *NewBase; + UINTN FdtSize; + UINTN FdtPages; + UINT64 *FdtHobData; + + FirmwareContext =3D NULL; + GetFirmwareContextPointer (&FirmwareContext); + + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __func__)); + return EFI_UNSUPPORTED; + } + + FdtPointer =3D (VOID *)FirmwareContext->FlattenedDeviceTree; + if (FdtPointer =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __func__)); + return EFI_UNSUPPORTED; + } + + DEBUG ((DEBUG_INFO, "%a: Build FDT HOB - FDT at address: 0x%x \n", __fun= c__, FdtPointer)); + Base =3D FdtPointer; + if (fdt_check_header (Base) !=3D 0) { + DEBUG ((DEBUG_ERROR, "%a: Corrupted DTB\n", __func__)); + return EFI_UNSUPPORTED; + } + + FdtSize =3D fdt_totalsize (Base); + FdtPages =3D EFI_SIZE_TO_PAGES (FdtSize); + NewBase =3D AllocatePages (FdtPages); + if (NewBase =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Could not allocate memory for DTB\n", __func= __)); + return EFI_UNSUPPORTED; + } + + fdt_open_into (Base, NewBase, EFI_PAGES_TO_SIZE (FdtPages)); + + FdtHobData =3D BuildGuidHob (&gFdtHobGuid, sizeof *FdtHobData); + if (FdtHobData =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Could not build FDT Hob\n", __func__)); + return EFI_UNSUPPORTED; + } + + *FdtHobData =3D (UINTN)NewBase; + + BuildFvHob (PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize)); + + // + // For Variable FD + // + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + PcdGet32 (PcdVariableFdBaseAddress), + PcdGet32 (PcdVariableFdSize) + ); + + PopulateIoResources (Base, "ns16550a"); + PopulateIoResources (Base, "qemu,fw-cfg-mmio"); + PopulateIoResources (Base, "virtio,mmio"); + + return EFI_SUCCESS; +} diff --git a/Platform/Qemu/RiscVQemuServerPlatform/Sec/SecEntry.S b/Platfor= m/Qemu/RiscVQemuServerPlatform/Sec/SecEntry.S new file mode 100755 index 00000000..14f6b4d0 --- /dev/null +++ b/Platform/Qemu/RiscVQemuServerPlatform/Sec/SecEntry.S @@ -0,0 +1,19 @@ +/* + Copyright (c) 2022 Ventana Micro Systems Inc. + Copyright (c) 2024, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + */ + +#include "SecMain.h" + +ASM_FUNC (_ModuleEntryPoint) + /* Use Temp memory as the stack for calling to C code */ + li a4, FixedPcdGet32 (PcdRiscVSecFvBase) + li a5, FixedPcdGet32 (PcdRiscVSecFvSize) + + /* Use Temp memory as the stack for calling to C code */ + add sp, a4, a5 + + call SecStartup diff --git a/Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.c b/Platform= /Qemu/RiscVQemuServerPlatform/Sec/SecMain.c new file mode 100755 index 00000000..cb53a71a --- /dev/null +++ b/Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.c @@ -0,0 +1,110 @@ +/** @file + RISC-V SEC phase module for Qemu Virt. + + Copyright (c) 2008 - 2024, Intel Corporation. All rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SecMain.h" + +STATIC +EFI_STATUS +EFIAPI +SecInitializePlatform ( + VOID + ) +{ + EFI_STATUS Status; + + MemoryPeimInitialization (); + + CpuPeimInitialization (); + + // Set the Boot Mode + SetBootMode (BOOT_WITH_FULL_CONFIGURATION); + + Status =3D PlatformPeimInitialization (); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +/** + + Entry point to the C language phase of SEC. After the SEC assembly + code has initialized some temporary memory and set up the stack, + the control is transferred to this function. + + + @param[in] BootHartId Hardware thread ID of boot hart. + @param[in] DeviceTreeAddress Pointer to Device Tree (DTB) +**/ +VOID +NORETURN +EFIAPI +SecStartup ( + IN UINTN BootHartId, + IN VOID *DeviceTreeAddress + ) +{ + EFI_HOB_HANDOFF_INFO_TABLE *HobList; + EFI_RISCV_FIRMWARE_CONTEXT FirmwareContext; + EFI_STATUS Status; + UINT64 UefiMemoryBase; + UINT64 StackBase; + UINT32 StackSize; + + SerialPortInitialize (); + + // + // Report Status Code to indicate entering SEC core + // + DEBUG (( + DEBUG_INFO, + "%a() BootHartId: 0x%x, DeviceTreeAddress=3D0x%x\n", + __func__, + BootHartId, + DeviceTreeAddress + )); + + FirmwareContext.BootHartId =3D BootHartId; + FirmwareContext.FlattenedDeviceTree =3D (UINT64)DeviceTreeAddress; + SetFirmwareContextPointer (&FirmwareContext); + + StackBase =3D (UINT64)FixedPcdGet32 (PcdRiscVSecFvBase); + StackSize =3D FixedPcdGet32 (PcdRiscVSecFvSize); + UefiMemoryBase =3D StackBase + StackSize - SIZE_32MB; + + // Declare the PI/UEFI memory region + HobList =3D HobConstructor ( + (VOID *)UefiMemoryBase, + SIZE_32MB, + (VOID *)UefiMemoryBase, + (VOID *)StackBase // The top of the UEFI Memory is reserved = for the stacks + ); + PrePeiSetHobList (HobList); + + SecInitializePlatform (); + + BuildStackHob (StackBase, StackSize); + + // + // Process all libraries constructor function linked to SecMain. + // + ProcessLibraryConstructorList (); + + // Assume the FV that contains the SEC (our code) also contains a compre= ssed FV. + Status =3D DecompressFirstFv (); + ASSERT_EFI_ERROR (Status); + + // Load the DXE Core and transfer control to it + Status =3D LoadDxeCoreFromFv (NULL, 0); + ASSERT_EFI_ERROR (Status); + // + // Should not come here. + // + UNREACHABLE (); +} diff --git a/Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.h b/Platform= /Qemu/RiscVQemuServerPlatform/Sec/SecMain.h new file mode 100755 index 00000000..29da93c8 --- /dev/null +++ b/Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.h @@ -0,0 +1,104 @@ +/** @file + Master header file for SecCore. + + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ Copyright (c) 2024, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SEC_MAIN_H_ +#define SEC_MAIN_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Entry point to the C language phase of SEC. After the SEC assembly + code has initialized some temporary memory and set up the stack, + the control is transferred to this function. + + @param SizeOfRam Size of the temporary memory available for us= e. + @param TempRamBase Base address of temporary ram + @param BootFirmwareVolume Base address of the Boot Firmware Volume. +**/ +VOID +NORETURN +EFIAPI +SecStartup ( + IN UINTN BootHartId, + IN VOID *DeviceTreeAddress + ); + +/** + Auto-generated function that calls the library constructors for all of t= he module's + dependent libraries. This function must be called by the SEC Core once = a stack has + been established. + +**/ +VOID +EFIAPI +ProcessLibraryConstructorList ( + VOID + ); + +/** + Perform Platform PEIM initialization. + + @return EFI_SUCCESS The platform initialized successfully. + @retval Others - As the error code indicates + +**/ +EFI_STATUS +EFIAPI +PlatformPeimInitialization ( + VOID + ); + +/** + Perform Memory PEIM initialization. + + @return EFI_SUCCESS The platform initialized successfully. + @retval Others - As the error code indicates + +**/ +EFI_STATUS +EFIAPI +MemoryPeimInitialization ( + VOID + ); + +/** + Perform CPU PEIM initialization. + + @return EFI_SUCCESS The platform initialized successfully. + @retval Others - As the error code indicates + +**/ +EFI_STATUS +EFIAPI +CpuPeimInitialization ( + VOID + ); + +#endif diff --git a/Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.inf b/Platfo= rm/Qemu/RiscVQemuServerPlatform/Sec/SecMain.inf new file mode 100755 index 00000000..b40a095a --- /dev/null +++ b/Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.inf @@ -0,0 +1,67 @@ +## @file +# SEC Driver for RISC-V +# +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D SecMainRiscV64 + FILE_GUID =3D 80D22D3C-81EC-44B2-A55C-242C21BF9539 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SecMain + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + SecEntry.S + SecMain.c + SecMain.h + Cpu.c + Memory.c + Platform.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + PcdLib + IoLib + PeCoffLib + LzmaDecompressLib + RiscVSbiLib + PrePiLib + FdtLib + MemoryAllocationLib + HobLib + SerialPortLib + +[Ppis] + gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED + gEfiTemporaryRamDonePpiGuid ## PRODUCES + +[Pcd] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvBase + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize + +[Guids] + gFdtHobGuid diff --git a/Platform/Qemu/RiscVQemuServerPlatform/VarStore.fdf.inc b/Platf= orm/Qemu/RiscVQemuServerPlatform/VarStore.fdf.inc new file mode 100755 index 00000000..07fe3caf --- /dev/null +++ b/Platform/Qemu/RiscVQemuServerPlatform/VarStore.fdf.inc @@ -0,0 +1,72 @@ +## @file +# FDF include file with Layout Regions that define an empty variable stor= e. +# +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (C) 2014, Red Hat, Inc. +# Copyright (c) 2006 - 2024, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +$(VARS_OFFSET)|$(VARS_LIVE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +# +# NV_VARIABLE_STORE +# +DATA =3D { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid =3D + # { 0xFFF12B8D, 0x7696, 0x4C8B, + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0xC0000 + 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, + # Signature "_FVH" # Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x28, 0x09, 0x00, 0x00, 0x00, 0x02, + # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block + 0x3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, + # Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER + # It is compatible with SECURE_BOOT_ENABLE =3D=3D FALSE as well. + # Signature: gEfiAuthenticatedVariableGuid =3D + # { 0xaaf32c78, 0x947b, 0x439a, + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, + # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariabl= eSize) - + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x3FFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xFF, 0x03, 0x00, + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(VARS_FTW_WORKING_OFFSET)|$(VARS_FTW_WORKING_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +# +#NV_FTW_WORK +# +DATA =3D { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved + 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(VARS_FTW_SPARE_OFFSET)|$(VARS_FTW_SPARE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +# +#NV_FTW_SPARE diff --git a/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorF= lash.c b/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlash= .c new file mode 100755 index 00000000..e6aaed27 --- /dev/null +++ b/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlash.c @@ -0,0 +1,742 @@ +/** @file NorFlash.c + + Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.
+ Copyright (c) 2020, Linaro, Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "VirtNorFlash.h" + +// +// Global variable declarations +// +extern NOR_FLASH_INSTANCE **mNorFlashInstances; +extern UINT32 mNorFlashDeviceCount; + +UINT32 +NorFlashReadStatusRegister ( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN SR_Address + ) +{ + // Prepare to read the status register + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_READ_STATUS_RE= GISTER); + return MmioRead32 (Instance->DeviceBaseAddress); +} + +STATIC +BOOLEAN +NorFlashBlockIsLocked ( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN BlockAddress + ) +{ + UINT32 LockStatus; + + // Send command for reading device id + SEND_NOR_COMMAND (BlockAddress, 2, P30_CMD_READ_DEVICE_ID); + + // Read block lock status + LockStatus =3D MmioRead32 (CREATE_NOR_ADDRESS (BlockAddress, 2)); + + // Decode block lock status + LockStatus =3D FOLD_32BIT_INTO_16BIT (LockStatus); + + if ((LockStatus & 0x2) !=3D 0) { + DEBUG ((DEBUG_ERROR, "NorFlashBlockIsLocked: WARNING: Block LOCKED DOW= N\n")); + } + + return ((LockStatus & 0x1) !=3D 0); +} + +STATIC +EFI_STATUS +NorFlashUnlockSingleBlock ( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN BlockAddress + ) +{ + UINT32 LockStatus; + + // Raise the Task Priority Level to TPL_NOTIFY to serialise all its oper= ations + // and to protect shared data structures. + + // Request a lock setup + SEND_NOR_COMMAND (BlockAddress, 0, P30_CMD_LOCK_BLOCK_SETUP); + + // Request an unlock + SEND_NOR_COMMAND (BlockAddress, 0, P30_CMD_UNLOCK_BLOCK); + + // Wait until the status register gives us the all clear + do { + LockStatus =3D NorFlashReadStatusRegister (Instance, BlockAddress); + } while ((LockStatus & P30_SR_BIT_WRITE) !=3D P30_SR_BIT_WRITE); + + // Put device back into Read Array mode + SEND_NOR_COMMAND (BlockAddress, 0, P30_CMD_READ_ARRAY); + + DEBUG ((DEBUG_BLKIO, "UnlockSingleBlock: BlockAddress=3D0x%08x\n", Block= Address)); + + return EFI_SUCCESS; +} + +EFI_STATUS +NorFlashUnlockSingleBlockIfNecessary ( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN BlockAddress + ) +{ + EFI_STATUS Status; + + Status =3D EFI_SUCCESS; + + if (NorFlashBlockIsLocked (Instance, BlockAddress)) { + Status =3D NorFlashUnlockSingleBlock (Instance, BlockAddress); + } + + return Status; +} + +/** + * The following function presumes that the block has already been unlocke= d. + **/ +EFI_STATUS +NorFlashEraseSingleBlock ( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN BlockAddress + ) +{ + EFI_STATUS Status; + UINT32 StatusRegister; + + Status =3D EFI_SUCCESS; + + // Request a block erase and then confirm it + SEND_NOR_COMMAND (BlockAddress, 0, P30_CMD_BLOCK_ERASE_SETUP); + SEND_NOR_COMMAND (BlockAddress, 0, P30_CMD_BLOCK_ERASE_CONFIRM); + + // Wait until the status register gives us the all clear + do { + StatusRegister =3D NorFlashReadStatusRegister (Instance, BlockAddress)= ; + } while ((StatusRegister & P30_SR_BIT_WRITE) !=3D P30_SR_BIT_WRITE); + + if (StatusRegister & P30_SR_BIT_VPP) { + DEBUG ((DEBUG_ERROR, "EraseSingleBlock(BlockAddress=3D0x%08x: VPP Rang= e Error\n", BlockAddress)); + Status =3D EFI_DEVICE_ERROR; + } + + if ((StatusRegister & (P30_SR_BIT_ERASE | P30_SR_BIT_PROGRAM)) =3D=3D (P= 30_SR_BIT_ERASE | P30_SR_BIT_PROGRAM)) { + DEBUG ((DEBUG_ERROR, "EraseSingleBlock(BlockAddress=3D0x%08x: Command = Sequence Error\n", BlockAddress)); + Status =3D EFI_DEVICE_ERROR; + } + + if (StatusRegister & P30_SR_BIT_ERASE) { + DEBUG ((DEBUG_ERROR, "EraseSingleBlock(BlockAddress=3D0x%08x: Block Er= ase Error StatusRegister:0x%X\n", BlockAddress, StatusRegister)); + Status =3D EFI_DEVICE_ERROR; + } + + if (StatusRegister & P30_SR_BIT_BLOCK_LOCKED) { + // The debug level message has been reduced because a device lock migh= t happen. In this case we just retry it ... + DEBUG ((DEBUG_INFO, "EraseSingleBlock(BlockAddress=3D0x%08x: Block Loc= ked Error\n", BlockAddress)); + Status =3D EFI_WRITE_PROTECTED; + } + + if (EFI_ERROR (Status)) { + // Clear the Status Register + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_CLEAR_STATUS= _REGISTER); + } + + // Put device back into Read Array mode + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_READ_ARRAY); + + return Status; +} + +EFI_STATUS +NorFlashWriteSingleWord ( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN WordAddress, + IN UINT32 WriteData + ) +{ + EFI_STATUS Status; + UINT32 StatusRegister; + + Status =3D EFI_SUCCESS; + + // Request a write single word command + SEND_NOR_COMMAND (WordAddress, 0, P30_CMD_WORD_PROGRAM_SETUP); + + // Store the word into NOR Flash; + MmioWrite32 (WordAddress, WriteData); + + // Wait for the write to complete and then check for any errors; i.e. ch= eck the Status Register + do { + // Prepare to read the status register + StatusRegister =3D NorFlashReadStatusRegister (Instance, WordAddress); + // The chip is busy while the WRITE bit is not asserted + } while ((StatusRegister & P30_SR_BIT_WRITE) !=3D P30_SR_BIT_WRITE); + + // Perform a full status check: + // Mask the relevant bits of Status Register. + // Everything should be zero, if not, we have a problem + + if (StatusRegister & P30_SR_BIT_VPP) { + DEBUG ((DEBUG_ERROR, "NorFlashWriteSingleWord(WordAddress:0x%X): VPP R= ange Error\n", WordAddress)); + Status =3D EFI_DEVICE_ERROR; + } + + if (StatusRegister & P30_SR_BIT_PROGRAM) { + DEBUG ((DEBUG_ERROR, "NorFlashWriteSingleWord(WordAddress:0x%X): Progr= am Error\n", WordAddress)); + Status =3D EFI_DEVICE_ERROR; + } + + if (StatusRegister & P30_SR_BIT_BLOCK_LOCKED) { + DEBUG ((DEBUG_ERROR, "NorFlashWriteSingleWord(WordAddress:0x%X): Devic= e Protect Error\n", WordAddress)); + Status =3D EFI_DEVICE_ERROR; + } + + if (!EFI_ERROR (Status)) { + // Clear the Status Register + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_CLEAR_STATUS= _REGISTER); + } + + return Status; +} + +/* + * Writes data to the NOR Flash using the Buffered Programming method. + * + * The maximum size of the on-chip buffer is 32-words, because of hardware= restrictions. + * Therefore this function will only handle buffers up to 32 words or 128 = bytes. + * To deal with larger buffers, call this function again. + * + * This function presumes that both the TargetAddress and the TargetAddres= s+BufferSize + * exist entirely within the NOR Flash. Therefore these conditions will no= t be checked here. + * + * In buffered programming, if the target address not at the beginning of = a 32-bit word boundary, + * then programming time is doubled and power consumption is increased. + * Therefore, it is a requirement to align buffer writes to 32-bit word bo= undaries. + * i.e. the last 4 bits of the target start address must be zero: 0x......= 00 + */ +EFI_STATUS +NorFlashWriteBuffer ( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN TargetAddress, + IN UINTN BufferSizeInBytes, + IN UINT32 *Buffer + ) +{ + EFI_STATUS Status; + UINTN BufferSizeInWords; + UINTN Count; + volatile UINT32 *Data; + UINTN WaitForBuffer; + BOOLEAN BufferAvailable; + UINT32 StatusRegister; + + WaitForBuffer =3D MAX_BUFFERED_PROG_ITERATIONS; + BufferAvailable =3D FALSE; + + // Check that the target address does not cross a 32-word boundary. + if ((TargetAddress & BOUNDARY_OF_32_WORDS) !=3D 0) { + return EFI_INVALID_PARAMETER; + } + + // Check there are some data to program + if (BufferSizeInBytes =3D=3D 0) { + return EFI_BUFFER_TOO_SMALL; + } + + // Check that the buffer size does not exceed the maximum hardware buffe= r size on chip. + if (BufferSizeInBytes > P30_MAX_BUFFER_SIZE_IN_BYTES) { + return EFI_BAD_BUFFER_SIZE; + } + + // Check that the buffer size is a multiple of 32-bit words + if ((BufferSizeInBytes % 4) !=3D 0) { + return EFI_BAD_BUFFER_SIZE; + } + + // Pre-programming conditions checked, now start the algorithm. + + // Prepare the data destination address + Data =3D (UINT32 *)TargetAddress; + + // Check the availability of the buffer + do { + // Issue the Buffered Program Setup command + SEND_NOR_COMMAND (TargetAddress, 0, P30_CMD_BUFFERED_PROGRAM_SETUP); + + // Read back the status register bit#7 from the same address + if (((*Data) & P30_SR_BIT_WRITE) =3D=3D P30_SR_BIT_WRITE) { + BufferAvailable =3D TRUE; + } + + // Update the loop counter + WaitForBuffer--; + } while ((WaitForBuffer > 0) && (BufferAvailable =3D=3D FALSE)); + + // The buffer was not available for writing + if (WaitForBuffer =3D=3D 0) { + return EFI_DEVICE_ERROR; + } + + // From now on we work in 32-bit words + BufferSizeInWords =3D BufferSizeInBytes / (UINTN)4; + + // Write the word count, which is (buffer_size_in_words - 1), + // because word count 0 means one word. + SEND_NOR_COMMAND (TargetAddress, 0, (BufferSizeInWords - 1)); + + // Write the data to the NOR Flash, advancing each address by 4 bytes + for (Count =3D 0; Count < BufferSizeInWords; Count++, Data++, Buffer++) = { + MmioWrite32 ((UINTN)Data, *Buffer); + } + + // Issue the Buffered Program Confirm command, to start the programming = operation + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_BUFFERED_PROGR= AM_CONFIRM); + + // Wait for the write to complete and then check for any errors; i.e. ch= eck the Status Register + do { + StatusRegister =3D NorFlashReadStatusRegister (Instance, TargetAddress= ); + // The chip is busy while the WRITE bit is not asserted + } while ((StatusRegister & P30_SR_BIT_WRITE) !=3D P30_SR_BIT_WRITE); + + // Perform a full status check: + // Mask the relevant bits of Status Register. + // Everything should be zero, if not, we have a problem + + Status =3D EFI_SUCCESS; + + if (StatusRegister & P30_SR_BIT_VPP) { + DEBUG ((DEBUG_ERROR, "NorFlashWriteBuffer(TargetAddress:0x%X): VPP Ran= ge Error\n", TargetAddress)); + Status =3D EFI_DEVICE_ERROR; + } + + if (StatusRegister & P30_SR_BIT_PROGRAM) { + DEBUG ((DEBUG_ERROR, "NorFlashWriteBuffer(TargetAddress:0x%X): Program= Error\n", TargetAddress)); + Status =3D EFI_DEVICE_ERROR; + } + + if (StatusRegister & P30_SR_BIT_BLOCK_LOCKED) { + DEBUG ((DEBUG_ERROR, "NorFlashWriteBuffer(TargetAddress:0x%X): Device = Protect Error\n", TargetAddress)); + Status =3D EFI_DEVICE_ERROR; + } + + if (!EFI_ERROR (Status)) { + // Clear the Status Register + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_CLEAR_STATUS= _REGISTER); + } + + return Status; +} + +EFI_STATUS +NorFlashWriteBlocks ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN BufferSizeInBytes, + IN VOID *Buffer + ) +{ + UINT32 *pWriteBuffer; + EFI_STATUS Status; + EFI_LBA CurrentBlock; + UINT32 BlockSizeInWords; + UINT32 NumBlocks; + UINT32 BlockCount; + + Status =3D EFI_SUCCESS; + + // The buffer must be valid + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // We must have some bytes to read + DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: BufferSizeInBytes=3D0x%x\n", = BufferSizeInBytes)); + if (BufferSizeInBytes =3D=3D 0) { + return EFI_BAD_BUFFER_SIZE; + } + + // The size of the buffer must be a multiple of the block size + DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: BlockSize in bytes =3D0x%x\n"= , Instance->BlockSize)); + if ((BufferSizeInBytes % Instance->BlockSize) !=3D 0) { + return EFI_BAD_BUFFER_SIZE; + } + + // All blocks must be within the device + NumBlocks =3D ((UINT32)BufferSizeInBytes) / Instance->BlockSize; + + DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: NumBlocks=3D%d, LastBlock=3D%= ld, Lba=3D%ld.\n", NumBlocks, Instance->LastBlock, Lba)); + + if ((Lba + NumBlocks) > (Instance->LastBlock + 1)) { + DEBUG ((DEBUG_ERROR, "NorFlashWriteBlocks: ERROR - Write will exceed l= ast block.\n")); + return EFI_INVALID_PARAMETER; + } + + BlockSizeInWords =3D Instance->BlockSize / 4; + + // Because the target *Buffer is a pointer to VOID, we must put all the = data into a pointer + // to a proper data type, so use *ReadBuffer + pWriteBuffer =3D (UINT32 *)Buffer; + + CurrentBlock =3D Lba; + for (BlockCount =3D 0; BlockCount < NumBlocks; BlockCount++, CurrentBloc= k++, pWriteBuffer =3D pWriteBuffer + BlockSizeInWords) { + DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: Writing block #%d\n", (UINT= N)CurrentBlock)); + + Status =3D NorFlashWriteFullBlock (Instance, CurrentBlock, pWriteBuffe= r, BlockSizeInWords); + + if (EFI_ERROR (Status)) { + break; + } + } + + DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: Exit Status =3D \"%r\".\n", S= tatus)); + return Status; +} + +EFI_STATUS +NorFlashReadBlocks ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN BufferSizeInBytes, + OUT VOID *Buffer + ) +{ + UINT32 NumBlocks; + UINTN StartAddress; + + DEBUG (( + DEBUG_BLKIO, + "NorFlashReadBlocks: BufferSize=3D0x%xB BlockSize=3D0x%xB LastBlock=3D= %ld, Lba=3D%ld.\n", + BufferSizeInBytes, + Instance->BlockSize, + Instance->LastBlock, + Lba + )); + + // The buffer must be valid + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // Return if we have not any byte to read + if (BufferSizeInBytes =3D=3D 0) { + return EFI_SUCCESS; + } + + // The size of the buffer must be a multiple of the block size + if ((BufferSizeInBytes % Instance->BlockSize) !=3D 0) { + return EFI_BAD_BUFFER_SIZE; + } + + // All blocks must be within the device + NumBlocks =3D ((UINT32)BufferSizeInBytes) / Instance->BlockSize; + + if ((Lba + NumBlocks) > (Instance->LastBlock + 1)) { + DEBUG ((DEBUG_ERROR, "NorFlashReadBlocks: ERROR - Read will exceed las= t block\n")); + return EFI_INVALID_PARAMETER; + } + + // Get the address to start reading from + StartAddress =3D GET_NOR_BLOCK_ADDRESS ( + Instance->RegionBaseAddress, + Lba, + Instance->BlockSize + ); + + // Put the device into Read Array mode + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_READ_ARRAY); + + // Readout the data + CopyMem (Buffer, (VOID *)StartAddress, BufferSizeInBytes); + + return EFI_SUCCESS; +} + +EFI_STATUS +NorFlashRead ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN Offset, + IN UINTN BufferSizeInBytes, + OUT VOID *Buffer + ) +{ + UINTN StartAddress; + + // The buffer must be valid + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // Return if we have not any byte to read + if (BufferSizeInBytes =3D=3D 0) { + return EFI_SUCCESS; + } + + if (((Lba * Instance->BlockSize) + Offset + BufferSizeInBytes) > Instanc= e->Size) { + DEBUG ((DEBUG_ERROR, "NorFlashRead: ERROR - Read will exceed device si= ze.\n")); + return EFI_INVALID_PARAMETER; + } + + // Get the address to start reading from + StartAddress =3D GET_NOR_BLOCK_ADDRESS ( + Instance->RegionBaseAddress, + Lba, + Instance->BlockSize + ); + + // Put the device into Read Array mode + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_READ_ARRAY); + + // Readout the data + CopyMem (Buffer, (VOID *)(StartAddress + Offset), BufferSizeInBytes); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +NorFlashWriteSingleBlockWithErase ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + + // Read NOR Flash data into shadow buffer + Status =3D NorFlashReadBlocks (Instance, Lba, Instance->BlockSize, Insta= nce->ShadowBuffer); + if (EFI_ERROR (Status)) { + // Return one of the pre-approved error statuses + return EFI_DEVICE_ERROR; + } + + // Put the data at the appropriate location inside the buffer area + CopyMem ((VOID *)((UINTN)Instance->ShadowBuffer + Offset), Buffer, *NumB= ytes); + + // Write the modified buffer back to the NorFlash + Status =3D NorFlashWriteBlocks (Instance, Lba, Instance->BlockSize, Inst= ance->ShadowBuffer); + if (EFI_ERROR (Status)) { + // Return one of the pre-approved error statuses + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + +/* + Write a full or portion of a block. It must not span block boundaries; t= hat is, + Offset + *NumBytes <=3D Instance->BlockSize. +*/ +EFI_STATUS +NorFlashWriteSingleBlock ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + UINTN CurOffset; + UINTN BlockSize; + UINTN BlockAddress; + UINT8 *OrigData; + UINTN Start, End; + UINT32 Index, Count; + + DEBUG ((DEBUG_BLKIO, "NorFlashWriteSingleBlock(Parameters: Lba=3D%ld, Of= fset=3D0x%x, *NumBytes=3D0x%x, Buffer @ 0x%08x)\n", Lba, Offset, *NumBytes,= Buffer)); + + // Check we did get some memory. Buffer is BlockSize. + if (Instance->ShadowBuffer =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "FvbWrite: ERROR - Buffer not ready\n")); + return EFI_DEVICE_ERROR; + } + + // Cache the block size to avoid de-referencing pointers all the time + BlockSize =3D Instance->BlockSize; + + // The write must not span block boundaries. + // We need to check each variable individually because adding two large = values together overflows. + if ((Offset >=3D BlockSize) || + (*NumBytes > BlockSize) || + ((Offset + *NumBytes) > BlockSize)) + { + DEBUG ((DEBUG_ERROR, "NorFlashWriteSingleBlock: ERROR - EFI_BAD_BUFFER= _SIZE: (Offset=3D0x%x + NumBytes=3D0x%x) > BlockSize=3D0x%x\n", Offset, *Nu= mBytes, BlockSize)); + return EFI_BAD_BUFFER_SIZE; + } + + // We must have some bytes to write + if (*NumBytes =3D=3D 0) { + DEBUG ((DEBUG_ERROR, "NorFlashWriteSingleBlock: ERROR - EFI_BAD_BUFFER= _SIZE: (Offset=3D0x%x + NumBytes=3D0x%x) > BlockSize=3D0x%x\n", Offset, *Nu= mBytes, BlockSize)); + return EFI_BAD_BUFFER_SIZE; + } + + // Pick 4 * P30_MAX_BUFFER_SIZE_IN_BYTES (=3D=3D 512 bytes) as a good + // start for word operations as opposed to erasing the block and + // writing the data regardless if an erase is really needed. + // + // Many NV variable updates are small enough for a a single + // P30_MAX_BUFFER_SIZE_IN_BYTES block write. In case the update is + // larger than a single block, or the update crosses a + // P30_MAX_BUFFER_SIZE_IN_BYTES boundary (as shown in the diagram + // below), or both, we might have to write two or more blocks. + // + // 0 128 256 + // [----------------|----------------] + // ^ ^ ^ ^ + // | | | | + // | | | End, the next "word" boundary bey= ond + // | | | the (logical) update + // | | | + // | | (Offset & BOUNDARY_OF_32_WORDS) + NumBytes; + // | | i.e., the relative offset inside (or just past) + // | | the *double-word* such that it is the + // | | *exclusive* end of the (logical) update. + // | | + // | Offset & BOUNDARY_OF_32_WORDS; i.e., Offset within the "= word"; + // | this is where the (logical) update is supposed to start + // | + // Start =3D Offset & ~BOUNDARY_OF_32_WORDS; i.e., Offset truncated t= o "word" boundary + + Start =3D Offset & ~BOUNDARY_OF_32_WORDS; + End =3D ALIGN_VALUE (Offset + *NumBytes, P30_MAX_BUFFER_SIZE_IN_BYTES)= ; + + if ((End - Start) <=3D (4 * P30_MAX_BUFFER_SIZE_IN_BYTES)) { + // Check to see if we need to erase before programming the data into N= OR. + // If the destination bits are only changing from 1s to 0s we can just= write. + // After a block is erased all bits in the block is set to 1. + // If any byte requires us to erase we just give up and rewrite all of= it. + + // Read the old version of the data into the shadow buffer + Status =3D NorFlashRead ( + Instance, + Lba, + Start, + End - Start, + Instance->ShadowBuffer + ); + if (EFI_ERROR (Status)) { + return EFI_DEVICE_ERROR; + } + + // Make OrigData point to the start of the old version of the data ins= ide + // the word aligned buffer + OrigData =3D Instance->ShadowBuffer + (Offset & BOUNDARY_OF_32_WORDS); + + // Update the buffer containing the old version of the data with the n= ew + // contents, while checking whether the old version had any bits clear= ed + // that we want to set. In that case, we will need to erase the block = first. + for (CurOffset =3D 0; CurOffset < *NumBytes; CurOffset++) { + if (~(UINT32)OrigData[CurOffset] & (UINT32)Buffer[CurOffset]) { + Status =3D NorFlashWriteSingleBlockWithErase ( + Instance, + Lba, + Offset, + NumBytes, + Buffer + ); + return Status; + } + + OrigData[CurOffset] =3D Buffer[CurOffset]; + } + + // + // Write the updated buffer to NOR. + // + BlockAddress =3D GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, L= ba, BlockSize); + + // Unlock the block if we have to + Status =3D NorFlashUnlockSingleBlockIfNecessary (Instance, BlockAddres= s); + if (EFI_ERROR (Status)) { + goto Exit; + } + + Count =3D (End - Start) / P30_MAX_BUFFER_SIZE_IN_BYTES; + for (Index =3D 0; Index < Count; Index++) { + Status =3D NorFlashWriteBuffer ( + Instance, + BlockAddress + Start + Index * P30_MAX_BUFFER_SIZE_IN_BYT= ES, + P30_MAX_BUFFER_SIZE_IN_BYTES, + Instance->ShadowBuffer + Index * P30_MAX_BUFFER_SIZE_IN_B= YTES + ); + if (EFI_ERROR (Status)) { + goto Exit; + } + } + } else { + Status =3D NorFlashWriteSingleBlockWithErase ( + Instance, + Lba, + Offset, + NumBytes, + Buffer + ); + return Status; + } + +Exit: + // Put device back into Read Array mode + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_READ_ARRAY); + + return Status; +} + +EFI_STATUS +NorFlashReset ( + IN NOR_FLASH_INSTANCE *Instance + ) +{ + // As there is no specific RESET to perform, ensure that the devices is = in the default Read Array mode + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_READ_ARRAY); + return EFI_SUCCESS; +} + +/** + Fixup internal data so that EFI can be call in virtual mode. + Call the passed in Child Notify event and convert any pointers in + lib to virtual mode. + + @param[in] Event The Event that is being processed + @param[in] Context Event Context +**/ +VOID +EFIAPI +NorFlashVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + UINTN Index; + + for (Index =3D 0; Index < mNorFlashDeviceCount; Index++) { + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->DeviceBas= eAddress); + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->RegionBas= eAddress); + + // Convert Fvb + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->FvbProtoc= ol.EraseBlocks); + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->FvbProtoc= ol.GetAttributes); + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->FvbProtoc= ol.GetBlockSize); + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->FvbProtoc= ol.GetPhysicalAddress); + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->FvbProtoc= ol.Read); + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->FvbProtoc= ol.SetAttributes); + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->FvbProtoc= ol.Write); + + if (mNorFlashInstances[Index]->ShadowBuffer !=3D NULL) { + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->ShadowB= uffer); + } + } + + return; +} diff --git a/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorF= lash.h b/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlash= .h new file mode 100755 index 00000000..455eafac --- /dev/null +++ b/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlash.h @@ -0,0 +1,345 @@ +/** @file NorFlash.h + + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __VIRT_NOR_FLASH__ +#define __VIRT_NOR_FLASH__ + +#include +#include + +#include + +#include + +#include +#include +#include +#include +#include + +#define NOR_FLASH_ERASE_RETRY 10 + +// Device access macros +// These are necessary because we use 2 x 16bit parts to make up 32bit dat= a + +#define HIGH_16_BITS 0xFFFF0000 +#define LOW_16_BITS 0x0000FFFF +#define LOW_8_BITS 0x000000FF + +#define FOLD_32BIT_INTO_16BIT(value) ( ( value >> 16 ) | ( value & LOW_16= _BITS ) ) + +#define GET_LOW_BYTE(value) ( value & LOW_8_BITS ) +#define GET_HIGH_BYTE(value) ( GET_LOW_BYTE( value >> 16 ) ) + +// Each command must be sent simultaneously to both chips, +// i.e. at the lower 16 bits AND at the higher 16 bits +#define CREATE_NOR_ADDRESS(BaseAddr, OffsetAddr) ((BaseAddr) + ((Off= setAddr) << 2)) +#define CREATE_DUAL_CMD(Cmd) ( ( Cmd << 16) | ( = Cmd & LOW_16_BITS) ) +#define SEND_NOR_COMMAND(BaseAddr, Offset, Cmd) MmioWrite32 (CREATE= _NOR_ADDRESS(BaseAddr,Offset), CREATE_DUAL_CMD(Cmd)) +#define GET_NOR_BLOCK_ADDRESS(BaseAddr, Lba, LbaSize) ( BaseAddr + (UINTN= )((Lba) * LbaSize) ) + +// Status Register Bits +#define P30_SR_BIT_WRITE (BIT7 << 16 | BIT7) +#define P30_SR_BIT_ERASE_SUSPEND (BIT6 << 16 | BIT6) +#define P30_SR_BIT_ERASE (BIT5 << 16 | BIT5) +#define P30_SR_BIT_PROGRAM (BIT4 << 16 | BIT4) +#define P30_SR_BIT_VPP (BIT3 << 16 | BIT3) +#define P30_SR_BIT_PROGRAM_SUSPEND (BIT2 << 16 | BIT2) +#define P30_SR_BIT_BLOCK_LOCKED (BIT1 << 16 | BIT1) +#define P30_SR_BIT_BEFP (BIT0 << 16 | BIT0) + +// Device Commands for Intel StrataFlash(R) Embedded Memory (P30) Family + +// On chip buffer size for buffered programming operations +// There are 2 chips, each chip can buffer up to 32 (16-bit)words, and eac= h word is 2 bytes. +// Therefore the total size of the buffer is 2 x 32 x 2 =3D 128 bytes +#define P30_MAX_BUFFER_SIZE_IN_BYTES ((UINTN)128) +#define P30_MAX_BUFFER_SIZE_IN_WORDS (P30_MAX_BUFFER_SIZE_IN_BYTES/((UINT= N)4)) +#define MAX_BUFFERED_PROG_ITERATIONS 10000000 +#define BOUNDARY_OF_32_WORDS ((UINTN)0x7F) + +// CFI Addresses +#define P30_CFI_ADDR_QUERY_UNIQUE_QRY 0x10 +#define P30_CFI_ADDR_VENDOR_ID 0x13 + +// CFI Data +#define CFI_QRY 0x00595251 + +// READ Commands +#define P30_CMD_READ_DEVICE_ID 0x0090 +#define P30_CMD_READ_STATUS_REGISTER 0x0070 +#define P30_CMD_CLEAR_STATUS_REGISTER 0x0050 +#define P30_CMD_READ_ARRAY 0x00FF +#define P30_CMD_READ_CFI_QUERY 0x0098 + +// WRITE Commands +#define P30_CMD_WORD_PROGRAM_SETUP 0x0040 +#define P30_CMD_ALTERNATE_WORD_PROGRAM_SETUP 0x0010 +#define P30_CMD_BUFFERED_PROGRAM_SETUP 0x00E8 +#define P30_CMD_BUFFERED_PROGRAM_CONFIRM 0x00D0 +#define P30_CMD_BEFP_SETUP 0x0080 +#define P30_CMD_BEFP_CONFIRM 0x00D0 + +// ERASE Commands +#define P30_CMD_BLOCK_ERASE_SETUP 0x0020 +#define P30_CMD_BLOCK_ERASE_CONFIRM 0x00D0 + +// SUSPEND Commands +#define P30_CMD_PROGRAM_OR_ERASE_SUSPEND 0x00B0 +#define P30_CMD_SUSPEND_RESUME 0x00D0 + +// BLOCK LOCKING / UNLOCKING Commands +#define P30_CMD_LOCK_BLOCK_SETUP 0x0060 +#define P30_CMD_LOCK_BLOCK 0x0001 +#define P30_CMD_UNLOCK_BLOCK 0x00D0 +#define P30_CMD_LOCK_DOWN_BLOCK 0x002F + +// PROTECTION Commands +#define P30_CMD_PROGRAM_PROTECTION_REGISTER_SETUP 0x00C0 + +// CONFIGURATION Commands +#define P30_CMD_READ_CONFIGURATION_REGISTER_SETUP 0x0060 +#define P30_CMD_READ_CONFIGURATION_REGISTER 0x0003 + +#define NOR_FLASH_SIGNATURE SIGNATURE_32('n', 'o', 'r', '0') +#define INSTANCE_FROM_FVB_THIS(a) CR(a, NOR_FLASH_INSTANCE, FvbProtocol, = NOR_FLASH_SIGNATURE) + +typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE; + +#pragma pack (1) +typedef struct { + VENDOR_DEVICE_PATH Vendor; + UINT8 Index; + EFI_DEVICE_PATH_PROTOCOL End; +} NOR_FLASH_DEVICE_PATH; +#pragma pack () + +struct _NOR_FLASH_INSTANCE { + UINT32 Signature; + EFI_HANDLE Handle; + + UINTN DeviceBaseAddress; + UINTN RegionBaseAddress; + UINTN Size; + EFI_LBA StartLba; + EFI_LBA LastBlock; + UINT32 BlockSize; + + EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol; + VOID *ShadowBuffer; + + NOR_FLASH_DEVICE_PATH DevicePath; +}; + +EFI_STATUS +NorFlashReadCfiData ( + IN UINTN DeviceBaseAddress, + IN UINTN CFI_Offset, + IN UINT32 NumberOfBytes, + OUT UINT32 *Data + ); + +EFI_STATUS +NorFlashWriteBuffer ( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN TargetAddress, + IN UINTN BufferSizeInBytes, + IN UINT32 *Buffer + ); + +// +// NorFlashFvbDxe.c +// + +EFI_STATUS +EFIAPI +FvbGetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ); + +EFI_STATUS +EFIAPI +FvbSetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ); + +EFI_STATUS +EFIAPI +FvbGetPhysicalAddress ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_PHYSICAL_ADDRESS *Address + ); + +EFI_STATUS +EFIAPI +FvbGetBlockSize ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + OUT UINTN *BlockSize, + OUT UINTN *NumberOfBlocks + ); + +EFI_STATUS +EFIAPI +FvbRead ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN OUT UINT8 *Buffer + ); + +EFI_STATUS +EFIAPI +FvbWrite ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ); + +EFI_STATUS +EFIAPI +FvbEraseBlocks ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + ... + ); + +EFI_STATUS +ValidateFvHeader ( + IN NOR_FLASH_INSTANCE *Instance + ); + +EFI_STATUS +InitializeFvAndVariableStoreHeaders ( + IN NOR_FLASH_INSTANCE *Instance + ); + +VOID +EFIAPI +FvbVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ); + +// +// NorFlashDxe.c +// + +EFI_STATUS +NorFlashWriteFullBlock ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINT32 *DataBuffer, + IN UINT32 BlockSizeInWords + ); + +EFI_STATUS +NorFlashUnlockAndEraseSingleBlock ( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN BlockAddress + ); + +EFI_STATUS +NorFlashCreateInstance ( + IN UINTN NorFlashDeviceBase, + IN UINTN NorFlashRegionBase, + IN UINTN NorFlashSize, + IN UINT32 Index, + IN UINT32 BlockSize, + IN BOOLEAN SupportFvb, + OUT NOR_FLASH_INSTANCE **NorFlashInstance + ); + +EFI_STATUS +EFIAPI +NorFlashFvbInitialize ( + IN NOR_FLASH_INSTANCE *Instance + ); + +// +// NorFlash.c +// +EFI_STATUS +NorFlashWriteSingleBlock ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ); + +EFI_STATUS +NorFlashWriteBlocks ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN BufferSizeInBytes, + IN VOID *Buffer + ); + +EFI_STATUS +NorFlashReadBlocks ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN BufferSizeInBytes, + OUT VOID *Buffer + ); + +EFI_STATUS +NorFlashRead ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN Offset, + IN UINTN BufferSizeInBytes, + OUT VOID *Buffer + ); + +EFI_STATUS +NorFlashWrite ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ); + +EFI_STATUS +NorFlashReset ( + IN NOR_FLASH_INSTANCE *Instance + ); + +EFI_STATUS +NorFlashEraseSingleBlock ( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN BlockAddress + ); + +EFI_STATUS +NorFlashUnlockSingleBlockIfNecessary ( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN BlockAddress + ); + +EFI_STATUS +NorFlashWriteSingleWord ( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN WordAddress, + IN UINT32 WriteData + ); + +VOID +EFIAPI +NorFlashVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ); + +#endif /* __VIRT_NOR_FLASH__ */ diff --git a/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorF= lashDxe.c b/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFl= ashDxe.c new file mode 100755 index 00000000..a7620702 --- /dev/null +++ b/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashDxe= .c @@ -0,0 +1,447 @@ +/** @file NorFlashDxe.c + + Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.
+ Copyright (c) 2024, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +#include "VirtNorFlash.h" + +STATIC EFI_EVENT mNorFlashVirtualAddrChangeEvent; + +// +// Global variable declarations +// +NOR_FLASH_INSTANCE **mNorFlashInstances; +UINT32 mNorFlashDeviceCount; +UINTN mFlashNvStorageVariableBase; +EFI_EVENT mFvbVirtualAddrChangeEvent; + +NOR_FLASH_INSTANCE mNorFlashInstanceTemplate =3D { + NOR_FLASH_SIGNATURE, // Signature + NULL, // Handle ... NEED TO BE FILLED + + 0, // DeviceBaseAddress ... NEED TO BE FILLED + 0, // RegionBaseAddress ... NEED TO BE FILLED + 0, // Size ... NEED TO BE FILLED + 0, // StartLba + 0, // LastBlock + 0, // BlockSize + + { + FvbGetAttributes, // GetAttributes + FvbSetAttributes, // SetAttributes + FvbGetPhysicalAddress, // GetPhysicalAddress + FvbGetBlockSize, // GetBlockSize + FvbRead, // Read + FvbWrite, // Write + FvbEraseBlocks, // EraseBlocks + NULL, // ParentHandle + }, // FvbProtoccol; + NULL, // ShadowBuffer + { + { + { + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + { + (UINT8)(OFFSET_OF (NOR_FLASH_DEVICE_PATH, End)), + (UINT8)(OFFSET_OF (NOR_FLASH_DEVICE_PATH, End) >> 8) + } + }, + { 0x0, 0x0, 0x0, { 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0 } + }, // GU= ID ... NEED TO BE FILLED + }, + 0, // Index + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } + } + } // DevicePath +}; + +EFI_STATUS +NorFlashCreateInstance ( + IN UINTN NorFlashDeviceBase, + IN UINTN NorFlashRegionBase, + IN UINTN NorFlashSize, + IN UINT32 Index, + IN UINT32 BlockSize, + IN BOOLEAN SupportFvb, + OUT NOR_FLASH_INSTANCE **NorFlashInstance + ) +{ + EFI_STATUS Status; + NOR_FLASH_INSTANCE *Instance; + + ASSERT (NorFlashInstance !=3D NULL); + + Instance =3D AllocateRuntimeCopyPool (sizeof (NOR_FLASH_INSTANCE), &mNor= FlashInstanceTemplate); + if (Instance =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Instance->DeviceBaseAddress =3D NorFlashDeviceBase; + Instance->RegionBaseAddress =3D NorFlashRegionBase; + Instance->Size =3D NorFlashSize; + Instance->BlockSize =3D BlockSize; + Instance->LastBlock =3D (NorFlashSize / BlockSize) - 1; + + CopyGuid (&Instance->DevicePath.Vendor.Guid, &gEfiCallerIdGuid); + Instance->DevicePath.Index =3D (UINT8)Index; + + Instance->ShadowBuffer =3D AllocateRuntimePool (BlockSize); + if (Instance->ShadowBuffer =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + if (SupportFvb) { + NorFlashFvbInitialize (Instance); + + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Instance->Handle, + &gEfiDevicePathProtocolGuid, + &Instance->DevicePath, + &gEfiFirmwareVolumeBlockProtocolGuid, + &Instance->FvbProtocol, + NULL + ); + if (EFI_ERROR (Status)) { + FreePool (Instance); + return Status; + } + } else { + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Instance->Handle, + &gEfiDevicePathProtocolGuid, + &Instance->DevicePath, + NULL + ); + if (EFI_ERROR (Status)) { + FreePool (Instance); + return Status; + } + } + + *NorFlashInstance =3D Instance; + return Status; +} + +/** + * This function unlock and erase an entire NOR Flash block. + **/ +EFI_STATUS +NorFlashUnlockAndEraseSingleBlock ( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN BlockAddress + ) +{ + EFI_STATUS Status; + UINTN Index; + EFI_TPL OriginalTPL; + + if (!EfiAtRuntime ()) { + // Raise TPL to TPL_HIGH to stop anyone from interrupting us. + OriginalTPL =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); + } else { + // This initialization is only to prevent the compiler to complain abo= ut the + // use of uninitialized variables + OriginalTPL =3D TPL_HIGH_LEVEL; + } + + Index =3D 0; + // The block erase might fail a first time (SW bug ?). Retry it ... + do { + // Unlock the block if we have to + Status =3D NorFlashUnlockSingleBlockIfNecessary (Instance, BlockAddres= s); + if (EFI_ERROR (Status)) { + break; + } + + Status =3D NorFlashEraseSingleBlock (Instance, BlockAddress); + Index++; + } while ((Index < NOR_FLASH_ERASE_RETRY) && (Status =3D=3D EFI_WRITE_PRO= TECTED)); + + if (Index =3D=3D NOR_FLASH_ERASE_RETRY) { + DEBUG ((DEBUG_ERROR, "EraseSingleBlock(BlockAddress=3D0x%08x: Block Lo= cked Error (try to erase %d times)\n", BlockAddress, Index)); + } + + if (!EfiAtRuntime ()) { + // Interruptions can resume. + gBS->RestoreTPL (OriginalTPL); + } + + return Status; +} + +EFI_STATUS +NorFlashWriteFullBlock ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINT32 *DataBuffer, + IN UINT32 BlockSizeInWords + ) +{ + EFI_STATUS Status; + UINTN WordAddress; + UINT32 WordIndex; + UINTN BufferIndex; + UINTN BlockAddress; + UINTN BuffersInBlock; + UINTN RemainingWords; + EFI_TPL OriginalTPL; + UINTN Cnt; + + Status =3D EFI_SUCCESS; + + // Get the physical address of the block + BlockAddress =3D GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba= , BlockSizeInWords * 4); + + // Start writing from the first address at the start of the block + WordAddress =3D BlockAddress; + + if (!EfiAtRuntime ()) { + // Raise TPL to TPL_HIGH to stop anyone from interrupting us. + OriginalTPL =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); + } else { + // This initialization is only to prevent the compiler to complain abo= ut the + // use of uninitialized variables + OriginalTPL =3D TPL_HIGH_LEVEL; + } + + Status =3D NorFlashUnlockAndEraseSingleBlock (Instance, BlockAddress); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "WriteSingleBlock: ERROR - Failed to Unlock and E= rase the single block at 0x%X\n", BlockAddress)); + goto EXIT; + } + + // To speed up the programming operation, NOR Flash is programmed using = the Buffered Programming method. + + // Check that the address starts at a 32-word boundary, i.e. last 7 bits= must be zero + if ((WordAddress & BOUNDARY_OF_32_WORDS) =3D=3D 0x00) { + // First, break the entire block into buffer-sized chunks. + BuffersInBlock =3D (UINTN)(BlockSizeInWords * 4) / P30_MAX_BUFFER_SIZE= _IN_BYTES; + + // Then feed each buffer chunk to the NOR Flash + // If a buffer does not contain any data, don't write it. + for (BufferIndex =3D 0; + BufferIndex < BuffersInBlock; + BufferIndex++, WordAddress +=3D P30_MAX_BUFFER_SIZE_IN_BYTES, Dat= aBuffer +=3D P30_MAX_BUFFER_SIZE_IN_WORDS + ) + { + // Check the buffer to see if it contains any data (not set all 1s). + for (Cnt =3D 0; Cnt < P30_MAX_BUFFER_SIZE_IN_WORDS; Cnt++) { + if (~DataBuffer[Cnt] !=3D 0 ) { + // Some data found, write the buffer. + Status =3D NorFlashWriteBuffer ( + Instance, + WordAddress, + P30_MAX_BUFFER_SIZE_IN_BYTES, + DataBuffer + ); + if (EFI_ERROR (Status)) { + goto EXIT; + } + + break; + } + } + } + + // Finally, finish off any remaining words that are less than the maxi= mum size of the buffer + RemainingWords =3D BlockSizeInWords % P30_MAX_BUFFER_SIZE_IN_WORDS; + + if (RemainingWords !=3D 0) { + Status =3D NorFlashWriteBuffer (Instance, WordAddress, (RemainingWor= ds * 4), DataBuffer); + if (EFI_ERROR (Status)) { + goto EXIT; + } + } + } else { + // For now, use the single word programming algorithm + // It is unlikely that the NOR Flash will exist in an address which fa= lls within a 32 word boundary range, + // i.e. which ends in the range 0x......01 - 0x......7F. + for (WordIndex =3D 0; WordIndex < BlockSizeInWords; WordIndex++, DataB= uffer++, WordAddress =3D WordAddress + 4) { + Status =3D NorFlashWriteSingleWord (Instance, WordAddress, *DataBuff= er); + if (EFI_ERROR (Status)) { + goto EXIT; + } + } + } + +EXIT: + // Put device back into Read Array mode + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_READ_ARRAY); + + if (!EfiAtRuntime ()) { + // Interruptions can resume. + gBS->RestoreTPL (OriginalTPL); + } + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "NOR FLASH Programming [WriteSingleBlock] failed = at address 0x%08x. Exit Status =3D \"%r\".\n", WordAddress, Status)); + } + + return Status; +} + +EFI_STATUS +EFIAPI +NorFlashInitialise ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINT32 Index; + VIRT_NOR_FLASH_DESCRIPTION *NorFlashDevices; + BOOLEAN ContainVariableStorage; + + Status =3D VirtNorFlashPlatformInitialization (); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "NorFlashInitialise: Fail to initialize Nor Flash= devices\n")); + return Status; + } + + Status =3D VirtNorFlashPlatformGetDevices (&NorFlashDevices, &mNorFlashD= eviceCount); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "NorFlashInitialise: Fail to get Nor Flash device= s\n")); + return Status; + } + + mNorFlashInstances =3D AllocateRuntimePool (sizeof (NOR_FLASH_INSTANCE *= ) * mNorFlashDeviceCount); + + for (Index =3D 0; Index < mNorFlashDeviceCount; Index++) { + // Check if this NOR Flash device contain the variable storage region + + if (PcdGet64 (PcdFlashNvStorageVariableBase64) !=3D 0) { + ContainVariableStorage =3D + (NorFlashDevices[Index].RegionBaseAddress <=3D PcdGet64 (PcdFlashN= vStorageVariableBase64)) && + (PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashNv= StorageVariableSize) <=3D + NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index]= .Size); + } else { + ContainVariableStorage =3D + (NorFlashDevices[Index].RegionBaseAddress <=3D PcdGet32 (PcdFlashN= vStorageVariableBase)) && + (PcdGet32 (PcdFlashNvStorageVariableBase) + PcdGet32 (PcdFlashNvSt= orageVariableSize) <=3D + NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index]= .Size); + } + + Status =3D NorFlashCreateInstance ( + NorFlashDevices[Index].DeviceBaseAddress, + NorFlashDevices[Index].RegionBaseAddress, + NorFlashDevices[Index].Size, + Index, + NorFlashDevices[Index].BlockSize, + ContainVariableStorage, + &mNorFlashInstances[Index] + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "NorFlashInitialise: Fail to create instance fo= r NorFlash[%d]\n", Index)); + } + } + + // + // Register for the virtual address change event + // + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + NorFlashVirtualNotifyEvent, + NULL, + &gEfiEventVirtualAddressChangeGuid, + &mNorFlashVirtualAddrChangeEvent + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +EFI_STATUS +EFIAPI +NorFlashFvbInitialize ( + IN NOR_FLASH_INSTANCE *Instance + ) +{ + EFI_STATUS Status; + UINT32 FvbNumLba; + EFI_BOOT_MODE BootMode; + + DEBUG ((DEBUG_BLKIO, "NorFlashFvbInitialize\n")); + ASSERT ((Instance !=3D NULL)); + + mFlashNvStorageVariableBase =3D (PcdGet64 (PcdFlashNvStorageVariableBase= 64) !=3D 0) ? + PcdGet64 (PcdFlashNvStorageVariableBase64)= : PcdGet32 (PcdFlashNvStorageVariableBase); + + // Set the index of the first LBA for the FVB + Instance->StartLba =3D (mFlashNvStorageVariableBase - Instance->RegionBa= seAddress) / Instance->BlockSize; + + BootMode =3D GetBootModeHob (); + if (BootMode =3D=3D BOOT_WITH_DEFAULT_SETTINGS) { + Status =3D EFI_INVALID_PARAMETER; + } else { + // Determine if there is a valid header at the beginning of the NorFla= sh + Status =3D ValidateFvHeader (Instance); + } + + // Install the Default FVB header if required + if (EFI_ERROR (Status)) { + // There is no valid header, so time to install one. + DEBUG ((DEBUG_INFO, "%a: The FVB Header is not valid.\n", __func__)); + DEBUG (( + DEBUG_INFO, + "%a: Installing a correct one for this volume.\n", + __func__ + )); + + // Erase all the NorFlash that is reserved for variable storage + FvbNumLba =3D (PcdGet32 (PcdFlashNvStorageVariableSize) + PcdGet32 (Pc= dFlashNvStorageFtwWorkingSize) + PcdGet32 (PcdFlashNvStorageFtwSpareSize)) = / Instance->BlockSize; + + Status =3D FvbEraseBlocks (&Instance->FvbProtocol, (EFI_LBA)0, FvbNumL= ba, EFI_LBA_LIST_TERMINATOR); + if (EFI_ERROR (Status)) { + return Status; + } + + // Install all appropriate headers + Status =3D InitializeFvAndVariableStoreHeaders (Instance); + if (EFI_ERROR (Status)) { + return Status; + } + } + + // + // The driver implementing the variable read service can now be dispatch= ed; + // the varstore headers are in place. + // + Status =3D gBS->InstallProtocolInterface ( + &gImageHandle, + &gEdkiiNvVarStoreFormattedGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + ASSERT_EFI_ERROR (Status); + + // + // Register for the virtual address change event + // + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + FvbVirtualNotifyEvent, + NULL, + &gEfiEventVirtualAddressChangeGuid, + &mFvbVirtualAddrChangeEvent + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorF= lashDxe.inf b/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNor= FlashDxe.inf new file mode 100755 index 00000000..8975bdb1 --- /dev/null +++ b/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashDxe= .inf @@ -0,0 +1,69 @@ +#/** @file +# +# Component description file for NorFlashDxe module +# +# Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.
+# Copyright (c) 2024, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 1.29 + BASE_NAME =3D VirtNorFlashDxe + FILE_GUID =3D ADA0DB67-7C55-4950-8BA3-FC6D19CEA52F + MODULE_TYPE =3D DXE_RUNTIME_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D NorFlashInitialise + +[Sources.common] + VirtNorFlash.c + VirtNorFlash.h + VirtNorFlashDxe.c + VirtNorFlashFvb.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + OvmfPkg/OvmfPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + HobLib + IoLib + SafeIntLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + UefiRuntimeLib + VirtNorFlashPlatformLib + +[Guids] + gEdkiiNvVarStoreFormattedGuid ## PRODUCES ## PROTOCOL + gEfiAuthenticatedVariableGuid + gEfiEventVirtualAddressChangeGuid + gEfiSystemNvDataFvGuid + gEfiVariableGuid + +[Protocols] + gEfiBlockIoProtocolGuid + gEfiDevicePathProtocolGuid + gEfiDiskIoProtocolGuid + gEfiFirmwareVolumeBlockProtocolGuid + +[Pcd.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + +[Depex] + gEfiCpuArchProtocolGuid diff --git a/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorF= lashFvb.c b/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFl= ashFvb.c new file mode 100755 index 00000000..c8b5e0be --- /dev/null +++ b/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashFvb= .c @@ -0,0 +1,904 @@ +/*++ @file NorFlashFvbDxe.c + + Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + --*/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "VirtNorFlash.h" + +extern UINTN mFlashNvStorageVariableBase; +/// +/// The Firmware Volume Block Protocol is the low-level interface +/// to a firmware volume. File-level access to a firmware volume +/// should not be done using the Firmware Volume Block Protocol. +/// Normal access to a firmware volume must use the Firmware +/// Volume Protocol. Typically, only the file system driver that +/// produces the Firmware Volume Protocol will bind to the +/// Firmware Volume Block Protocol. +/// + +/** + Initialises the FV Header and Variable Store Header + to support variable operations. + + @param[in] Ptr - Location to initialise the headers + +**/ +EFI_STATUS +InitializeFvAndVariableStoreHeaders ( + IN NOR_FLASH_INSTANCE *Instance + ) +{ + EFI_STATUS Status; + VOID *Headers; + UINTN HeadersLength; + EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader; + VARIABLE_STORE_HEADER *VariableStoreHeader; + UINT32 NvStorageFtwSpareSize; + UINT32 NvStorageFtwWorkingSize; + UINT32 NvStorageVariableSize; + UINT64 NvStorageFtwSpareBase; + UINT64 NvStorageFtwWorkingBase; + UINT64 NvStorageVariableBase; + + HeadersLength =3D sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_B= LOCK_MAP_ENTRY) + sizeof (VARIABLE_STORE_HEADER); + Headers =3D AllocateZeroPool (HeadersLength); + + NvStorageFtwWorkingSize =3D PcdGet32 (PcdFlashNvStorageFtwWorkingSize); + NvStorageFtwSpareSize =3D PcdGet32 (PcdFlashNvStorageFtwSpareSize); + NvStorageVariableSize =3D PcdGet32 (PcdFlashNvStorageVariableSize); + + NvStorageFtwSpareBase =3D (PcdGet64 (PcdFlashNvStorageFtwSpareBase64) != =3D 0) ? + PcdGet64 (PcdFlashNvStorageFtwSpareBase64) : Pcd= Get32 (PcdFlashNvStorageFtwSpareBase); + NvStorageFtwWorkingBase =3D (PcdGet64 (PcdFlashNvStorageFtwWorkingBase64= ) !=3D 0) ? + PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) := PcdGet32 (PcdFlashNvStorageFtwWorkingBase); + NvStorageVariableBase =3D (PcdGet64 (PcdFlashNvStorageVariableBase64) != =3D 0) ? + PcdGet64 (PcdFlashNvStorageVariableBase64) : Pcd= Get32 (PcdFlashNvStorageVariableBase); + + // FirmwareVolumeHeader->FvLength is declared to have the Variable area = AND the FTW working area AND the FTW Spare contiguous. + if ((NvStorageVariableBase + NvStorageVariableSize) !=3D NvStorageFtwWor= kingBase) { + DEBUG (( + DEBUG_ERROR, + "%a: NvStorageFtwWorkingBase is not contiguous with NvStorageVariabl= eBase region\n", + __func__ + )); + return EFI_INVALID_PARAMETER; + } + + if ((NvStorageFtwWorkingBase + NvStorageFtwWorkingSize) !=3D NvStorageFt= wSpareBase) { + DEBUG (( + DEBUG_ERROR, + "%a: NvStorageFtwSpareBase is not contiguous with NvStorageFtwWorkin= gBase region\n", + __func__ + )); + return EFI_INVALID_PARAMETER; + } + + // Check if the size of the area is at least one block size + if ((NvStorageVariableSize <=3D 0) || (NvStorageVariableSize / Instance-= >BlockSize <=3D 0)) { + DEBUG (( + DEBUG_ERROR, + "%a: NvStorageVariableSize is 0x%x, should be atleast one block size= \n", + __func__, + NvStorageVariableSize + )); + return EFI_INVALID_PARAMETER; + } + + if ((NvStorageFtwWorkingSize <=3D 0) || (NvStorageFtwWorkingSize / Insta= nce->BlockSize <=3D 0)) { + DEBUG (( + DEBUG_ERROR, + "%a: NvStorageFtwWorkingSize is 0x%x, should be atleast one block si= ze\n", + __func__, + NvStorageFtwWorkingSize + )); + return EFI_INVALID_PARAMETER; + } + + if ((NvStorageFtwSpareSize <=3D 0) || (NvStorageFtwSpareSize / Instance-= >BlockSize <=3D 0)) { + DEBUG (( + DEBUG_ERROR, + "%a: NvStorageFtwSpareSize is 0x%x, should be atleast one block size= \n", + __func__, + NvStorageFtwSpareSize + )); + return EFI_INVALID_PARAMETER; + } + + // Ensure the Variable area Base Addresses are aligned on a block size b= oundaries + if ((NvStorageVariableBase % Instance->BlockSize !=3D 0) || + (NvStorageFtwWorkingBase % Instance->BlockSize !=3D 0) || + (NvStorageFtwSpareBase % Instance->BlockSize !=3D 0)) + { + DEBUG ((DEBUG_ERROR, "%a: NvStorage Base addresses must be aligned to = block size boundaries", __func__)); + return EFI_INVALID_PARAMETER; + } + + // + // EFI_FIRMWARE_VOLUME_HEADER + // + FirmwareVolumeHeader =3D (EFI_FIRMWARE_VOLUME_HEADER *)Headers; + CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid= ); + FirmwareVolumeHeader->FvLength =3D + PcdGet32 (PcdFlashNvStorageVariableSize) + + PcdGet32 (PcdFlashNvStorageFtwWorkingSize) + + PcdGet32 (PcdFlashNvStorageFtwSpareSize); + FirmwareVolumeHeader->Signature =3D EFI_FVH_SIGNATURE; + FirmwareVolumeHeader->Attributes =3D (EFI_FVB_ATTRIBUTES_2)( + EFI_FVB2_READ_= ENABLED_CAP | // Reads may be enabled + EFI_FVB2_READ_= STATUS | // Reads are currently enabled + EFI_FVB2_STICK= Y_WRITE | // A block erase is required to flip bits into EFI_FVB2_ERA= SE_POLARITY + EFI_FVB2_MEMOR= Y_MAPPED | // It is memory mapped + EFI_FVB2_ERASE= _POLARITY | // After erasure all bits take this value (i.e. '1') + EFI_FVB2_WRITE= _STATUS | // Writes are currently enabled + EFI_FVB2_WRITE= _ENABLED_CAP // Writes may be enabled + ); + FirmwareVolumeHeader->HeaderLength =3D sizeof (EFI_FIRMWARE_VOL= UME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY); + FirmwareVolumeHeader->Revision =3D EFI_FVH_REVISION; + FirmwareVolumeHeader->BlockMap[0].NumBlocks =3D Instance->LastBlock + 1; + FirmwareVolumeHeader->BlockMap[0].Length =3D Instance->BlockSize; + FirmwareVolumeHeader->BlockMap[1].NumBlocks =3D 0; + FirmwareVolumeHeader->BlockMap[1].Length =3D 0; + FirmwareVolumeHeader->Checksum =3D CalculateCheckSum16 ((UI= NT16 *)FirmwareVolumeHeader, FirmwareVolumeHeader->HeaderLength); + + // + // VARIABLE_STORE_HEADER + // + VariableStoreHeader =3D (VARIABLE_STORE_HEADER *)((UINTN)Headers + Firmw= areVolumeHeader->HeaderLength); + CopyGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGui= d); + VariableStoreHeader->Size =3D PcdGet32 (PcdFlashNvStorageVariableSize)= - FirmwareVolumeHeader->HeaderLength; + VariableStoreHeader->Format =3D VARIABLE_STORE_FORMATTED; + VariableStoreHeader->State =3D VARIABLE_STORE_HEALTHY; + + // Install the combined super-header in the NorFlash + Status =3D FvbWrite (&Instance->FvbProtocol, 0, 0, &HeadersLength, Heade= rs); + + FreePool (Headers); + return Status; +} + +/** + Check the integrity of firmware volume header. + + @param[in] FwVolHeader - A pointer to a firmware volume header + + @retval EFI_SUCCESS - The firmware volume is consistent + @retval EFI_NOT_FOUND - The firmware volume has been corrupted. + +**/ +EFI_STATUS +ValidateFvHeader ( + IN NOR_FLASH_INSTANCE *Instance + ) +{ + UINT16 Checksum; + CONST EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader; + CONST VARIABLE_STORE_HEADER *VariableStoreHeader; + UINTN VarOffset; + UINTN VariableStoreLength; + UINTN FvLength; + + FwVolHeader =3D (EFI_FIRMWARE_VOLUME_HEADER *)Instance->RegionBaseAddres= s; + + FvLength =3D PcdGet32 (PcdFlashNvStorageVariableSize) + PcdGet32 (PcdFla= shNvStorageFtwWorkingSize) + + PcdGet32 (PcdFlashNvStorageFtwSpareSize); + + // + // Verify the header revision, header signature, length + // Length of FvBlock cannot be 2**64-1 + // HeaderLength cannot be an odd number + // + if ( (FwVolHeader->Revision !=3D EFI_FVH_REVISION) + || (FwVolHeader->Signature !=3D EFI_FVH_SIGNATURE) + || (FwVolHeader->FvLength !=3D FvLength) + ) + { + DEBUG (( + DEBUG_INFO, + "%a: No Firmware Volume header present\n", + __func__ + )); + return EFI_NOT_FOUND; + } + + // Check the Firmware Volume Guid + if ( CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid)= =3D=3D FALSE ) { + DEBUG (( + DEBUG_INFO, + "%a: Firmware Volume Guid non-compatible\n", + __func__ + )); + return EFI_NOT_FOUND; + } + + // Verify the header checksum + Checksum =3D CalculateSum16 ((UINT16 *)FwVolHeader, FwVolHeader->HeaderL= ength); + if (Checksum !=3D 0) { + DEBUG (( + DEBUG_INFO, + "%a: FV checksum is invalid (Checksum:0x%X)\n", + __func__, + Checksum + )); + return EFI_NOT_FOUND; + } + + VariableStoreHeader =3D (VARIABLE_STORE_HEADER *)((UINTN)FwVolHeader + F= wVolHeader->HeaderLength); + + // Check the Variable Store Guid + if (!CompareGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVar= iableGuid)) { + DEBUG (( + DEBUG_INFO, + "%a: Variable Store Guid non-compatible\n", + __func__ + )); + return EFI_NOT_FOUND; + } + + VariableStoreLength =3D PcdGet32 (PcdFlashNvStorageVariableSize) - FwVol= Header->HeaderLength; + if (VariableStoreHeader->Size !=3D VariableStoreLength) { + DEBUG (( + DEBUG_INFO, + "%a: Variable Store Length does not match\n", + __func__ + )); + return EFI_NOT_FOUND; + } + + // + // check variables + // + DEBUG ((DEBUG_INFO, "%a: checking variables\n", __func__)); + VarOffset =3D sizeof (*VariableStoreHeader); + for ( ; ;) { + UINTN VarHeaderEnd; + UINTN VarNameEnd; + UINTN VarEnd; + UINTN VarPadding; + CONST AUTHENTICATED_VARIABLE_HEADER *VarHeader; + CONST CHAR16 *VarName; + CONST CHAR8 *VarState; + RETURN_STATUS Status; + + Status =3D SafeUintnAdd (VarOffset, sizeof (*VarHeader), &VarHeaderEnd= ); + if (RETURN_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: integer overflow\n", __func__)); + return EFI_NOT_FOUND; + } + + if (VarHeaderEnd >=3D VariableStoreHeader->Size) { + if (VarOffset <=3D VariableStoreHeader->Size - sizeof (UINT16)) { + CONST UINT16 *StartId; + + StartId =3D (VOID *)((UINTN)VariableStoreHeader + VarOffset); + if (*StartId =3D=3D 0x55aa) { + DEBUG ((DEBUG_ERROR, "%a: startid at invalid location\n", __func= __)); + return EFI_NOT_FOUND; + } + } + + DEBUG ((DEBUG_INFO, "%a: end of var list (no space left)\n", __func_= _)); + break; + } + + VarHeader =3D (VOID *)((UINTN)VariableStoreHeader + VarOffset); + if (VarHeader->StartId !=3D 0x55aa) { + DEBUG ((DEBUG_INFO, "%a: end of var list (no startid)\n", __func__))= ; + break; + } + + if (VarHeader->State =3D=3D 0xff) { + DEBUG ((DEBUG_INFO, "%a: end of var list (unwritten state)\n", __fun= c__)); + break; + } + + VarName =3D NULL; + switch (VarHeader->State) { + // usage: State =3D VAR_HEADER_VALID_ONLY + case VAR_HEADER_VALID_ONLY: + VarState =3D "header-ok"; + VarName =3D L""; + break; + + // usage: State =3D VAR_ADDED + case VAR_ADDED: + VarState =3D "ok"; + break; + + // usage: State &=3D VAR_IN_DELETED_TRANSITION + case VAR_ADDED &VAR_IN_DELETED_TRANSITION: + VarState =3D "del-in-transition"; + break; + + // usage: State &=3D VAR_DELETED + case VAR_ADDED &VAR_DELETED: + case VAR_ADDED &VAR_DELETED &VAR_IN_DELETED_TRANSITION: + VarState =3D "deleted"; + break; + + default: + DEBUG (( + DEBUG_ERROR, + "%a: invalid variable state: 0x%x\n", + __func__, + VarHeader->State + )); + return EFI_NOT_FOUND; + } + + Status =3D SafeUintnAdd (VarHeaderEnd, VarHeader->NameSize, &VarNameEn= d); + if (RETURN_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: integer overflow\n", __func__)); + return EFI_NOT_FOUND; + } + + Status =3D SafeUintnAdd (VarNameEnd, VarHeader->DataSize, &VarEnd); + if (RETURN_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: integer overflow\n", __func__)); + return EFI_NOT_FOUND; + } + + if (VarEnd > VariableStoreHeader->Size) { + DEBUG (( + DEBUG_ERROR, + "%a: invalid variable size: 0x%Lx + 0x%Lx + 0x%x + 0x%x > 0x%x\n", + __func__, + (UINT64)VarOffset, + (UINT64)(sizeof (*VarHeader)), + VarHeader->NameSize, + VarHeader->DataSize, + VariableStoreHeader->Size + )); + return EFI_NOT_FOUND; + } + + if (((VarHeader->NameSize & 1) !=3D 0) || + (VarHeader->NameSize < 4)) + { + DEBUG ((DEBUG_ERROR, "%a: invalid name size\n", __func__)); + return EFI_NOT_FOUND; + } + + if (VarName =3D=3D NULL) { + VarName =3D (VOID *)((UINTN)VariableStoreHeader + VarHeaderEnd); + if (VarName[VarHeader->NameSize / 2 - 1] !=3D L'\0') { + DEBUG ((DEBUG_ERROR, "%a: name is not null terminated\n", __func__= )); + return EFI_NOT_FOUND; + } + } + + DEBUG (( + DEBUG_VERBOSE, + "%a: +0x%04Lx: name=3D0x%x data=3D0x%x guid=3D%g '%s' (%a)\n", + __func__, + (UINT64)VarOffset, + VarHeader->NameSize, + VarHeader->DataSize, + &VarHeader->VendorGuid, + VarName, + VarState + )); + + VarPadding =3D (4 - (VarEnd & 3)) & 3; + Status =3D SafeUintnAdd (VarEnd, VarPadding, &VarOffset); + if (RETURN_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: integer overflow\n", __func__)); + return EFI_NOT_FOUND; + } + } + + return EFI_SUCCESS; +} + +/** + The GetAttributes() function retrieves the attributes and + current settings of the block. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL ins= tance. + + @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attribut= es and + current settings are returned. + Type EFI_FVB_ATTRIBUTES_2 is defined in EFI_FIRMWARE_= VOLUME_HEADER. + + @retval EFI_SUCCESS The firmware volume attributes were returned. + + **/ +EFI_STATUS +EFIAPI +FvbGetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ) +{ + EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes; + + FlashFvbAttributes =3D (EFI_FVB_ATTRIBUTES_2)( + + EFI_FVB2_READ_ENABLED_CAP | = // Reads may be enabled + EFI_FVB2_READ_STATUS | = // Reads are currently enabled + EFI_FVB2_STICKY_WRITE | = // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY + EFI_FVB2_MEMORY_MAPPED | = // It is memory mapped + EFI_FVB2_ERASE_POLARITY | = // After erasure all bits take this value (i.e. '1') + EFI_FVB2_WRITE_STATUS | = // Writes are currently enabled + EFI_FVB2_WRITE_ENABLED_CAP = // Writes may be enabled + + ); + + *Attributes =3D FlashFvbAttributes; + + DEBUG ((DEBUG_BLKIO, "FvbGetAttributes(0x%X)\n", *Attributes)); + + return EFI_SUCCESS; +} + +/** + The SetAttributes() function sets configurable firmware volume attributes + and returns the new settings of the firmware volume. + + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_= PROTOCOL instance. + + @param Attributes On input, Attributes is a pointer to EFI_= FVB_ATTRIBUTES_2 + that contains the desired firmware volume= settings. + On successful return, it contains the new= settings of + the firmware volume. + Type EFI_FVB_ATTRIBUTES_2 is defined in E= FI_FIRMWARE_VOLUME_HEADER. + + @retval EFI_SUCCESS The firmware volume attributes were retur= ned. + + @retval EFI_INVALID_PARAMETER The attributes requested are in conflict = with the capabilities + as declared in the firmware volume header= . + + **/ +EFI_STATUS +EFIAPI +FvbSetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ) +{ + DEBUG ((DEBUG_BLKIO, "FvbSetAttributes(0x%X) is not supported\n", *Attri= butes)); + return EFI_UNSUPPORTED; +} + +/** + The GetPhysicalAddress() function retrieves the base address of + a memory-mapped firmware volume. This function should be called + only for memory-mapped firmware volumes. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOC= OL instance. + + @param Address Pointer to a caller-allocated + EFI_PHYSICAL_ADDRESS that, on successful + return from GetPhysicalAddress(), contains the + base address of the firmware volume. + + @retval EFI_SUCCESS The firmware volume base address was returned. + + @retval EFI_NOT_SUPPORTED The firmware volume is not memory mapped. + + **/ +EFI_STATUS +EFIAPI +FvbGetPhysicalAddress ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_PHYSICAL_ADDRESS *Address + ) +{ + NOR_FLASH_INSTANCE *Instance; + + Instance =3D INSTANCE_FROM_FVB_THIS (This); + + DEBUG ((DEBUG_BLKIO, "FvbGetPhysicalAddress(BaseAddress=3D0x%08x)\n", In= stance->RegionBaseAddress)); + + ASSERT (Address !=3D NULL); + + *Address =3D mFlashNvStorageVariableBase; + return EFI_SUCCESS; +} + +/** + The GetBlockSize() function retrieves the size of the requested + block. It also returns the number of additional blocks with + the identical size. The GetBlockSize() function is used to + retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER). + + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_= PROTOCOL instance. + + @param Lba Indicates the block for which to return t= he size. + + @param BlockSize Pointer to a caller-allocated UINTN in wh= ich + the size of the block is returned. + + @param NumberOfBlocks Pointer to a caller-allocated UINTN in + which the number of consecutive blocks, + starting with Lba, is returned. All + blocks in this range have a size of + BlockSize. + + + @retval EFI_SUCCESS The firmware volume base address was retu= rned. + + @retval EFI_INVALID_PARAMETER The requested LBA is out of range. + + **/ +EFI_STATUS +EFIAPI +FvbGetBlockSize ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + OUT UINTN *BlockSize, + OUT UINTN *NumberOfBlocks + ) +{ + EFI_STATUS Status; + NOR_FLASH_INSTANCE *Instance; + + Instance =3D INSTANCE_FROM_FVB_THIS (This); + + DEBUG ((DEBUG_BLKIO, "FvbGetBlockSize(Lba=3D%ld, BlockSize=3D0x%x, LastB= lock=3D%ld)\n", Lba, Instance->BlockSize, Instance->LastBlock)); + + if (Lba > Instance->LastBlock) { + DEBUG ((DEBUG_ERROR, "FvbGetBlockSize: ERROR - Parameter LBA %ld is be= yond the last Lba (%ld).\n", Lba, Instance->LastBlock)); + Status =3D EFI_INVALID_PARAMETER; + } else { + // This is easy because in this platform each NorFlash device has equa= l sized blocks. + *BlockSize =3D (UINTN)Instance->BlockSize; + *NumberOfBlocks =3D (UINTN)(Instance->LastBlock - Lba + 1); + + DEBUG ((DEBUG_BLKIO, "FvbGetBlockSize: *BlockSize=3D0x%x, *NumberOfBlo= cks=3D0x%x.\n", *BlockSize, *NumberOfBlocks)); + + Status =3D EFI_SUCCESS; + } + + return Status; +} + +/** + Reads the specified number of bytes into a buffer from the specified bloc= k. + + The Read() function reads the requested number of bytes from the + requested block and stores them in the provided buffer. + Implementations should be mindful that the firmware volume + might be in the ReadDisabled state. If it is in this state, + the Read() function must return the status code + EFI_ACCESS_DENIED without modifying the contents of the + buffer. The Read() function must also prevent spanning block + boundaries. If a read is requested that would span a block + boundary, the read must read up to the boundary but not + beyond. The output parameter NumBytes must be set to correctly + indicate the number of bytes actually read. The caller must be + aware that a read may be partially completed. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROT= OCOL instance. + + @param Lba The starting logical block index from which t= o read. + + @param Offset Offset into the block at which to begin readi= ng. + + @param NumBytes Pointer to a UINTN. + At entry, *NumBytes contains the total size o= f the buffer. + At exit, *NumBytes contains the total number = of bytes read. + + @param Buffer Pointer to a caller-allocated buffer that wil= l be used + to hold the data that is read. + + @retval EFI_SUCCESS The firmware volume was read successfully, a= nd contents are + in Buffer. + + @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary. + On output, NumBytes contains the total number= of bytes + returned in Buffer. + + @retval EFI_ACCESS_DENIED The firmware volume is in the ReadDisabled st= ate. + + @retval EFI_DEVICE_ERROR The block device is not functioning correctly= and could not be read. + + **/ +EFI_STATUS +EFIAPI +FvbRead ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN OUT UINT8 *Buffer + ) +{ + EFI_STATUS TempStatus; + UINTN BlockSize; + NOR_FLASH_INSTANCE *Instance; + + Instance =3D INSTANCE_FROM_FVB_THIS (This); + + DEBUG ((DEBUG_BLKIO, "FvbRead(Parameters: Lba=3D%ld, Offset=3D0x%x, *Num= Bytes=3D0x%x, Buffer @ 0x%08x)\n", Instance->StartLba + Lba, Offset, *NumBy= tes, Buffer)); + + TempStatus =3D EFI_SUCCESS; + + // Cache the block size to avoid de-referencing pointers all the time + BlockSize =3D Instance->BlockSize; + + DEBUG ((DEBUG_BLKIO, "FvbRead: Check if (Offset=3D0x%x + NumBytes=3D0x%x= ) <=3D BlockSize=3D0x%x\n", Offset, *NumBytes, BlockSize)); + + // The read must not span block boundaries. + // We need to check each variable individually because adding two large = values together overflows. + if ((Offset >=3D BlockSize) || + (*NumBytes > BlockSize) || + ((Offset + *NumBytes) > BlockSize)) + { + DEBUG ((DEBUG_ERROR, "FvbRead: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=3D= 0x%x + NumBytes=3D0x%x) > BlockSize=3D0x%x\n", Offset, *NumBytes, BlockSize= )); + return EFI_BAD_BUFFER_SIZE; + } + + // We must have some bytes to read + if (*NumBytes =3D=3D 0) { + return EFI_BAD_BUFFER_SIZE; + } + + // Decide if we are doing full block reads or not. + if (*NumBytes % BlockSize !=3D 0) { + TempStatus =3D NorFlashRead (Instance, Instance->StartLba + Lba, Offse= t, *NumBytes, Buffer); + if (EFI_ERROR (TempStatus)) { + return EFI_DEVICE_ERROR; + } + } else { + // Read NOR Flash data into shadow buffer + TempStatus =3D NorFlashReadBlocks (Instance, Instance->StartLba + Lba,= BlockSize, Buffer); + if (EFI_ERROR (TempStatus)) { + // Return one of the pre-approved error statuses + return EFI_DEVICE_ERROR; + } + } + + return EFI_SUCCESS; +} + +/** + Writes the specified number of bytes from the input buffer to the block. + + The Write() function writes the specified number of bytes from + the provided buffer to the specified block and offset. If the + firmware volume is sticky write, the caller must ensure that + all the bits of the specified range to write are in the + EFI_FVB_ERASE_POLARITY state before calling the Write() + function, or else the result will be unpredictable. This + unpredictability arises because, for a sticky-write firmware + volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY + state but cannot flip it back again. Before calling the + Write() function, it is recommended for the caller to first call + the EraseBlocks() function to erase the specified block to + write. A block erase cycle will transition bits from the + (NOT)EFI_FVB_ERASE_POLARITY state back to the + EFI_FVB_ERASE_POLARITY state. Implementations should be + mindful that the firmware volume might be in the WriteDisabled + state. If it is in this state, the Write() function must + return the status code EFI_ACCESS_DENIED without modifying the + contents of the firmware volume. The Write() function must + also prevent spanning block boundaries. If a write is + requested that spans a block boundary, the write must store up + to the boundary but not beyond. The output parameter NumBytes + must be set to correctly indicate the number of bytes actually + written. The caller must be aware that a write may be + partially completed. All writes, partial or otherwise, must be + fully flushed to the hardware before the Write() service + returns. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROT= OCOL instance. + + @param Lba The starting logical block index to write to. + + @param Offset Offset into the block at which to begin writi= ng. + + @param NumBytes The pointer to a UINTN. + At entry, *NumBytes contains the total size o= f the buffer. + At exit, *NumBytes contains the total number = of bytes actually written. + + @param Buffer The pointer to a caller-allocated buffer that= contains the source for the write. + + @retval EFI_SUCCESS The firmware volume was written successfully. + + @retval EFI_BAD_BUFFER_SIZE The write was attempted across an LBA boundar= y. + On output, NumBytes contains the total number= of bytes + actually written. + + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled s= tate. + + @retval EFI_DEVICE_ERROR The block device is malfunctioning and could = not be written. + + + **/ +EFI_STATUS +EFIAPI +FvbWrite ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ) +{ + NOR_FLASH_INSTANCE *Instance; + + Instance =3D INSTANCE_FROM_FVB_THIS (This); + + return NorFlashWriteSingleBlock (Instance, Instance->StartLba + Lba, Off= set, NumBytes, Buffer); +} + +/** + Erases and initialises a firmware volume block. + + The EraseBlocks() function erases one or more blocks as denoted + by the variable argument list. The entire parameter list of + blocks must be verified before erasing any blocks. If a block is + requested that does not exist within the associated firmware + volume (it has a larger index than the last block of the + firmware volume), the EraseBlocks() function must return the + status code EFI_INVALID_PARAMETER without modifying the contents + of the firmware volume. Implementations should be mindful that + the firmware volume might be in the WriteDisabled state. If it + is in this state, the EraseBlocks() function must return the + status code EFI_ACCESS_DENIED without modifying the contents of + the firmware volume. All calls to EraseBlocks() must be fully + flushed to the hardware before the EraseBlocks() service + returns. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_= PROTOCOL + instance. + + @param ... The variable argument list is a list of t= uples. + Each tuple describes a range of LBAs to e= rase + and consists of the following: + - An EFI_LBA that indicates the starting = LBA + - A UINTN that indicates the number of bl= ocks to erase. + + The list is terminated with an EFI_LBA_LI= ST_TERMINATOR. + For example, the following indicates that= two ranges of blocks + (5-7 and 10-11) are to be erased: + EraseBlocks (This, 5, 3, 10, 2, EFI_LBA_L= IST_TERMINATOR); + + @retval EFI_SUCCESS The erase request successfully completed. + + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabl= ed state. + + @retval EFI_DEVICE_ERROR The block device is not functioning corre= ctly and could not be written. + The firmware device may have been partial= ly erased. + + @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the var= iable argument list do + not exist in the firmware volume. + + **/ +EFI_STATUS +EFIAPI +FvbEraseBlocks ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + ... + ) +{ + EFI_STATUS Status; + VA_LIST Args; + UINTN BlockAddress; // Physical address of Lba to erase + EFI_LBA StartingLba; // Lba from which we start erasing + UINTN NumOfLba; // Number of Lba blocks to erase + NOR_FLASH_INSTANCE *Instance; + + Instance =3D INSTANCE_FROM_FVB_THIS (This); + + DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks()\n")); + + Status =3D EFI_SUCCESS; + + // Before erasing, check the entire list of parameters to ensure all spe= cified blocks are valid + + VA_START (Args, This); + do { + // Get the Lba from which we start erasing + StartingLba =3D VA_ARG (Args, EFI_LBA); + + // Have we reached the end of the list? + if (StartingLba =3D=3D EFI_LBA_LIST_TERMINATOR) { + // Exit the while loop + break; + } + + // How many Lba blocks are we requested to erase? + NumOfLba =3D VA_ARG (Args, UINTN); + + // All blocks must be within range + DEBUG (( + DEBUG_BLKIO, + "FvbEraseBlocks: Check if: ( StartingLba=3D%ld + NumOfLba=3D%Lu - 1 = ) > LastBlock=3D%ld.\n", + Instance->StartLba + StartingLba, + (UINT64)NumOfLba, + Instance->LastBlock + )); + if ((NumOfLba =3D=3D 0) || ((Instance->StartLba + StartingLba + NumOfL= ba - 1) > Instance->LastBlock)) { + VA_END (Args); + DEBUG ((DEBUG_ERROR, "FvbEraseBlocks: ERROR - Lba range goes past th= e last Lba.\n")); + Status =3D EFI_INVALID_PARAMETER; + goto EXIT; + } + } while (TRUE); + + VA_END (Args); + + // + // To get here, all must be ok, so start erasing + // + VA_START (Args, This); + do { + // Get the Lba from which we start erasing + StartingLba =3D VA_ARG (Args, EFI_LBA); + + // Have we reached the end of the list? + if (StartingLba =3D=3D EFI_LBA_LIST_TERMINATOR) { + // Exit the while loop + break; + } + + // How many Lba blocks are we requested to erase? + NumOfLba =3D VA_ARG (Args, UINTN); + + // Go through each one and erase it + while (NumOfLba > 0) { + // Get the physical address of Lba to erase + BlockAddress =3D GET_NOR_BLOCK_ADDRESS ( + Instance->RegionBaseAddress, + Instance->StartLba + StartingLba, + Instance->BlockSize + ); + + // Erase it + DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks: Erasing Lba=3D%ld @ 0x%08x.\n"= , Instance->StartLba + StartingLba, BlockAddress)); + Status =3D NorFlashUnlockAndEraseSingleBlock (Instance, BlockAddress= ); + if (EFI_ERROR (Status)) { + VA_END (Args); + Status =3D EFI_DEVICE_ERROR; + goto EXIT; + } + + // Move to the next Lba + StartingLba++; + NumOfLba--; + } + } while (TRUE); + + VA_END (Args); + +EXIT: + return Status; +} + +/** + Fixup internal data so that EFI can be call in virtual mode. + Call the passed in Child Notify event and convert any pointers in + lib to virtual mode. + + @param[in] Event The Event that is being processed + @param[in] Context Event Context +**/ +VOID +EFIAPI +FvbVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EfiConvertPointer (0x0, (VOID **)&mFlashNvStorageVariableBase); + return; +} --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#116174): https://edk2.groups.io/g/devel/message/116174 Mute This Topic: https://groups.io/mt/104645147/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-

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