[edk2-devel] [PATCH v3 2/3] UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension

["Tuan Phan" <tphan@ventanamicro.com>]

The GCD EFI_MEMORY_UC and EFI_MEMORY_WC memory attributes will be
supported when Svpbmt extension available.

Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
---
 .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 101 +++++++++++++++---
 .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf       |   1 +
 2 files changed, 88 insertions(+), 14 deletions(-)

diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
index 826a1d32a1d4..f4419bb8f380 100644
--- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
@@ -36,6 +36,11 @@
 #define PTE_PPN_SHIFT         10
 #define RISCV_MMU_PAGE_SHIFT  12
 
+#define RISCV_CPU_FEATURE_PBMT_BITMASK  BIT2
+#define PTE_PBMT_NC                     BIT61
+#define PTE_PBMT_IO                     BIT62
+#define PTE_PBMT_MASK                   (PTE_PBMT_NC | PTE_PBMT_IO)
+
 STATIC UINTN  mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF };
 STATIC UINTN  mMaxRootTableLevel;
 STATIC UINTN  mBitPerLevel;
@@ -489,32 +494,89 @@ UpdateRegionMapping (
 /**
   Convert GCD attribute to RISC-V page attribute.
 
-  @param  GcdAttributes The GCD attribute.
+  @param  GcdAttributes   The GCD attribute.
+  @param  RiscVAttribtues The pointer of RISC-V page attribute.
 
-  @return               The RISC-V page attribute.
+  @retval EFI_INVALID_PARAMETER   The RiscVAttribtues is NULL or cache type mask not valid.
+  @retval EFI_SUCCESS             The operation succesfully.
 
 **/
 STATIC
-UINTN
+EFI_STATUS
 GcdAttributeToPageAttribute (
-  IN UINTN  GcdAttributes
+  IN UINTN   GcdAttributes,
+  OUT UINTN  *RiscVAttributes
   )
 {
-  UINTN  RiscVAttributes;
+  UINT64   CacheTypeMask;
+  BOOLEAN  PmbtExtEnabled = (PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_PBMT_BITMASK) ? TRUE : FALSE;
 
-  RiscVAttributes = RISCV_PG_R | RISCV_PG_W | RISCV_PG_X;
+  if (!RiscVAttributes) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  *RiscVAttributes = RISCV_PG_R | RISCV_PG_W | RISCV_PG_X;
 
   // Determine protection attributes
   if ((GcdAttributes & EFI_MEMORY_RO) != 0) {
-    RiscVAttributes &= ~(RISCV_PG_W);
+    *RiscVAttributes &= ~(RISCV_PG_W);
   }
 
   // Process eXecute Never attribute
   if ((GcdAttributes & EFI_MEMORY_XP) != 0) {
-    RiscVAttributes &= ~RISCV_PG_X;
+    *RiscVAttributes &= ~RISCV_PG_X;
+  }
+
+  CacheTypeMask = GcdAttributes & EFI_CACHE_ATTRIBUTE_MASK;
+  if ((CacheTypeMask != 0) &&
+      (((CacheTypeMask - 1) & CacheTypeMask) != 0))
+  {
+    DEBUG (
+      (
+       DEBUG_ERROR,
+       "%a: The cache type mask (0x%llX) should contain exactly one bit set\n",
+       __func__,
+       CacheTypeMask
+      )
+      );
+    return EFI_INVALID_PARAMETER;
   }
 
-  return RiscVAttributes;
+  switch (CacheTypeMask) {
+    case EFI_MEMORY_UC:
+      if (PmbtExtEnabled) {
+        *RiscVAttributes |= PTE_PBMT_IO;
+      } else {
+        DEBUG (
+          (
+           DEBUG_VERBOSE,
+           "%a: EFI_MEMORY_UC set but Pmbt extension not available\n",
+           __func__
+          )
+          );
+      }
+
+      break;
+    case EFI_MEMORY_WC:
+      if (PmbtExtEnabled) {
+        *RiscVAttributes |= PTE_PBMT_NC;
+      } else {
+        DEBUG (
+          (
+           DEBUG_VERBOSE,
+           "%a: EFI_MEMORY_WC set but Pmbt extension not available\n",
+           __func__
+          )
+          );
+      }
+
+      break;
+    default:
+      // Default PMA mode
+      break;
+  }
+
+  return EFI_SUCCESS;
 }
 
 /**
@@ -537,21 +599,32 @@ RiscVSetMemoryAttributes (
   IN UINTN                 Attributes
   )
 {
-  UINTN  PageAttributesSet;
+  UINTN       PageAttributesSet;
+  UINTN       PageAttributesClear;
+  EFI_STATUS  Status;
 
-  PageAttributesSet = GcdAttributeToPageAttribute (Attributes);
+  Status = GcdAttributeToPageAttribute (Attributes, &PageAttributesSet);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
 
   if (!RiscVMmuEnabled ()) {
     return EFI_SUCCESS;
   }
 
+  PageAttributesClear = PTE_ATTRIBUTES_MASK;
+  if ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_PBMT_BITMASK) != 0) {
+    PageAttributesClear |= PTE_PBMT_MASK;
+  }
+
   DEBUG (
     (
      DEBUG_VERBOSE,
-     "%a: Set %llX page attribute 0x%X\n",
+     "%a: %llX: set attributes 0x%X, clear attributes 0x%X\n",
      __func__,
      BaseAddress,
-     PageAttributesSet
+     PageAttributesSet,
+     PageAttributesClear
     )
     );
 
@@ -559,7 +632,7 @@ RiscVSetMemoryAttributes (
            BaseAddress,
            Length,
            PageAttributesSet,
-           PTE_ATTRIBUTES_MASK,
+           PageAttributesClear,
            (UINTN *)RiscVGetRootTranslateTable (),
            TRUE
            );
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
index 51ebe1750e97..1dbaa81f3608 100644
--- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
@@ -28,3 +28,4 @@
 
 [Pcd]
   gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode  ## CONSUMES
+  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride     ## CONSUMES
-- 
2.25.1



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