From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 554FB941612 for ; Wed, 6 Mar 2024 11:42:05 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=hal5dsIrFtBng9pqtX5ZfP0NZH5/a4VfwAb5dBYkYUA=; c=relaxed/simple; d=groups.io; h=From:Date:Subject:MIME-Version:Message-Id:References:In-Reply-To:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20240206; t=1709725324; v=1; b=NnL0fZqLcW9MhejkvnaI8yraM0/EL5kLtjFeInRvGZTNmsU3DRLeSqoJYeiSLeIXIYjdOaDd zpfJz+72kBytp8u09BRDbiFjeXlsfwsUy02kmkU3yDNmc3AUrrqh2JhpeiZzdXOrCra3Yjs/8sP TQmaFHwz9xCsWuTACDmyfY3dE2PbFAuRk7f+3mYEqKrsgKLvqyrv/bM6WatVzj5VI+fCDSYBvAZ neSK8eSBkFKAEKzBTKJIZiZm5o36XZIZhZFZl9O2xY3BRlMW7a5RuxEASTs+Yr8WYzirqMEUs/K KvQTr1VtEudH8Xav5Dlcd8kTpbmqxIuuUoB5kg354lUOA== X-Received: by 127.0.0.2 with SMTP id L4U3YY7687511xJ6DzDnJAq4; Wed, 06 Mar 2024 03:42:04 -0800 X-Received: from muminek.juszkiewicz.com.pl (muminek.juszkiewicz.com.pl [213.251.184.221]) by mx.groups.io with SMTP id smtpd.web10.9884.1709725323184257332 for ; Wed, 06 Mar 2024 03:42:03 -0800 X-Received: from localhost (localhost [127.0.0.1]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTP id 38A9B260835; Wed, 6 Mar 2024 12:42:01 +0100 (CET) X-Virus-Scanned: Debian amavis at juszkiewicz.com.pl X-Received: from muminek.juszkiewicz.com.pl ([127.0.0.1]) by localhost (muminek.juszkiewicz.com.pl [127.0.0.1]) (amavis, port 10024) with ESMTP id rGj_OYBtgKdr; Wed, 6 Mar 2024 12:41:59 +0100 (CET) X-Received: from [172.17.0.1] (83.11.22.169.ipv4.supernova.orange.pl [83.11.22.169]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTPSA id CEE9A260B83; Wed, 6 Mar 2024 12:41:57 +0100 (CET) From: "Marcin Juszkiewicz" Date: Wed, 06 Mar 2024 03:42:03 -0800 Subject: [edk2-devel] [PATCH edk2-platforms v6 6/7] Platform/SbsaQemu: get the information of memory via SMC calls MIME-Version: 1.0 Message-Id: <20240306-no-dt-for-cpu-v6-6-acd8727a1b59@linaro.org> References: <20240306-no-dt-for-cpu-v6-0-acd8727a1b59@linaro.org> In-Reply-To: <20240306-no-dt-for-cpu-v6-0-acd8727a1b59@linaro.org> To: devel@edk2.groups.io Cc: Leif Lindholm , Ard Biesheuvel , Graeme Gregory , Xiong Yining , Chen Baozi , Marcin Juszkiewicz Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,marcin.juszkiewicz@linaro.org List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: pyEO3UNeFHjG4xAFVCjQ6Nm1x7686176AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=NnL0fZqL; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=linaro.org (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io From: Xiong Yining Provide functions to check for memory information: - amount of memory nodes - memory address - NUMA node id for memory Values are read from TF-A using platform specific SMC calls. Signed-off-by: Xiong Yining Signed-off-by: Chen Baozi --- .../SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf | 2 +- .../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h | 2 + .../Include/Library/SbsaQemuHardwareInfoLib.h | 28 ++++++++++ .../SbsaQemuHardwareInfoLib.c | 47 ++++++++++++++++= + .../Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c | 54 +++++-----------= ---- 5 files changed, 91 insertions(+), 42 deletions(-) diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf b/Si= licon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf index c067a80cc715..fb856efe4c27 100644 --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf @@ -32,9 +32,9 @@ [LibraryClasses] ArmLib BaseMemoryLib DebugLib - FdtLib MemoryAllocationLib PcdLib + SbsaQemuHardwareInfoLib =20 [Pcd] gArmTokenSpaceGuid.PcdSystemMemoryBase diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h b= /Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h index d9faee7fa5b2..e7bf54978d4e 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h @@ -16,6 +16,8 @@ #define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101) #define SIP_SVC_GET_CPU_COUNT SMC_SIP_FUNCTION_ID(200) #define SIP_SVC_GET_CPU_NODE SMC_SIP_FUNCTION_ID(201) +#define SIP_SVC_GET_MEMORY_NODE_COUNT SMC_SIP_FUNCTION_ID(300) +#define SIP_SVC_GET_MEMORY_NODE SMC_SIP_FUNCTION_ID(301) =20 /* * SMCC does not define return codes for SiP functions. diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuHardwareInfoLib.= h b/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuHardwareInfoLib.h index ca52c6b27093..0b71a3f7e6eb 100644 --- a/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuHardwareInfoLib.h +++ b/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuHardwareInfoLib.h @@ -9,6 +9,12 @@ #ifndef SBSA_QEMU_HARDWARE_INFO_ #define SBSA_QEMU_HARDWARE_INFO_ =20 +typedef struct{ + UINT32 NodeId; + UINT64 AddressBase; + UINT64 AddressSize; +} MemoryInfo; + /** Get CPU count from information passed by Qemu. =20 @@ -42,4 +48,26 @@ SbsaQemuGetCpuNumaNode ( IN UINTN CpuId ); =20 +/** + Get the number of memory node from device tree passed by Qemu. + + @retval the number of memory nodes. +**/ +UINT32 +SbsaQemuGetMemNodeCount ( + VOID + ); + +/** + Get memory infomation(node-id, addressbase, addresssize) for a given mem= ory node from device tree passed by Qemu. + + @param [in] MemoryId Index of memory to retrieve memory information= . + + @retval memory infomation for given memory node. +**/ +MemoryInfo +SbsaQemuGetMemInfo ( + IN UINTN MemoryId + ); + #endif /* SBSA_QEMU_HARDWARE_INFO_ */ diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemu= HardwareInfoLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/S= bsaQemuHardwareInfoLib.c index e1f1a9588b19..88b50e46c072 100644 --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwar= eInfoLib.c +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwar= eInfoLib.c @@ -201,3 +201,50 @@ SbsaQemuGetCpuNumaNode ( =20 return Arg0; } + +UINT32 +SbsaQemuGetMemNodeCount ( + VOID + ) +{ + UINTN SmcResult; + UINTN Arg0; + + SmcResult =3D ArmCallSmc0 (SIP_SVC_GET_MEMORY_NODE_COUNT, &Arg0, NULL, N= ULL); + if (SmcResult !=3D SMC_SIP_CALL_SUCCESS) { + DEBUG ((DEBUG_ERROR, "SIP_SVC_GET_MEMORY_NODE_COUNT call failed.\n")); + } + + DEBUG(( DEBUG_INFO, "The number of the memory nodes is %ld\n", Arg0)); + return (UINT32)Arg0; +} + +MemoryInfo +SbsaQemuGetMemInfo ( + IN UINTN MemoryId + ) +{ + UINTN SmcResult; + UINTN Arg0; + UINTN Arg1; + UINTN Arg2; + MemoryInfo MemInfo; + + Arg0 =3D MemoryId; + + SmcResult =3D ArmCallSmc1 (SIP_SVC_GET_MEMORY_NODE, &Arg0, &Arg1, &Arg2)= ; + if (SmcResult !=3D SMC_SIP_CALL_SUCCESS) { + DEBUG ((DEBUG_ERROR, "SIP_SVC_GET_MEMORY_NODE call failed.\n")); + } else { + MemInfo.NodeId =3D Arg0; + MemInfo.AddressBase =3D Arg1; + MemInfo.AddressSize =3D Arg2; + } + + DEBUG(( DEBUG_INFO, "NUMA node for System RAM:%d =3D 0x%lx - 0x%lx\n", + MemInfo.NodeId, + MemInfo.AddressBase, + MemInfo.AddressBase + MemInfo.AddressSize -1 )); + + return MemInfo; +} diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c b/Sili= con/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c index 8c2eb0b6a028..5a418a461174 100644 --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include =20 // Number of Virtual Memory Map Descriptors #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 4 @@ -23,53 +23,25 @@ SbsaQemuLibConstructor ( VOID ) { - VOID *DeviceTreeBase; - INT32 Node, Prev; UINT64 NewBase, CurBase; UINT64 NewSize, CurSize; - CONST CHAR8 *Type; - INT32 Len; - CONST UINT64 *RegProp; + UINT32 NumMemNodes; + UINT32 Index; + MemoryInfo MemInfo; RETURN_STATUS PcdStatus; =20 NewBase =3D 0; NewSize =3D 0; =20 - DeviceTreeBase =3D (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress); - ASSERT (DeviceTreeBase !=3D NULL); - - // Make sure we have a valid device tree blob - ASSERT (fdt_check_header (DeviceTreeBase) =3D=3D 0); - - // Look for the lowest memory node - for (Prev =3D 0;; Prev =3D Node) { - Node =3D fdt_next_node (DeviceTreeBase, Prev, NULL); - if (Node < 0) { - break; - } - - // Check for memory node - Type =3D fdt_getprop (DeviceTreeBase, Node, "device_type", &Len); - if (Type && AsciiStrnCmp (Type, "memory", Len) =3D=3D 0) { - // Get the 'reg' property of this node. For now, we will assume - // two 8 byte quantities for base and size, respectively. - RegProp =3D fdt_getprop (DeviceTreeBase, Node, "reg", &Len); - if (RegProp !=3D 0 && Len =3D=3D (2 * sizeof (UINT64))) { - - CurBase =3D fdt64_to_cpu (ReadUnaligned64 (RegProp)); - CurSize =3D fdt64_to_cpu (ReadUnaligned64 (RegProp + 1)); - - DEBUG ((DEBUG_INFO, "%a: System RAM @ 0x%lx - 0x%lx\n", - __FUNCTION__, CurBase, CurBase + CurSize - 1)); - - if (NewBase > CurBase || NewBase =3D=3D 0) { - NewBase =3D CurBase; - NewSize =3D CurSize; - } - } else { - DEBUG ((DEBUG_ERROR, "%a: Failed to parse FDT memory node\n", - __FUNCTION__)); - } + NumMemNodes =3D SbsaQemuGetMemNodeCount(); + for(Index =3D 0; Index < NumMemNodes; Index++){ + MemInfo =3D SbsaQemuGetMemInfo(Index); + CurBase =3D MemInfo.AddressBase; + CurSize =3D MemInfo.AddressSize; + + if (NewBase > CurBase || NewBase =3D=3D 0) { + NewBase =3D CurBase; + NewSize =3D CurSize; } } =20 --=20 2.44.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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