From: "Zhai, MingXin (Duke) via groups.io" <duke.zhai=amd.com@groups.io>
To: <devel@edk2.groups.io>
Cc: Abner Chang <abner.chang@amd.com>,
Igniculus Fu <igniculus.fu@amd.com>, Ken Yao <ken.yao@amd.com>,
Eric Xing <eric.xing@amd.com>
Subject: [edk2-devel] [PATCH 4/4] AMD/AmdPlatformPkg: Update FspWrapper UPD table for BIOS setup options
Date: Mon, 11 Mar 2024 00:22:33 -0700 [thread overview]
Message-ID: <20240311072130.861-5-duke.zhai@amd.com> (raw)
In-Reply-To: <20240311072130.861-1-duke.zhai@amd.com>
From: Duke Zhai <Duke.Zhai@amd.com>
BZ #:4728
1.Remove useless options like I2C enable
2.Add new option:SocVoltage
Cc: Abner Chang <abner.chang@amd.com>
Cc: Igniculus Fu <igniculus.fu@amd.com>
Reviewed-by: Ken Yao <ken.yao@amd.com>
Reviewed-by: Eric Xing <eric.xing@amd.com>
Signed-off-by: Duke Zhai <Duke.Zhai@amd.com>
---
.../edk2/Fsp2WrapperPkg/Include/FspmUpd.h | 71 ++++++++++---------
.../FspWrapperPlatformLibSample.c | 29 --------
2 files changed, 36 insertions(+), 64 deletions(-)
diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Include/FspmUpd.h b/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Include/FspmUpd.h
index 8cadbe430a..875461a58a 100644
--- a/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Include/FspmUpd.h
+++ b/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Include/FspmUpd.h
@@ -16,41 +16,42 @@
/** Fsp M Configuration
**/
typedef struct {
- /** Offset 0x0040**/ UINT32 bert_size;
- /** Offset 0x0044**/ UINT32 tseg_size;
- /** Offset 0x0048**/ UINT32 dxio_descriptor_table_pointer;
- /** Offset 0x004C**/ UINT32 pcie_reset_function_pointer;
- /** Offset 0x0050**/ UINT32 ddi_descriptor_table_pointer;
- /** Offset 0x0054**/ UINT32 temp_memory_base_addr;
- /** Offset 0x0058**/ UINT32 temp_memory_size;
- /** Offset 0x005C**/ UINT32 fsp_o_pei_volume_address;
- /** Offset 0x0060**/ UINT32 fsp_o_pei_upd_address;
- /** Offset 0x0064**/ UINT32 pei_reset_ppi_addr;
- /** Offset 0x0068**/ UINT32 resource_size_for_each_rb_ptr;
- /** Offset 0x006C**/ UINT32 resource_size_for_each_rb_size;
- /** Offset 0x0070**/ UINT32 total_number_of_root_bridges_ptr;
- /** Offset 0x0074**/ UINT32 total_number_of_root_bridges_size;
- /** Offset 0x0078**/ UINT32 amd_pbs_setup_ptr;
- /** Offset 0x007C**/ UINT32 amd_pbs_setup_size;
- /** Offset 0x0080**/ UINT32 ap_sync_flag_nv_ptr;
- /** Offset 0x0084**/ UINT32 ap_sync_flag_nv_size;
- /** Offset 0x0088**/ UINT8 DbgFchUsbUsb0DrdMode;
- /** Offset 0x0089**/ UINT8 DbgFchUsbUsb2DrdMode;
- /** Offset 0x008A**/ UINT32 CmnGnbGfxUmaFrameBufferSize;
- /** Offset 0x008E**/ UINT8 CmnGnbNbIOMMU;
- /** Offset 0x008F**/ UINT32 DbgFastPPTLimit;
- /** Offset 0x0093**/ UINT32 DbgSlowPPTLimit;
- /** Offset 0x0097**/ UINT32 CmnCpuVoltageOffset;
- /** Offset 0x009B**/ UINT32 CmnGpuVoltageOffset;
- /** Offset 0x009F**/ UINT32 CmnSocVoltageOffset;
- /** Offset 0x00A3**/ UINT8 CmnGnbGfxUmaMode;
- /** Offset 0x00A4**/ UINT8 CmnFchI2C0Config;
- /** Offset 0x00A5**/ UINT8 CmnFchI2C1Config;
- /** Offset 0x00A6**/ UINT8 CmnFchI2C2Config;
- /** Offset 0x00A7**/ UINT8 CmnFchI2C3Config;
- /** Offset 0x00A8**/ UINT32 ids_nv_table_address;
- /** Offset 0x00AC**/ UINT32 ids_nv_table_size;
- /** Offset 0x00B0**/ UINT16 UpdTerminator;
+ /** Offset 0x0040**/ UINT32 bert_size;
+ /** Offset 0x0044**/ UINT32 tseg_size;
+ /** Offset 0x0048**/ UINT32 dxio_descriptor_table_pointer;
+ /** Offset 0x004C**/ UINT32 pcie_reset_function_pointer;
+ /** Offset 0x0050**/ UINT32 ddi_descriptor_table_pointer;
+ /** Offset 0x0054**/ UINT32 temp_memory_base_addr;
+ /** Offset 0x0058**/ UINT32 temp_memory_size;
+ /** Offset 0x005C**/ UINT32 fsp_o_pei_volume_address;
+ /** Offset 0x0060**/ UINT32 fsp_o_pei_upd_address;
+ /** Offset 0x0064**/ UINT32 pei_reset_ppi_addr;
+ /** Offset 0x0068**/ UINT32 resource_size_for_each_rb_ptr;
+ /** Offset 0x006C**/ UINT32 resource_size_for_each_rb_size;
+ /** Offset 0x0070**/ UINT32 total_number_of_root_bridges_ptr;
+ /** Offset 0x0074**/ UINT32 total_number_of_root_bridges_size;
+ /** Offset 0x0078**/ UINT32 amd_pbs_setup_ptr;
+ /** Offset 0x007C**/ UINT32 amd_pbs_setup_size;
+ /** Offset 0x0080**/ UINT32 ap_sync_flag_nv_ptr;
+ /** Offset 0x0084**/ UINT32 ap_sync_flag_nv_size;
+ /** Offset 0x0088**/ UINT8 FchUsbUsb0DrdMode;
+ /** Offset 0x0089**/ UINT8 FchUsbUsb2DrdMode;
+ /** Offset 0x008A**/ UINT8 CmnGnbGfxUmaMode;
+ /** Offset 0x008B**/ UINT32 CmnGnbGfxUmaFrameBufferSize;
+ /** Offset 0x008F**/ UINT8 CmnGnbNbIOMMU;
+ /** Offset 0x0090**/ UINT8 PPTCtl;
+ /** Offset 0x0091**/ UINT32 FastPPTLimit;
+ /** Offset 0x0095**/ UINT32 SlowPPTLimit;
+ /** Offset 0x0099**/ UINT8 CmnCpuVolOffsetCtl;
+ /** Offset 0x009A**/ UINT32 CmnCpuVoltageOffset;
+ /** Offset 0x009E**/ UINT8 CmnGpuVolOffsetCtl;
+ /** Offset 0x009F**/ UINT32 CmnGpuVoltageOffset;
+ /** Offset 0x00A3**/ UINT8 CmnSocVolOffsetCtl;
+ /** Offset 0x00A4**/ UINT32 CmnSocVoltageOffset;
+ /** Offset 0x00A8**/ UINT16 CclkFmaxOverride;
+ /** Offset 0x00AA**/ UINT16 GfxclkFmaxOverride;
+ /** Offset 0x00AC**/ UINT8 padding1[8];
+ /** Offset 0x00B4**/ UINT16 UpdTerminator;
} FSP_M_CONFIG;
/** Fsp M UPD Configuration
diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Library/BaseFspWrapperPlatformLibSample/FspWrapperPlatformLibSample.c b/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Library/BaseFspWrapperPlatformLibSample/FspWrapperPlatformLibSample.c
index 1afcf68f85..2a616482e3 100644
--- a/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Library/BaseFspWrapperPlatformLibSample/FspWrapperPlatformLibSample.c
+++ b/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Library/BaseFspWrapperPlatformLibSample/FspWrapperPlatformLibSample.c
@@ -61,35 +61,6 @@ GetIdsNvData (
FSPM_UPD *volatile FspmUpd
)
{
- VOID *IdsNvTableData;
- UINT32 IdsNvDataSize = 0;
- IDS_HOOK_STATUS Status = GetIdsNvTable (NULL, &IdsNvDataSize);
-
- if ((Status == IDS_HOOK_BUFFER_TOO_SMALL) || (Status == IDS_HOOK_SUCCESS)) {
- // The CBS code doesn't follow its header!
- IdsNvTableData = AllocatePool (IdsNvDataSize+100);
- if (IdsNvTableData != NULL) {
- Status = GetIdsNvTable (IdsNvTableData, &IdsNvDataSize);
- if (Status == IDS_HOOK_SUCCESS) {
- FspmUpd->FspmConfig.ids_nv_table_address = (UINT32)(UINTN)IdsNvTableData;
- FspmUpd->FspmConfig.ids_nv_table_size = IdsNvDataSize;
- DEBUG ((
- DEBUG_INFO,
- "IDS NV Table address:%x, size:%x\n", \
- FspmUpd->FspmConfig.ids_nv_table_address,
- FspmUpd->FspmConfig.ids_nv_table_size
- ));
- return EFI_SUCCESS;
- } else {
- DEBUG ((DEBUG_ERROR, "Get NV Table #3:%d\n", Status));
- }
- } else {
- DEBUG ((DEBUG_ERROR, "Get NV Table #2:%d\n", Status));
- }
- } else {
- DEBUG ((DEBUG_ERROR, "Get NV Table #1:%d\n", Status));
- }
-
return EFI_UNSUPPORTED;
}
--
2.31.1
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prev parent reply other threads:[~2024-03-11 7:22 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-11 7:22 [edk2-devel] [PATCH 0/4] Update Vangogh platform reference code Zhai, MingXin (Duke) via groups.io
2024-03-11 7:22 ` [edk2-devel] [PATCH 1/4] AMD/AmdPlatformPkg: Use HpetTimerDxe to replace 8254Timer Zhai, MingXin (Duke) via groups.io
2024-03-11 7:22 ` [edk2-devel] [PATCH 2/4] AMD/AmdPlatformPkg: Fix Bug Microcode version cannot show correctly at BIOS setup Zhai, MingXin (Duke) via groups.io
2024-03-11 7:22 ` [edk2-devel] [PATCH 3/4] AMD/AmdPlatformPkg: Enable capsule at linux build Zhai, MingXin (Duke) via groups.io
2024-03-11 7:22 ` Zhai, MingXin (Duke) via groups.io [this message]
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