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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C X-Received: from SATLEXMB04.amd.com (165.204.84.17) by CH3PEPF0000000E.mail.protection.outlook.com (10.167.244.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7386.12 via Frontend Transport; Mon, 11 Mar 2024 07:22:30 +0000 X-Received: from SHA-LX-MINGXZHA.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 11 Mar 2024 02:22:28 -0500 From: "Zhai, MingXin (Duke) via groups.io" To: CC: Abner Chang , Igniculus Fu , Ken Yao , Eric Xing Subject: [edk2-devel] [PATCH 4/4] AMD/AmdPlatformPkg: Update FspWrapper UPD table for BIOS setup options Date: Mon, 11 Mar 2024 00:22:33 -0700 Message-ID: <20240311072130.861-5-duke.zhai@amd.com> In-Reply-To: <20240311072130.861-1-duke.zhai@amd.com> References: <20240311072130.861-1-duke.zhai@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000E:EE_|IA1PR12MB6484:EE_ X-MS-Office365-Filtering-Correlation-Id: ee626c80-0ded-4189-e90b-08dc419c0353 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: wbNf9qL23COZBS+jizNJ3I50yfDzANUna47ruiEDHPxfrFKX3HaqSht8Y/Pla/uUvEfvVq+Ko4Rm9iwQAJdSKqyvnfTBv5H6+Z6Y8S23mXNA2vx12NOzUhLhbhcW8qjpipezu8nYsG03gZp37DcuEJmAsg4oRP20w+QBxxeQ5rhcYLhmLIefv/V0nsUS+CSiiBUDCKWiuJNcLmk0PGC/EZzS7zv9mkUsdzcxxFFjwQo+ujyMHnt1OQmUb1yZjuBtA2Asz/B0MdoVzFDEoxbty/PWF0klF+4AWoJtriJpXSv1yHqrxZ3dfFtVdjnGBpZ4BpHUMfm1YS7C+fpv3JVv4/pyVXsYsTKL5h63lYs2nPBIK1u/ltP/efegMXwSTVZehmKjpB+6vZDWRv5KecBwWf/T5JkT6/XWpUWxoWXVer3NHLR13IsG79YgCTrWD/8JPqLlAbdnh+lKvkKtTu0vPBrK/Mu0oQbkA8nqtIT545RXhwJOCqUaXdt3wpomVtrQ8gjUa1O8QvzLOYP0/rbL0dy4RBvFe2e4thi5kuBv7cyAItD6ZMUubfu4FSfC4Kwsu3nQHbslhgK+Wud3sT0+S+vcwADX3/u/1bVrGe6xn7RYhxtDGaKzWGuDoIx6phxA/4IVjIBcBrLOYEUHr2W2esEsVxcDb0IgMx0zNPDzRsnjCcqu8/E/LM65owpuoobRlWdq0KQqj8UuL7xzrnEZDberwLQunl+9vfJgElnj/ggbEAVzfAgZC2J8nxIbz6Db X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Mar 2024 07:22:30.5520 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ee626c80-0ded-4189-e90b-08dc419c0353 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6484 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,duke.zhai@amd.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: ozJoXQe8KBt48K4qs9U6HH6tx7686176AA= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=U8i1A+WS; dmarc=pass (policy=none) header.from=groups.io; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io From: Duke Zhai BZ #:4728 1.Remove useless options like I2C enable 2.Add new option:SocVoltage Cc: Abner Chang Cc: Igniculus Fu Reviewed-by: Ken Yao Reviewed-by: Eric Xing Signed-off-by: Duke Zhai --- .../edk2/Fsp2WrapperPkg/Include/FspmUpd.h | 71 ++++++++++--------- .../FspWrapperPlatformLibSample.c | 29 -------- 2 files changed, 36 insertions(+), 64 deletions(-) diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Include= /FspmUpd.h b/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Include= /FspmUpd.h index 8cadbe430a..875461a58a 100644 --- a/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Include/FspmUp= d.h +++ b/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Include/FspmUp= d.h @@ -16,41 +16,42 @@ /** Fsp M Configuration **/ typedef struct { - /** Offset 0x0040**/ UINT32 bert_size; - /** Offset 0x0044**/ UINT32 tseg_size; - /** Offset 0x0048**/ UINT32 dxio_descriptor_table_pointer; - /** Offset 0x004C**/ UINT32 pcie_reset_function_pointer; - /** Offset 0x0050**/ UINT32 ddi_descriptor_table_pointer; - /** Offset 0x0054**/ UINT32 temp_memory_base_addr; - /** Offset 0x0058**/ UINT32 temp_memory_size; - /** Offset 0x005C**/ UINT32 fsp_o_pei_volume_address; - /** Offset 0x0060**/ UINT32 fsp_o_pei_upd_address; - /** Offset 0x0064**/ UINT32 pei_reset_ppi_addr; - /** Offset 0x0068**/ UINT32 resource_size_for_each_rb_ptr; - /** Offset 0x006C**/ UINT32 resource_size_for_each_rb_size; - /** Offset 0x0070**/ UINT32 total_number_of_root_bridges_ptr; - /** Offset 0x0074**/ UINT32 total_number_of_root_bridges_size; - /** Offset 0x0078**/ UINT32 amd_pbs_setup_ptr; - /** Offset 0x007C**/ UINT32 amd_pbs_setup_size; - /** Offset 0x0080**/ UINT32 ap_sync_flag_nv_ptr; - /** Offset 0x0084**/ UINT32 ap_sync_flag_nv_size; - /** Offset 0x0088**/ UINT8 DbgFchUsbUsb0DrdMode; - /** Offset 0x0089**/ UINT8 DbgFchUsbUsb2DrdMode; - /** Offset 0x008A**/ UINT32 CmnGnbGfxUmaFrameBufferSize; - /** Offset 0x008E**/ UINT8 CmnGnbNbIOMMU; - /** Offset 0x008F**/ UINT32 DbgFastPPTLimit; - /** Offset 0x0093**/ UINT32 DbgSlowPPTLimit; - /** Offset 0x0097**/ UINT32 CmnCpuVoltageOffset; - /** Offset 0x009B**/ UINT32 CmnGpuVoltageOffset; - /** Offset 0x009F**/ UINT32 CmnSocVoltageOffset; - /** Offset 0x00A3**/ UINT8 CmnGnbGfxUmaMode; - /** Offset 0x00A4**/ UINT8 CmnFchI2C0Config; - /** Offset 0x00A5**/ UINT8 CmnFchI2C1Config; - /** Offset 0x00A6**/ UINT8 CmnFchI2C2Config; - /** Offset 0x00A7**/ UINT8 CmnFchI2C3Config; - /** Offset 0x00A8**/ UINT32 ids_nv_table_address; - /** Offset 0x00AC**/ UINT32 ids_nv_table_size; - /** Offset 0x00B0**/ UINT16 UpdTerminator; + /** Offset 0x0040**/ UINT32 bert_size; + /** Offset 0x0044**/ UINT32 tseg_size; + /** Offset 0x0048**/ UINT32 dxio_descriptor_table_po= inter; + /** Offset 0x004C**/ UINT32 pcie_reset_function_poin= ter; + /** Offset 0x0050**/ UINT32 ddi_descriptor_table_poi= nter; + /** Offset 0x0054**/ UINT32 temp_memory_base_addr; + /** Offset 0x0058**/ UINT32 temp_memory_size; + /** Offset 0x005C**/ UINT32 fsp_o_pei_volume_address= ; + /** Offset 0x0060**/ UINT32 fsp_o_pei_upd_address; + /** Offset 0x0064**/ UINT32 pei_reset_ppi_addr; + /** Offset 0x0068**/ UINT32 resource_size_for_each_r= b_ptr; + /** Offset 0x006C**/ UINT32 resource_size_for_each_r= b_size; + /** Offset 0x0070**/ UINT32 total_number_of_root_bri= dges_ptr; + /** Offset 0x0074**/ UINT32 total_number_of_root_bri= dges_size; + /** Offset 0x0078**/ UINT32 amd_pbs_setup_ptr; + /** Offset 0x007C**/ UINT32 amd_pbs_setup_size; + /** Offset 0x0080**/ UINT32 ap_sync_flag_nv_ptr; + /** Offset 0x0084**/ UINT32 ap_sync_flag_nv_size; + /** Offset 0x0088**/ UINT8 FchUsbUsb0DrdMode; + /** Offset 0x0089**/ UINT8 FchUsbUsb2DrdMode; + /** Offset 0x008A**/ UINT8 CmnGnbGfxUmaMode; + /** Offset 0x008B**/ UINT32 CmnGnbGfxUmaFrameBufferS= ize; + /** Offset 0x008F**/ UINT8 CmnGnbNbIOMMU; + /** Offset 0x0090**/ UINT8 PPTCtl; + /** Offset 0x0091**/ UINT32 FastPPTLimit; + /** Offset 0x0095**/ UINT32 SlowPPTLimit; + /** Offset 0x0099**/ UINT8 CmnCpuVolOffsetCtl; + /** Offset 0x009A**/ UINT32 CmnCpuVoltageOffset; + /** Offset 0x009E**/ UINT8 CmnGpuVolOffsetCtl; + /** Offset 0x009F**/ UINT32 CmnGpuVoltageOffset; + /** Offset 0x00A3**/ UINT8 CmnSocVolOffsetCtl; + /** Offset 0x00A4**/ UINT32 CmnSocVoltageOffset; + /** Offset 0x00A8**/ UINT16 CclkFmaxOverride; + /** Offset 0x00AA**/ UINT16 GfxclkFmaxOverride; + /** Offset 0x00AC**/ UINT8 padding1[8]; + /** Offset 0x00B4**/ UINT16 UpdTerminator; } FSP_M_CONFIG; /** Fsp M UPD Configuration diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Library= /BaseFspWrapperPlatformLibSample/FspWrapperPlatformLibSample.c b/Platform/A= MD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Library/BaseFspWrapperPlatform= LibSample/FspWrapperPlatformLibSample.c index 1afcf68f85..2a616482e3 100644 --- a/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Library/BaseFs= pWrapperPlatformLibSample/FspWrapperPlatformLibSample.c +++ b/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Library/BaseFs= pWrapperPlatformLibSample/FspWrapperPlatformLibSample.c @@ -61,35 +61,6 @@ GetIdsNvData ( FSPM_UPD *volatile FspmUpd ) { - VOID *IdsNvTableData; - UINT32 IdsNvDataSize =3D 0; - IDS_HOOK_STATUS Status =3D GetIdsNvTable (NULL, &IdsNvDataSize); - - if ((Status =3D=3D IDS_HOOK_BUFFER_TOO_SMALL) || (Status =3D=3D IDS_HOOK= _SUCCESS)) { - // The CBS code doesn't follow its header! - IdsNvTableData =3D AllocatePool (IdsNvDataSize+100); - if (IdsNvTableData !=3D NULL) { - Status =3D GetIdsNvTable (IdsNvTableData, &IdsNvDataSize); - if (Status =3D=3D IDS_HOOK_SUCCESS) { - FspmUpd->FspmConfig.ids_nv_table_address =3D (UINT32)(UINTN)IdsNvT= ableData; - FspmUpd->FspmConfig.ids_nv_table_size =3D IdsNvDataSize; - DEBUG (( - DEBUG_INFO, - "IDS NV Table address:%x, size:%x\n", \ - FspmUpd->FspmConfig.ids_nv_table_address, - FspmUpd->FspmConfig.ids_nv_table_size - )); - return EFI_SUCCESS; - } else { - DEBUG ((DEBUG_ERROR, "Get NV Table #3:%d\n", Status)); - } - } else { - DEBUG ((DEBUG_ERROR, "Get NV Table #2:%d\n", Status)); - } - } else { - DEBUG ((DEBUG_ERROR, "Get NV Table #1:%d\n", Status)); - } - return EFI_UNSUPPORTED; } -- 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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