[edk2-devel] [PATCH] MdeModulePkg/XhciDxe: Increase 1ms extra delay for xHCI issue HCRST

["Chiu, Ian" <ian.chiu@intel.com>]

From: Ian Chiu <ian.chiu@intel.com>

https://bugzilla.tianocore.org/show_bug.cgi?id=4727

More and more XHCI host controllers require to have extra 1ms
delay before accessing any MMIO register during reset.

Since PHY transition from P3 to P0 can take around 1.3ms and
the xHCI reset can take around 1.5ms.

Hence, need delay increase between issuing HCRST on xHCI
controller till first MMIO read for reset completion check.

Cc: Hao A Wu     <hao.a.wu@intel.com>
Cc: Ray Ni       <ray.ni@intel.com>
Cc: More Shih    <more.shih@intel.com>
Signed-off-by: Ian Chiu <ian.chiu@intel.com>
---
 MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
index 40f2f1f227..eafe4b0d11 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
@@ -861,10 +861,11 @@ XhcResetHC (
     XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);
     //
     // Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during reset.
+    // PHY transition from P3 to P0 can take around 1.3ms and the xHCI reset can take around 1.5ms.
     // Otherwise there may have the timeout case happened.
-    // The below is a workaround to solve such problem.
+    // Stall for 2ms workaround to solve such problem.
     //
-    gBS->Stall (XHC_1_MILLISECOND);
+    gBS->Stall (XHC_1_MILLISECOND*2);
     Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);
 
     if (!EFI_ERROR (Status)) {
-- 
2.38.1.windows.1



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