From: "Tuan Phan" <tphan@ventanamicro.com>
To: devel@edk2.groups.io
Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn,
zhiguang.liu@intel.com, kraxel@redhat.com, lersek@redhat.com,
rahul1.kumar@intel.com, ray.ni@intel.com,
sunilvl@ventanamicro.com, jiewen.yao@intel.com,
andrei.warkentin@intel.com, ardb+tianocore@kernel.org,
Tuan Phan <tphan@ventanamicro.com>
Subject: [edk2-devel] [PATCH v4 2/4] UefiCpuPkg: RISC-V: MMU: Explictly use UINT64 instead of UINTN
Date: Thu, 14 Mar 2024 13:19:15 -0700 [thread overview]
Message-ID: <20240314201917.1756-3-tphan@ventanamicro.com> (raw)
In-Reply-To: <20240314201917.1756-1-tphan@ventanamicro.com>
While UINTN defined for RISC-V 64 bits is UINT64, explictly using UINT64
for those variables that clearly are UINT64.
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
---
.../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 158 +++++++++---------
1 file changed, 76 insertions(+), 82 deletions(-)
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
index 826a1d32a1d4..46ba4b4709b1 100644
--- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
@@ -65,7 +65,7 @@ RiscVMmuEnabled (
**/
STATIC
-UINTN
+UINT64
RiscVGetRootTranslateTable (
VOID
)
@@ -86,7 +86,7 @@ RiscVGetRootTranslateTable (
STATIC
BOOLEAN
IsValidPte (
- IN UINTN Entry
+ IN UINT64 Entry
)
{
if (((Entry & RISCV_PG_V) == 0) ||
@@ -107,9 +107,9 @@ IsValidPte (
**/
STATIC
-UINTN
+UINT64
SetValidPte (
- IN UINTN Entry
+ IN UINT64 Entry
)
{
/* Set Valid and Global mapping bits */
@@ -128,7 +128,7 @@ SetValidPte (
STATIC
BOOLEAN
IsBlockEntry (
- IN UINTN Entry
+ IN UINT64 Entry
)
{
return IsValidPte (Entry) &&
@@ -147,7 +147,7 @@ IsBlockEntry (
STATIC
BOOLEAN
IsTableEntry (
- IN UINTN Entry
+ IN UINT64 Entry
)
{
return IsValidPte (Entry) &&
@@ -163,13 +163,13 @@ IsTableEntry (
**/
STATIC
-UINTN
+UINT64
SetTableEntry (
- IN UINTN Entry
+ IN UINT64 Entry
)
{
Entry = SetValidPte (Entry);
- Entry &= ~(RISCV_PG_X | RISCV_PG_W | RISCV_PG_R);
+ Entry &= ~(UINT64)(RISCV_PG_X | RISCV_PG_W | RISCV_PG_R);
return Entry;
}
@@ -186,9 +186,9 @@ SetTableEntry (
STATIC
VOID
ReplaceTableEntry (
- IN UINTN *Entry,
- IN UINTN Value,
- IN UINTN RegionStart,
+ IN UINT64 *Entry,
+ IN UINT64 Value,
+ IN UINT64 RegionStart,
IN BOOLEAN IsLiveBlockMapping
)
{
@@ -208,9 +208,9 @@ ReplaceTableEntry (
**/
STATIC
-UINTN
+UINT64
GetPpnfromPte (
- IN UINTN Entry
+ IN UINT64 Entry
)
{
return ((Entry & PTE_PPN_MASK) >> PTE_PPN_SHIFT);
@@ -226,13 +226,13 @@ GetPpnfromPte (
**/
STATIC
-UINTN
+UINT64
SetPpnToPte (
- UINTN Entry,
- UINTN Address
+ UINT64 Entry,
+ UINT64 Address
)
{
- UINTN Ppn;
+ UINT64 Ppn;
Ppn = ((Address >> RISCV_MMU_PAGE_SHIFT) << PTE_PPN_SHIFT);
ASSERT (~(Ppn & ~PTE_PPN_MASK));
@@ -250,8 +250,8 @@ SetPpnToPte (
STATIC
VOID
FreePageTablesRecursive (
- IN UINTN *TranslationTable,
- IN UINTN Level
+ IN UINT64 *TranslationTable,
+ IN UINTN Level
)
{
UINTN Index;
@@ -260,8 +260,8 @@ FreePageTablesRecursive (
for (Index = 0; Index < mTableEntryCount; Index++) {
if (IsTableEntry (TranslationTable[Index])) {
FreePageTablesRecursive (
- (UINTN *)(GetPpnfromPte ((TranslationTable[Index])) <<
- RISCV_MMU_PAGE_SHIFT),
+ (UINT64 *)(GetPpnfromPte ((TranslationTable[Index])) <<
+ RISCV_MMU_PAGE_SHIFT),
Level + 1
);
}
@@ -289,22 +289,22 @@ FreePageTablesRecursive (
STATIC
EFI_STATUS
UpdateRegionMappingRecursive (
- IN UINTN RegionStart,
- IN UINTN RegionEnd,
- IN UINTN AttributeSetMask,
- IN UINTN AttributeClearMask,
- IN UINTN *PageTable,
+ IN UINT64 RegionStart,
+ IN UINT64 RegionEnd,
+ IN UINT64 AttributeSetMask,
+ IN UINT64 AttributeClearMask,
+ IN UINT64 *PageTable,
IN UINTN Level,
IN BOOLEAN TableIsLive
)
{
EFI_STATUS Status;
- UINTN BlockShift;
- UINTN BlockMask;
- UINTN BlockEnd;
- UINTN *Entry;
- UINTN EntryValue;
- UINTN *TranslationTable;
+ UINT64 BlockShift;
+ UINT64 BlockMask;
+ UINT64 BlockEnd;
+ UINT64 *Entry;
+ UINT64 EntryValue;
+ UINT64 *TranslationTable;
BOOLEAN NextTableIsLive;
ASSERT (Level < mMaxRootTableLevel);
@@ -313,18 +313,16 @@ UpdateRegionMappingRecursive (
BlockShift = (mMaxRootTableLevel - Level - 1) * mBitPerLevel + RISCV_MMU_PAGE_SHIFT;
BlockMask = MAX_ADDRESS >> (64 - BlockShift);
- DEBUG (
- (
- DEBUG_VERBOSE,
- "%a(%d): %llx - %llx set %lx clr %lx\n",
- __func__,
- Level,
- RegionStart,
- RegionEnd,
- AttributeSetMask,
- AttributeClearMask
- )
- );
+ DEBUG ((
+ DEBUG_VERBOSE,
+ "%a(%d): %LX - %LX set %LX clr %LX\n",
+ __func__,
+ Level,
+ RegionStart,
+ RegionEnd,
+ AttributeSetMask,
+ AttributeClearMask
+ ));
for ( ; RegionStart < RegionEnd; RegionStart = BlockEnd) {
BlockEnd = MIN (RegionEnd, (RegionStart | BlockMask) + 1);
@@ -380,7 +378,7 @@ UpdateRegionMappingRecursive (
NextTableIsLive = FALSE;
} else {
- TranslationTable = (UINTN *)(GetPpnfromPte (*Entry) << RISCV_MMU_PAGE_SHIFT);
+ TranslationTable = (UINT64 *)(GetPpnfromPte (*Entry) << RISCV_MMU_PAGE_SHIFT);
NextTableIsLive = TableIsLive;
}
@@ -412,7 +410,7 @@ UpdateRegionMappingRecursive (
}
if (!IsTableEntry (*Entry)) {
- EntryValue = SetPpnToPte (0, (UINTN)TranslationTable);
+ EntryValue = SetPpnToPte (0, (UINT64)TranslationTable);
EntryValue = SetTableEntry (EntryValue);
ReplaceTableEntry (
Entry,
@@ -463,11 +461,11 @@ UpdateRegionMappingRecursive (
STATIC
EFI_STATUS
UpdateRegionMapping (
- IN UINTN RegionStart,
- IN UINTN RegionLength,
- IN UINTN AttributeSetMask,
- IN UINTN AttributeClearMask,
- IN UINTN *RootTable,
+ IN UINT64 RegionStart,
+ IN UINT64 RegionLength,
+ IN UINT64 AttributeSetMask,
+ IN UINT64 AttributeClearMask,
+ IN UINT64 *RootTable,
IN BOOLEAN TableIsLive
)
{
@@ -495,23 +493,23 @@ UpdateRegionMapping (
**/
STATIC
-UINTN
+UINT64
GcdAttributeToPageAttribute (
- IN UINTN GcdAttributes
+ IN UINT64 GcdAttributes
)
{
- UINTN RiscVAttributes;
+ UINT64 RiscVAttributes;
RiscVAttributes = RISCV_PG_R | RISCV_PG_W | RISCV_PG_X;
// Determine protection attributes
if ((GcdAttributes & EFI_MEMORY_RO) != 0) {
- RiscVAttributes &= ~(RISCV_PG_W);
+ RiscVAttributes &= ~(UINT64)(RISCV_PG_W);
}
// Process eXecute Never attribute
if ((GcdAttributes & EFI_MEMORY_XP) != 0) {
- RiscVAttributes &= ~RISCV_PG_X;
+ RiscVAttributes &= ~(UINT64)RISCV_PG_X;
}
return RiscVAttributes;
@@ -533,11 +531,11 @@ EFI_STATUS
EFIAPI
RiscVSetMemoryAttributes (
IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINTN Length,
- IN UINTN Attributes
+ IN UINT64 Length,
+ IN UINT64 Attributes
)
{
- UINTN PageAttributesSet;
+ UINT64 PageAttributesSet;
PageAttributesSet = GcdAttributeToPageAttribute (Attributes);
@@ -560,7 +558,7 @@ RiscVSetMemoryAttributes (
Length,
PageAttributesSet,
PTE_ATTRIBUTES_MASK,
- (UINTN *)RiscVGetRootTranslateTable (),
+ (UINT64 *)RiscVGetRootTranslateTable (),
TRUE
);
}
@@ -583,8 +581,8 @@ RiscVMmuSetSatpMode (
)
{
VOID *TranslationTable;
- UINTN SatpReg;
- UINTN Ppn;
+ UINT64 SatpReg;
+ UINT64 Ppn;
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemoryMap;
UINTN NumberOfDescriptors;
UINTN Index;
@@ -622,7 +620,7 @@ RiscVMmuSetSatpMode (
return EFI_OUT_OF_RESOURCES;
}
- ZeroMem (TranslationTable, mTableEntryCount * sizeof (UINTN));
+ ZeroMem (TranslationTable, mTableEntryCount * sizeof (UINT64));
NumberOfDescriptors = 0;
MemoryMap = NULL;
@@ -662,7 +660,7 @@ RiscVMmuSetSatpMode (
DisableInterrupts ();
}
- Ppn = (UINTN)TranslationTable >> RISCV_MMU_PAGE_SHIFT;
+ Ppn = (UINT64)TranslationTable >> RISCV_MMU_PAGE_SHIFT;
ASSERT (!(Ppn & ~(SATP64_PPN)));
SatpReg = Ppn;
@@ -671,14 +669,12 @@ RiscVMmuSetSatpMode (
RiscVSetSupervisorAddressTranslationRegister (SatpReg);
/* Check if HW support the setup satp mode */
if (SatpReg != RiscVGetSupervisorAddressTranslationRegister ()) {
- DEBUG (
- (
- DEBUG_VERBOSE,
- "%a: HW does not support SATP mode:%d\n",
- __func__,
- SatpMode
- )
- );
+ DEBUG ((
+ DEBUG_VERBOSE,
+ "%a: HW does not support SATP mode:%d\n",
+ __func__,
+ SatpMode
+ ));
FreePageTablesRecursive (TranslationTable, 0);
return EFI_DEVICE_ERROR;
}
@@ -706,7 +702,7 @@ RiscVConfigureMmu (
)
{
EFI_STATUS Status;
- INTN Idx;
+ UINTN Idx;
Status = EFI_SUCCESS;
@@ -719,14 +715,12 @@ RiscVConfigureMmu (
return Status;
}
- DEBUG (
- (
- DEBUG_INFO,
- "%a: SATP mode %d successfully configured\n",
- __func__,
- mModeSupport[Idx]
- )
- );
+ DEBUG ((
+ DEBUG_INFO,
+ "%a: SATP mode %d successfully configured\n",
+ __func__,
+ mModeSupport[Idx]
+ ));
break;
}
--
2.25.1
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next prev parent reply other threads:[~2024-03-14 20:19 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-14 20:19 [edk2-devel] [PATCH v4 0/4] RISC-V: Support Svpbmt extension Tuan Phan
2024-03-14 20:19 ` [edk2-devel] [PATCH v4 1/4] MdePkg.dec: RISC-V: Define override bit for " Tuan Phan
2024-03-18 13:02 ` Sunil V L
2024-03-14 20:19 ` Tuan Phan [this message]
2024-03-14 20:19 ` [edk2-devel] [PATCH v4 3/4] UefiCpuPkg: RISC-V: MMU: Support " Tuan Phan
2024-03-18 13:00 ` Sunil V L
2024-03-19 16:44 ` Tuan Phan
[not found] ` <17BE38330B281CA5.29196@groups.io>
2024-04-02 22:42 ` Tuan Phan
2024-04-08 4:47 ` Sunil V L
2024-03-14 20:19 ` [edk2-devel] [PATCH v4 4/4] OvmfPkg/RiscVVirt: Disable " Tuan Phan
2024-03-18 13:01 ` Sunil V L
2024-04-08 5:45 ` [edk2-devel] [PATCH v4 0/4] RISC-V: Support " Sunil V L
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