From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 3FBCF941A78 for ; Wed, 20 Mar 2024 13:15:48 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=lxsQmNNYbF430lz2QIQEHgWkNtpso0LOT442Y2k10Jo=; c=relaxed/simple; d=groups.io; h=From:Date:Subject:MIME-Version:Message-Id:References:In-Reply-To:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20240206; t=1710940546; v=1; b=ZQCyi4K+wWcjYZu4rq6kMRMfejqUCjrnKUUEAHgVYzNJmBJiCnXS+nJR3yth0Sr+h0UwCsSV aB6RJtCg5rSVdrFSSLwQkQgDp2MTuWZ82XENZ/EInpF1CdfbnE/+nxwN88Rf39ctkFW+idPBvjL AoY+I6k5ml9HBaLyiPitMdVTOYlB+Ag9muwTlUW9yfB3pD/g3U1jIQzd3dLfc6BCduNc9EG7L6y TtSmskdPYPZ5nwre8f0A62TSmL78DWmxh5vGBBlpJVfXpEX6m7rw//c10IdVyi1j+yDr9WRqT7L SYh57ZKB3glFXkqF3swEasKyo2uu10m4eSQNqiMKKwPxA== X-Received: by 127.0.0.2 with SMTP id qMZKYY7687511xHdc02A2186; Wed, 20 Mar 2024 06:15:46 -0700 X-Received: from muminek.juszkiewicz.com.pl (muminek.juszkiewicz.com.pl [213.251.184.221]) by mx.groups.io with SMTP id smtpd.web10.44064.1710940545839487225 for ; Wed, 20 Mar 2024 06:15:46 -0700 X-Received: from localhost (localhost [127.0.0.1]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTP id E913D260FE6; Wed, 20 Mar 2024 14:15:42 +0100 (CET) X-Virus-Scanned: Debian amavis at juszkiewicz.com.pl X-Received: from muminek.juszkiewicz.com.pl ([127.0.0.1]) by localhost (muminek.juszkiewicz.com.pl [127.0.0.1]) (amavis, port 10024) with ESMTP id zUIqDMB_FD_j; Wed, 20 Mar 2024 14:15:41 +0100 (CET) X-Received: from [172.17.0.1] (83.11.22.169.ipv4.supernova.orange.pl [83.11.22.169]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTPSA id BBA5D260835; Wed, 20 Mar 2024 14:15:39 +0100 (CET) From: "Marcin Juszkiewicz" Date: Wed, 20 Mar 2024 14:15:32 +0100 Subject: [edk2-devel] [PATCH edk2-platforms v8 1/4] Platform/SbsaQemu: add SbsaQemuHardwareInfoLib MIME-Version: 1.0 Message-Id: <20240320-no-dt-for-cpu-v8-1-599ba99861ec@linaro.org> References: <20240320-no-dt-for-cpu-v8-0-599ba99861ec@linaro.org> In-Reply-To: <20240320-no-dt-for-cpu-v8-0-599ba99861ec@linaro.org> To: devel@edk2.groups.io Cc: Leif Lindholm , Ard Biesheuvel , Graeme Gregory , Xiong Yining , Chen Baozi , Marcin Juszkiewicz Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Wed, 20 Mar 2024 06:15:46 -0700 Reply-To: devel@edk2.groups.io,marcin.juszkiewicz@linaro.org List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: IBf8B1qWDWtlNjbNSsqx6Za2x7686176AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=ZQCyi4K+; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=linaro.org (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io This library provides functions to check for hardware information. For now it covers CPU ones: - amount of cpu cores - MPIDR value for cpu core - NUMA node id for cpu core Values are read from TF-A using platform specific SMC calls. Signed-off-by: Marcin Juszkiewicz --- Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 2 + Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 3 +- .../SbsaQemuHardwareInfoLib.inf | 29 ++++++ .../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h | 17 +++- .../Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h | 45 +++++++++ .../SbsaQemuHardwareInfoLib.c | 96 ++++++++++++++++= ++++ 6 files changed, 187 insertions(+), 5 deletions(-) diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/Sbs= aQemu.dec index 913d1d75ef29..427ff8b31aac 100644 --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec @@ -12,6 +12,8 @@ [Defines] PACKAGE_GUID =3D 8db32c5a-2821-43e2-b4ac-bc148e2b0b05 PACKAGE_VERSION =3D 0.1 =20 +[LibraryClasses] +HardwareInfoLib|Include/Library/HardwareInfoLib.h ##########################################################################= ###### # # Include Section - list of Include Paths that are provided by this packag= e. diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/S= bsaQemu.dsc index 378600050df9..3c3d2449bff4 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc @@ -1,6 +1,6 @@ # # Copyright (c) 2021, NUVIA Inc. All rights reserved. -# Copyright (c) 2019, Linaro Limited. All rights reserved. +# Copyright (c) 2019-2024, Linaro Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -128,6 +128,7 @@ [LibraryClasses.common] =20 FdtHelperLib|Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf OemMiscLib|Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf + HardwareInfoLib|Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/Sb= saQemuHardwareInfoLib.inf =20 # Debug Support PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCof= fExtraActionLib.inf diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemu= HardwareInfoLib.inf b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib= /SbsaQemuHardwareInfoLib.inf new file mode 100644 index 000000000000..2acb2a1e7c76 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwar= eInfoLib.inf @@ -0,0 +1,29 @@ +#/* @file +# +# Copyright (c) 2024, Linaro Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#*/ + +[Defines] + INF_VERSION =3D 0x0001001c + BASE_NAME =3D SbsaQemuHardwareInfoLib + FILE_GUID =3D 6454006f-6502-46e2-9be4-4bba8d4b29fb + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D HardwareInfoLib + +[Sources] + SbsaQemuHardwareInfoLib.c + +[Packages] + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Qemu/SbsaQemu/SbsaQemu.dec + +[LibraryClasses] + ArmSmcLib + ResetSystemLib diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h b= /Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h index 7934875e4aba..2317c1f0ae69 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2023, Linaro Ltd. All rights reserved.
+* Copyright (c) 2023-2024, Linaro Ltd. All rights reserved.
* * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -11,8 +11,17 @@ =20 #include =20 -#define SIP_SVC_VERSION SMC_SIP_FUNCTION_ID(1) -#define SIP_SVC_GET_GIC SMC_SIP_FUNCTION_ID(100) -#define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101) +#define SIP_SVC_VERSION SMC_SIP_FUNCTION_ID(1) +#define SIP_SVC_GET_GIC SMC_SIP_FUNCTION_ID(100) +#define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101) +#define SIP_SVC_GET_CPU_COUNT SMC_SIP_FUNCTION_ID(200) +#define SIP_SVC_GET_CPU_NODE SMC_SIP_FUNCTION_ID(201) + +/* + * SMCC does not define return codes for SiP functions. + * We use Architecture ones then. + */ + +#define SMC_SIP_CALL_SUCCESS SMC_ARCH_CALL_SUCCESS =20 #endif /* SBSA_QEMU_SMC_H_ */ diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h b/Sili= con/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h new file mode 100644 index 000000000000..9c7281f123d2 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h @@ -0,0 +1,45 @@ +/** @file +* +* Copyright (c) 2024, Linaro Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef HARDWARE_INFO_LIB +#define HARDWARE_INFO_LIB + +/** + Get CPU count from information passed by Qemu. + +**/ +UINT32 +GetCpuCount ( + VOID + ); + +/** + Get MPIDR for a given cpu from device tree passed by Qemu. + + @param [in] CpuId Index of cpu to retrieve MPIDR value for. + + @retval MPIDR value of CPU at index +**/ +UINT64 +GetMpidr ( + IN UINTN CpuId + ); + +/** + Get NUMA node id for a given cpu from device tree passed by Qemu. + + @param [in] CpuId Index of cpu to retrieve NUMA node id for. + + @retval NUMA node id for CPU at index +**/ +UINT64 +GetCpuNumaNode ( + IN UINTN CpuId + ); + +#endif /* HARDWARE_INFO_LIB */ diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemu= HardwareInfoLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/S= bsaQemuHardwareInfoLib.c new file mode 100644 index 000000000000..e96328978a55 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwar= eInfoLib.c @@ -0,0 +1,96 @@ +/** @file +* +* Copyright (c) 2021, NUVIA Inc. All rights reserved. +* Copyright (c) 2024, Linaro Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include +#include + +/** + Get CPU count from information passed by Qemu. + +**/ +UINT32 +GetCpuCount ( + VOID + ) +{ + UINTN Arg0; + UINTN SmcResult; + + SmcResult =3D ArmCallSmc0 (SIP_SVC_GET_CPU_COUNT, &Arg0, NULL, NULL); + if (SmcResult !=3D SMC_SIP_CALL_SUCCESS) { + DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_COUNT call failed. We have n= o cpu information.\n", __FUNCTION__)); + ResetShutdown (); + } + + DEBUG ((DEBUG_INFO, "%a: We have %d cpus.\n", __FUNCTION__, Arg0)); + + return Arg0; +} + +/** + Get MPIDR for a given cpu from device tree passed by Qemu. + + @param [in] CpuId Index of cpu to retrieve MPIDR value for. + + @retval MPIDR value of CPU at index +**/ +UINT64 +GetMpidr ( + IN UINTN CpuId + ) +{ + UINTN SmcResult; + UINTN Arg0; + UINTN Arg1; + + Arg0 =3D CpuId; + + SmcResult =3D ArmCallSmc0 (SIP_SVC_GET_CPU_NODE, &Arg0, &Arg1, NULL); + if (SmcResult !=3D SMC_SIP_CALL_SUCCESS) { + DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_NODE call failed. We have no= MPIDR for CPU%d.\n", __FUNCTION__, CpuId)); + ResetShutdown (); + } + + DEBUG ((DEBUG_INFO, "%a: MPIDR for CPU%d: =3D %d\n", __FUNCTION__, CpuId= , Arg1)); + + return Arg1; +} + +/** + Get NUMA node id for a given cpu from device tree passed by Qemu. + + @param [in] CpuId Index of cpu to retrieve NUMA node id for. + + @retval NUMA node id for CPU at index +**/ +UINT64 +GetCpuNumaNode ( + IN UINTN CpuId + ) +{ + UINTN SmcResult; + UINTN Arg0; + UINTN Arg1; + + Arg0 =3D CpuId; + + SmcResult =3D ArmCallSmc0 (SIP_SVC_GET_CPU_NODE, &Arg0, &Arg1, NULL); + if (SmcResult !=3D SMC_SIP_CALL_SUCCESS) { + DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_NODE call failed. Could not = find information for CPU%d.\n", __FUNCTION__, CpuId)); + return 0; + } + + DEBUG ((DEBUG_INFO, "%a: NUMA node for CPU%d: =3D %d\n", __FUNCTION__, C= puId, Arg0)); + + return Arg0; +} --=20 2.44.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#116936): https://edk2.groups.io/g/devel/message/116936 Mute This Topic: https://groups.io/mt/105044057/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-