From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id B49957803DE for ; Wed, 27 Mar 2024 14:03:25 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=oPNMudh/gRnIDmkHEYtWUsuoYiyZTb4q0nI8mab+v7w=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20240206; t=1711548204; v=1; b=mFqYVWzZ2JI4u0sMtGc4d58M9pswrJ/i3j92oN/zHSXNSnZFjhkSPBeZpRPkym50dQS6AdRK SVQVtvu/QQ4kFXi3lh/ezIPF1jxSUB/6VoO3YU4LT9HkHVAm5zEzsYw5rNIGtjUDzwQy5fSMc1g hLW0/G1TPlPdSYwdF/B5XBIGBIiwUfsFbmxy/AZSDwuGVNpSLIvfbkQqGuFRKzcxGwAorDPWi+X tfErXu16ZSYjPMy1jqCjVnnaGuwenBqlMdiui5HZkYVuh+knnRyHBT2GwqQ82YMcX4cNQAUXpA/ DPG0r9dybmdqHVGqiKJq8/r39T7ngz/LxeTLVpYb4s8EQ== X-Received: by 127.0.0.2 with SMTP id COFFYY7687511xOyP0NVwjjr; Wed, 27 Mar 2024 07:03:24 -0700 X-Received: from zg8tmtyylji0my4xnjqumte4.icoremail.net (zg8tmtyylji0my4xnjqumte4.icoremail.net [162.243.164.118]) by mx.groups.io with SMTP id smtpd.web10.38447.1711548203362726467 for ; Wed, 27 Mar 2024 07:03:23 -0700 X-Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-7 (Coremail) with SMTP id AQAAfwCniLQoJwRmuhoXEA--.27884S2; Wed, 27 Mar 2024 22:03:20 +0800 (CST) X-Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAfwCHGPgeJwRm8XcAAA--.515S4; Wed, 27 Mar 2024 22:03:15 +0800 (CST) From: "Xiong Yining" To: devel@edk2.groups.io Cc: quic_llindhol@quicinc.com, ardb+tianocore@kernel.org, graeme@xora.org.uk, marcin.juszkiewicz@linaro.org, chenbaozi@phytium.com.cn Subject: [edk2-devel] [PATCH v10 1/4] Platform/SbsaQemu: add SbsaQemuHardwareInfoLib Date: Wed, 27 Mar 2024 14:03:02 +0000 Message-Id: <20240327140305.3802896-2-xiongyining1480@phytium.com.cn> In-Reply-To: <20240327140305.3802896-1-xiongyining1480@phytium.com.cn> References: <20240327140305.3802896-1-xiongyining1480@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAfwCHGPgeJwRm8XcAAA--.515S4 X-CM-SenderInfo: x0lr0wp1lqx0bjrumio6sk53xlxphulrpou0/1tbiAQARBmYDI2QGVQACsl X-Coremail-Antispam: 1Uk129KBjvJXoW3Jw13CFW7uryfur47Jr45GFg_yoWfGFy5pF 4IyFWFgr4UJFyxKr4xGa4YvrnxCF1agFWUGrWqvr18Ar47JF1fXrW5XF1kJr1UJrsxu3yj gFW0qa4UuFnYkFJanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj DUYxn0WfASr-VFAU7a7-sFnT9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUU UUUUU Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Wed, 27 Mar 2024 07:03:23 -0700 Reply-To: devel@edk2.groups.io,xiongyining1480@phytium.com.cn List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: o3GrLZ1ka5iMmSnEFR0qOBfmx7686176AA= Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=mFqYVWzZ; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io From: Marcin Juszkiewicz This library provides functions to check for hardware information. For now it covers CPU ones: - amount of cpu cores - MPIDR value for cpu core - NUMA node id for cpu core Values are read from TF-A using platform specific SMC calls. Signed-off-by: Marcin Juszkiewicz --- Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 2 + Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 3 +- .../SbsaQemuHardwareInfoLib.inf | 29 ++++++ .../Include/IndustryStandard/SbsaQemuSmc.h | 17 +++- .../Include/Library/HardwareInfoLib.h | 45 +++++++++ .../SbsaQemuHardwareInfoLib.c | 96 +++++++++++++++++++ 6 files changed, 187 insertions(+), 5 deletions(-) create mode 100644 Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf create mode 100644 Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h create mode 100644 Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec index 913d1d75ef29..427ff8b31aac 100644 --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec @@ -12,6 +12,8 @@ PACKAGE_GUID = 8db32c5a-2821-43e2-b4ac-bc148e2b0b05 PACKAGE_VERSION = 0.1 +[LibraryClasses] +HardwareInfoLib|Include/Library/HardwareInfoLib.h ################################################################################ # # Include Section - list of Include Paths that are provided by this package. diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc index 378600050df9..3c3d2449bff4 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc @@ -1,6 +1,6 @@ # # Copyright (c) 2021, NUVIA Inc. All rights reserved. -# Copyright (c) 2019, Linaro Limited. All rights reserved. +# Copyright (c) 2019-2024, Linaro Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -128,6 +128,7 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE FdtHelperLib|Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf OemMiscLib|Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf + HardwareInfoLib|Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf # Debug Support PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf new file mode 100644 index 000000000000..2acb2a1e7c76 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf @@ -0,0 +1,29 @@ +#/* @file +# +# Copyright (c) 2024, Linaro Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#*/ + +[Defines] + INF_VERSION = 0x0001001c + BASE_NAME = SbsaQemuHardwareInfoLib + FILE_GUID = 6454006f-6502-46e2-9be4-4bba8d4b29fb + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = HardwareInfoLib + +[Sources] + SbsaQemuHardwareInfoLib.c + +[Packages] + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Qemu/SbsaQemu/SbsaQemu.dec + +[LibraryClasses] + ArmSmcLib + ResetSystemLib diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h index 7934875e4aba..2317c1f0ae69 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2023, Linaro Ltd. All rights reserved.
+* Copyright (c) 2023-2024, Linaro Ltd. All rights reserved.
* * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -11,8 +11,17 @@ #include -#define SIP_SVC_VERSION SMC_SIP_FUNCTION_ID(1) -#define SIP_SVC_GET_GIC SMC_SIP_FUNCTION_ID(100) -#define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101) +#define SIP_SVC_VERSION SMC_SIP_FUNCTION_ID(1) +#define SIP_SVC_GET_GIC SMC_SIP_FUNCTION_ID(100) +#define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101) +#define SIP_SVC_GET_CPU_COUNT SMC_SIP_FUNCTION_ID(200) +#define SIP_SVC_GET_CPU_NODE SMC_SIP_FUNCTION_ID(201) + +/* + * SMCC does not define return codes for SiP functions. + * We use Architecture ones then. + */ + +#define SMC_SIP_CALL_SUCCESS SMC_ARCH_CALL_SUCCESS #endif /* SBSA_QEMU_SMC_H_ */ diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h new file mode 100644 index 000000000000..8b1b5e5e1b93 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h @@ -0,0 +1,45 @@ +/** @file +* +* Copyright (c) 2024, Linaro Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef HARDWARE_INFO_LIB +#define HARDWARE_INFO_LIB + +/** + Get CPU count from information passed by Qemu. + +**/ +UINT32 +GetCpuCount ( + VOID + ); + +/** + Get MPIDR for a given cpu from device tree passed by Qemu. + + @param [in] CpuId Index of cpu to retrieve MPIDR value for. + + @retval MPIDR value of CPU at index +**/ +UINT64 +GetMpidr ( + IN UINTN CpuId + ); + +/** + Get NUMA node id for a given cpu from device tree passed by Qemu. + + @param [in] CpuId Index of cpu to retrieve NUMA node id for. + + @retval NUMA node id for CPU at index +**/ +UINT64 +GetCpuNumaNode ( + IN UINTN CpuId + ); + +#endif /* HARDWARE_INFO_LIB */ diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c new file mode 100644 index 000000000000..e96328978a55 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c @@ -0,0 +1,96 @@ +/** @file +* +* Copyright (c) 2021, NUVIA Inc. All rights reserved. +* Copyright (c) 2024, Linaro Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include +#include + +/** + Get CPU count from information passed by Qemu. + +**/ +UINT32 +GetCpuCount ( + VOID + ) +{ + UINTN Arg0; + UINTN SmcResult; + + SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_COUNT, &Arg0, NULL, NULL); + if (SmcResult != SMC_SIP_CALL_SUCCESS) { + DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_COUNT call failed. We have no cpu information.\n", __FUNCTION__)); + ResetShutdown (); + } + + DEBUG ((DEBUG_INFO, "%a: We have %d cpus.\n", __FUNCTION__, Arg0)); + + return Arg0; +} + +/** + Get MPIDR for a given cpu from device tree passed by Qemu. + + @param [in] CpuId Index of cpu to retrieve MPIDR value for. + + @retval MPIDR value of CPU at index +**/ +UINT64 +GetMpidr ( + IN UINTN CpuId + ) +{ + UINTN SmcResult; + UINTN Arg0; + UINTN Arg1; + + Arg0 = CpuId; + + SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_NODE, &Arg0, &Arg1, NULL); + if (SmcResult != SMC_SIP_CALL_SUCCESS) { + DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_NODE call failed. We have no MPIDR for CPU%d.\n", __FUNCTION__, CpuId)); + ResetShutdown (); + } + + DEBUG ((DEBUG_INFO, "%a: MPIDR for CPU%d: = %d\n", __FUNCTION__, CpuId, Arg1)); + + return Arg1; +} + +/** + Get NUMA node id for a given cpu from device tree passed by Qemu. + + @param [in] CpuId Index of cpu to retrieve NUMA node id for. + + @retval NUMA node id for CPU at index +**/ +UINT64 +GetCpuNumaNode ( + IN UINTN CpuId + ) +{ + UINTN SmcResult; + UINTN Arg0; + UINTN Arg1; + + Arg0 = CpuId; + + SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_NODE, &Arg0, &Arg1, NULL); + if (SmcResult != SMC_SIP_CALL_SUCCESS) { + DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_NODE call failed. Could not find information for CPU%d.\n", __FUNCTION__, CpuId)); + return 0; + } + + DEBUG ((DEBUG_INFO, "%a: NUMA node for CPU%d: = %d\n", __FUNCTION__, CpuId, Arg0)); + + return Arg0; +} -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117170): https://edk2.groups.io/g/devel/message/117170 Mute This Topic: https://groups.io/mt/105177611/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-