From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id A6BB2AC1724 for ; Wed, 27 Mar 2024 14:03:29 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=wb83JVAnKlmQTedM3TUsgdKPYGX1SR2XzbMSXn+U03k=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20240206; t=1711548208; v=1; b=e8OT2eyN/mEkxT5ZUMR4PEqlyTNx5c7gkbv/dwW1Pbdr9Ek5lL8sg3Dj2ZqxICMbV9x9HA/U KUsCJLV4H5Cp4eYuC/0q+Cfwr5OTqKjL3eUQJARLtl47I8sZ6KWfDC4pC+F/DJyy4BMlEDrCWKM VUsktjSBJxHb9CWyo9IvZbPl4vxJXYve38cAM6rW1JA1QDka5mf8OC5oCSDmK8KP1dHSgvo393Q Vf/HNeYMtn5dXaN870B1kAhtuNp0xF+9/vYB6kVHyBrcSGAqs+A1qnIS+z2ssiDFKbYBdZH3/4v 23N3pUjLXyYpbcVMLG9cL7Dj/SQs06H2oEIs4BvesLzug== X-Received: by 127.0.0.2 with SMTP id WJfvYY7687511x5fo23YmS5Y; Wed, 27 Mar 2024 07:03:28 -0700 X-Received: from zg8tmja5ljk3lje4ms43mwaa.icoremail.net (zg8tmja5ljk3lje4ms43mwaa.icoremail.net [209.97.181.73]) by mx.groups.io with SMTP id smtpd.web10.38450.1711548205414852969 for ; Wed, 27 Mar 2024 07:03:25 -0700 X-Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-7 (Coremail) with SMTP id AQAAfwDHzrYqJwRm5RoXEA--.12913S2; Wed, 27 Mar 2024 22:03:22 +0800 (CST) X-Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAfwCHGPgeJwRm8XcAAA--.515S7; Wed, 27 Mar 2024 22:03:19 +0800 (CST) From: "Xiong Yining" To: devel@edk2.groups.io Cc: quic_llindhol@quicinc.com, ardb+tianocore@kernel.org, graeme@xora.org.uk, marcin.juszkiewicz@linaro.org, chenbaozi@phytium.com.cn, Xiong Yining , Ard Biesheuvel Subject: [edk2-devel] [PATCH v10 4/4] Platform/SbsaQemu: get the information of memory via SMC calls Date: Wed, 27 Mar 2024 14:03:05 +0000 Message-Id: <20240327140305.3802896-5-xiongyining1480@phytium.com.cn> In-Reply-To: <20240327140305.3802896-1-xiongyining1480@phytium.com.cn> References: <20240327140305.3802896-1-xiongyining1480@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAfwCHGPgeJwRm8XcAAA--.515S7 X-CM-SenderInfo: x0lr0wp1lqx0bjrumio6sk53xlxphulrpou0/1tbiAQARBmYDI2QGWgAAso X-Coremail-Antispam: 1Uk129KBjvJXoW3Xw4fur18WF1kGryrXrWDArb_yoW3XFyDpF n7AFZ5ur4UJrySyr4xJayrtry5Ga43Gws8GrZFvr1Ykr47G3WrZrWUtrykJw4UXF98u3yq gFW8Xa4Uu3Z8GaDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj DUYxn0WfASr-VFAU7a7-sFnT9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUU UUUUU Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Wed, 27 Mar 2024 07:03:25 -0700 Reply-To: devel@edk2.groups.io,xiongyining1480@phytium.com.cn List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: zVlQCooRDja90zyGA0Ub5mtPx7686176AA= Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=e8OT2eyN; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Provide functions to check for memory information: - amount of memory nodes - memory address - NUMA node id for memory Values are read from TF-A using platform specific SMC calls. Signed-off-by: Xiong Yining Signed-off-by: Chen Baozi Signed-off-by: Marcin Juszkiewicz Reviewed-by: Ard Biesheuvel --- .../Library/SbsaQemuLib/SbsaQemuLib.inf | 3 +- .../Include/IndustryStandard/SbsaQemuSmc.h | 2 + .../Include/Library/HardwareInfoLib.h | 31 +++++++++++ .../SbsaQemuHardwareInfoLib.c | 49 +++++++++++++++++ .../Library/SbsaQemuLib/SbsaQemuMem.c | 54 +++++-------------- 5 files changed, 96 insertions(+), 43 deletions(-) diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf index 07e6bc4e9b11..384cbb349200 100644 --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf @@ -32,14 +32,13 @@ ArmLib BaseMemoryLib DebugLib + HardwareInfoLib MemoryAllocationLib PcdLib - SbsaQemuHardwareInfoLib [Pcd] gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress [FixedPcd] gArmTokenSpaceGuid.PcdFdBaseAddress diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h index 2317c1f0ae69..e3092007d27d 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h @@ -16,6 +16,8 @@ #define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101) #define SIP_SVC_GET_CPU_COUNT SMC_SIP_FUNCTION_ID(200) #define SIP_SVC_GET_CPU_NODE SMC_SIP_FUNCTION_ID(201) +#define SIP_SVC_GET_MEMORY_NODE_COUNT SMC_SIP_FUNCTION_ID(300) +#define SIP_SVC_GET_MEMORY_NODE SMC_SIP_FUNCTION_ID(301) /* * SMCC does not define return codes for SiP functions. diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h index 8b1b5e5e1b93..5db0eacc9d2d 100644 --- a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h +++ b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h @@ -9,6 +9,12 @@ #ifndef HARDWARE_INFO_LIB #define HARDWARE_INFO_LIB +typedef struct{ + UINT32 NodeId; + UINT64 AddressBase; + UINT64 AddressSize; +} MemoryInfo; + /** Get CPU count from information passed by Qemu. @@ -42,4 +48,29 @@ GetCpuNumaNode ( IN UINTN CpuId ); +/** + Get the number of memory node from device tree passed by Qemu. + + @retval the number of memory nodes. +**/ +UINT32 +GetMemNodeCount ( + VOID + ); + +/** + Get memory information(node-id, addressbase, addresssize) for a given memory node from device tree passed by Qemu. + + @param [in] MemoryId Index of memory to retrieve memory information. + @param [out] MemInfo A pointer to the memory information of given memory-id. + + + @retval memory infomation for given memory node. +**/ +VOID +GetMemInfo ( + IN UINTN MemoryId, + OUT MemoryInfo *MemInfo + ); + #endif /* HARDWARE_INFO_LIB */ diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c index e96328978a55..b178cf6c6c43 100644 --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c @@ -94,3 +94,52 @@ GetCpuNumaNode ( return Arg0; } + +UINT32 +GetMemNodeCount ( + VOID + ) +{ + UINTN SmcResult; + UINTN Arg0; + + SmcResult = ArmCallSmc0 (SIP_SVC_GET_MEMORY_NODE_COUNT, &Arg0, NULL, NULL); + if (SmcResult != SMC_SIP_CALL_SUCCESS) { + DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_MEMORY_NODE_COUNT call failed. We have no memory information.\n", __FUNCTION__)); + ResetShutdown (); + } + + DEBUG (( DEBUG_INFO, "%a: The number of the memory nodes is %ld\n", __FUNCTION__, Arg0)); + return (UINT32)Arg0; +} + +VOID +GetMemInfo ( + IN UINTN MemoryId, + OUT MemoryInfo *MemInfo + ) +{ + UINTN SmcResult; + UINTN Arg0; + UINTN Arg1; + UINTN Arg2; + + Arg0 = MemoryId; + + SmcResult = ArmCallSmc1 (SIP_SVC_GET_MEMORY_NODE, &Arg0, &Arg1, &Arg2); + if (SmcResult != SMC_SIP_CALL_SUCCESS) { + DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_MEMORY_NODE call failed. We have no memory information.\n", __FUNCTION__)); + ResetShutdown (); + } else { + MemInfo->NodeId = Arg0; + MemInfo->AddressBase = Arg1; + MemInfo->AddressSize = Arg2; + } + + DEBUG(( DEBUG_INFO, "%a: NUMA node for System RAM:%d = 0x%lx - 0x%lx\n", + __FUNCTION__, + MemInfo->NodeId, + MemInfo->AddressBase, + MemInfo->AddressBase + MemInfo->AddressSize -1 )); + +} diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c index 8c2eb0b6a028..f838fdcf274d 100644 --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include // Number of Virtual Memory Map Descriptors #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 4 @@ -23,53 +23,25 @@ SbsaQemuLibConstructor ( VOID ) { - VOID *DeviceTreeBase; - INT32 Node, Prev; UINT64 NewBase, CurBase; UINT64 NewSize, CurSize; - CONST CHAR8 *Type; - INT32 Len; - CONST UINT64 *RegProp; + UINT32 NumMemNodes; + UINT32 Index; + MemoryInfo MemInfo; RETURN_STATUS PcdStatus; NewBase = 0; NewSize = 0; - DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress); - ASSERT (DeviceTreeBase != NULL); - - // Make sure we have a valid device tree blob - ASSERT (fdt_check_header (DeviceTreeBase) == 0); - - // Look for the lowest memory node - for (Prev = 0;; Prev = Node) { - Node = fdt_next_node (DeviceTreeBase, Prev, NULL); - if (Node < 0) { - break; - } - - // Check for memory node - Type = fdt_getprop (DeviceTreeBase, Node, "device_type", &Len); - if (Type && AsciiStrnCmp (Type, "memory", Len) == 0) { - // Get the 'reg' property of this node. For now, we will assume - // two 8 byte quantities for base and size, respectively. - RegProp = fdt_getprop (DeviceTreeBase, Node, "reg", &Len); - if (RegProp != 0 && Len == (2 * sizeof (UINT64))) { - - CurBase = fdt64_to_cpu (ReadUnaligned64 (RegProp)); - CurSize = fdt64_to_cpu (ReadUnaligned64 (RegProp + 1)); - - DEBUG ((DEBUG_INFO, "%a: System RAM @ 0x%lx - 0x%lx\n", - __FUNCTION__, CurBase, CurBase + CurSize - 1)); - - if (NewBase > CurBase || NewBase == 0) { - NewBase = CurBase; - NewSize = CurSize; - } - } else { - DEBUG ((DEBUG_ERROR, "%a: Failed to parse FDT memory node\n", - __FUNCTION__)); - } + NumMemNodes = GetMemNodeCount(); + for(Index = 0; Index < NumMemNodes; Index++){ + GetMemInfo(Index, &MemInfo); + CurBase = MemInfo.AddressBase; + CurSize = MemInfo.AddressSize; + + if (NewBase > CurBase || NewBase == 0) { + NewBase = CurBase; + NewSize = CurSize; } } -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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