From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id D4F26740041 for ; Wed, 10 Apr 2024 13:57:37 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=feBBx35Bmoggyt8pa7pgal+qQm6y9HwGXGBbzRu0yvc=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20240206; t=1712757456; v=1; b=vdU+w9mzhdJ/vzeRbdMZQa03SJ0BbbvmbRkLh5LJmHjnQkN75mWocf4X9V8dcFx0RD4mkZvw 3DBuX16FZj8WEod1IW5i8KsrwqFACQaS2MDUxOwOS6AO1gVJbICgXp0QdzoJD/gHGYdyjVjutjn G3bBAFkHiouzlHXZF6Ab5DQkGaBvW/UhnGSDkkrBwbb7bfJDlKaG+aBu98MQr/L25IPWFk6I1bw nSvLAolG2nxTUkI/+j3g6wR+MDtn6g/cjZMvD6Yfy8OVJECAipFjCQOjG+66jkGV9104e0jZ+2e r1CkydpIm0hNq/zhOFljBHOF4Pcz3kAWnoXu00bbUufvw== X-Received: by 127.0.0.2 with SMTP id iCZhYY7687511xLXp8t0ApBI; Wed, 10 Apr 2024 06:57:36 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by mx.groups.io with SMTP id smtpd.web10.306.1712757450770649687 for ; Wed, 10 Apr 2024 06:57:36 -0700 X-CSE-ConnectionGUID: +qxUL5YlRcCiNRVlpCGEeg== X-CSE-MsgGUID: ulgP6yShQSaxzdVRTbCbWA== X-IronPort-AV: E=McAfee;i="6600,9927,11039"; a="30602136" X-IronPort-AV: E=Sophos;i="6.07,190,1708416000"; d="scan'208";a="30602136" X-Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Apr 2024 06:57:36 -0700 X-CSE-ConnectionGUID: gMQAeJVMTFm5P7RiVR5NlQ== X-CSE-MsgGUID: ZqO9+xqpRbeiQoqwWKxARg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,190,1708416000"; d="scan'208";a="51778161" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by fmviesa001.fm.intel.com with ESMTP; 10 Apr 2024 06:57:33 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Ray Ni , Zeng Star , Ard Biesheuvel , Jiewen Yao , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v1 03/13] UefiCpuPkg/SmmRelocationLib: Add library instance for OVMF Date: Wed, 10 Apr 2024 21:57:14 +0800 Message-Id: <20240410135724.15344-4-jiaxin.wu@intel.com> In-Reply-To: <20240410135724.15344-1-jiaxin.wu@intel.com> References: <20240410135724.15344-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Wed, 10 Apr 2024 06:57:36 -0700 Resent-From: jiaxin.wu@intel.com Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: ZI0zFFgg5lOAi1FiWPtbNOnMx7686176AA= X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=vdU+w9mz; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Due to the definition difference of SMRAM Save State, SmmBase config in SMRAM Save State for OVMF is also different. This patch provides the OvmfSmmRelocationLib library instance to handle the SMRAM Save State difference. Cc: Ray Ni Cc: Zeng Star Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- .../SmmRelocationLib/OvmfSmmRelocationLib.inf | 61 ++++++++++++ .../SmmRelocationLib/OvmfSmramSaveStateConfig.c | 107 +++++++++++++++++++++ 2 files changed, 168 insertions(+) create mode 100644 UefiCpuPkg/Library/SmmRelocationLib/OvmfSmmRelocationLib.inf create mode 100644 UefiCpuPkg/Library/SmmRelocationLib/OvmfSmramSaveStateConfig.c diff --git a/UefiCpuPkg/Library/SmmRelocationLib/OvmfSmmRelocationLib.inf b/UefiCpuPkg/Library/SmmRelocationLib/OvmfSmmRelocationLib.inf new file mode 100644 index 0000000000..eba1129ac2 --- /dev/null +++ b/UefiCpuPkg/Library/SmmRelocationLib/OvmfSmmRelocationLib.inf @@ -0,0 +1,61 @@ +## @file +# SMM Relocation Lib for each processor. +# +# This Lib produces the SMM_BASE_HOB in HOB database which tells +# the PiSmmCpuDxeSmm driver (runs at a later phase) about the new +# SMBASE for each processor. PiSmmCpuDxeSmm driver installs the +# SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 for processor +# Index. +# +# Copyright (c) 2024, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SmmRelocationLib + FILE_GUID = 51834F51-CCE0-4743-B553-935D0C8A53FF + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = SmmRelocationLib + +[Sources] + InternalSmmRelocationLib.h + OvmfSmramSaveStateConfig.c + SmmRelocationLib.c + +[Sources.Ia32] + Ia32/Semaphore.c + Ia32/SmmInit.nasm + +[Sources.X64] + X64/Semaphore.c + X64/SmmInit.nasm + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + CpuExceptionHandlerLib + DebugLib + HobLib + LocalApicLib + MemoryAllocationLib + PcdLib + PeiServicesLib + +[Guids] + gSmmBaseHobGuid ## HOB ALWAYS_PRODUCED + gEfiSmmSmramMemoryGuid ## CONSUMES + +[Pcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize ## CONSUMES + +[FeaturePcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport ## CONSUMES diff --git a/UefiCpuPkg/Library/SmmRelocationLib/OvmfSmramSaveStateConfig.c b/UefiCpuPkg/Library/SmmRelocationLib/OvmfSmramSaveStateConfig.c new file mode 100644 index 0000000000..505b1d694a --- /dev/null +++ b/UefiCpuPkg/Library/SmmRelocationLib/OvmfSmramSaveStateConfig.c @@ -0,0 +1,107 @@ +/** @file + Config SMRAM Save State for SmmBases Relocation. + + Copyright (c) 2024, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include "InternalSmmRelocationLib.h" +#include + +/** + This function configures the SmBase on the currently executing CPU. + + @param[in] CpuIndex The index of the CPU. + @param[in,out] CpuState Pointer to SMRAM Save State Map for the + currently executing CPU. On out, SmBase is + updated to the new value. + +**/ +VOID +EFIAPI +ConfigureSmBase ( + IN UINTN CpuIndex, + IN OUT SMRAM_SAVE_STATE_MAP *CpuState + ) +{ + AMD_SMRAM_SAVE_STATE_MAP *CpuSaveState; + + CpuSaveState = (AMD_SMRAM_SAVE_STATE_MAP *)CpuState; + + if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) { + CpuSaveState->x86.SMBASE = (UINT32)mSmBaseForAllCpus[CpuIndex]; + } else { + CpuSaveState->x64.SMBASE = (UINT32)mSmBaseForAllCpus[CpuIndex]; + } +} + +/** + This function updates the SMRAM save state on the currently executing CPU + to resume execution at a specific address after an RSM instruction. This + function must evaluate the SMRAM save state to determine the execution mode + the RSM instruction resumes and update the resume execution address with + either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart + flag in the SMRAM save state must always be cleared. This function returns + the value of the instruction pointer from the SMRAM save state that was + replaced. If this function returns 0, then the SMRAM save state was not + modified. + + This function is called during the very first SMI on each CPU after + SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode + to signal that the SMBASE of each CPU has been updated before the default + SMBASE address is used for the first SMI to the next CPU. + + @param[in] CpuIndex The processor index for the currently + executing CPU. + @param[in,out] CpuState Pointer to SMRAM Save State Map for the + currently executing CPU. + @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to + 32-bit mode from 64-bit SMM. + @param[in] NewInstructionPointer Instruction pointer to use if resuming to + same mode as SMM. + + @retval The value of the original instruction pointer before it was hooked. + +**/ +UINT64 +EFIAPI +HookReturnFromSmm ( + IN UINTN CpuIndex, + IN OUT SMRAM_SAVE_STATE_MAP *CpuState, + IN UINT64 NewInstructionPointer32, + IN UINT64 NewInstructionPointer + ) +{ + UINT64 OriginalInstructionPointer; + AMD_SMRAM_SAVE_STATE_MAP *CpuSaveState; + + CpuSaveState = (AMD_SMRAM_SAVE_STATE_MAP *)CpuState; + if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) { + OriginalInstructionPointer = (UINT64)CpuSaveState->x86._EIP; + CpuSaveState->x86._EIP = (UINT32)NewInstructionPointer; + // + // Clear the auto HALT restart flag so the RSM instruction returns + // program control to the instruction following the HLT instruction. + // + if ((CpuSaveState->x86.AutoHALTRestart & BIT0) != 0) { + CpuSaveState->x86.AutoHALTRestart &= ~BIT0; + } + } else { + OriginalInstructionPointer = CpuSaveState->x64._RIP; + if ((CpuSaveState->x64.EFER & LMA) == 0) { + CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer32; + } else { + CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer; + } + + // + // Clear the auto HALT restart flag so the RSM instruction returns + // program control to the instruction following the HLT instruction. + // + if ((CpuSaveState->x64.AutoHALTRestart & BIT0) != 0) { + CpuSaveState->x64.AutoHALTRestart &= ~BIT0; + } + } + + return OriginalInstructionPointer; +} -- 2.16.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117591): https://edk2.groups.io/g/devel/message/117591 Mute This Topic: https://groups.io/mt/105441992/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-