From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id 8F2C9740034 for ; Sat, 20 Apr 2024 02:31:45 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=Fb3vKP5vbD2P52HvxgD3QhW5JSWB9LDmmS/hs+w/VKA=; c=relaxed/simple; d=groups.io; h=Date:Mime-Version:Message-ID:Subject:From:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20240206; t=1713580304; v=1; b=AyaJsdON1gluf5DszP0YuA/xATqRnGbRhvCFBUxRX6DpcyX76PxuWkFOrPegfk0KfYvXq8hn E6FL8exq6bLgrdQVi05QB1Zfffk3GloPVlBX/ODa6Lhhz3nDMrpmSeusAK0sn9DedcOoR3excKZ aGdfKNvgvWNd9/ZXACE4/F3bZ4ebwUycOUxpEPUP8kYBFDBCQFFNEvH1wrHFnBy3avJ3EfEswkr W85FHD8xyP8p/joUIjEY/wG/RTOmSlny0lOCp6BFD70OeaLXoO3xmXnaGz1iKTHmM5wMWiUT94R LxPxYSbhpEnYlDgHNLNYPdr7iCn95OTmgWtMyLaqmh5gg== X-Received: by 127.0.0.2 with SMTP id LK6OYY7687511xr6oXihIojG; Fri, 19 Apr 2024 19:31:44 -0700 X-Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) by mx.groups.io with SMTP id smtpd.web10.374.1713549017095764450 for ; Fri, 19 Apr 2024 10:50:17 -0700 X-Received: by mail-yw1-f201.google.com with SMTP id 00721157ae682-617bd0cf61fso47284207b3.3 for ; Fri, 19 Apr 2024 10:50:16 -0700 (PDT) X-Gm-Message-State: qltWkgMzxt9swrou3uEFzZxEx7686176AA= X-Google-Smtp-Source: AGHT+IEIQB3Q+GPSHdCHFJfQZ7U1B+ZKjlyqgw2PqJY9NKx2yCAJCzwwcJKCAzhUW8buJuMrSx9KDA7c X-Received: from palermo.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:118a]) (user=ardb job=sendgmr) by 2002:a05:690c:610e:b0:618:9588:e9db with SMTP id hi14-20020a05690c610e00b006189588e9dbmr722562ywb.2.1713549016211; Fri, 19 Apr 2024 10:50:16 -0700 (PDT) Date: Fri, 19 Apr 2024 19:50:13 +0200 Mime-Version: 1.0 Message-ID: <20240419175013.3983824-1-ardb+git@google.com> Subject: [edk2-devel] [PATCH] ArmVirtPkg/ArmVirtQemu: always build XIP code with strict alignment From: "Ard Biesheuvel via groups.io" To: devel@edk2.groups.io Cc: quic_llindhol@quicinc.com, Ard Biesheuvel , Jonathan Cameron , Richard Henderson , "=?UTF-8?q?Philippe=20Mathieu-Daud=E9?=" , Idan Horowitz , qemu-arm@nongnu.org Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Fri, 19 Apr 2024 19:31:43 -0700 Resent-From: ardb+git@google.com Reply-To: devel@edk2.groups.io,ardb+git@google.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=AyaJsdON; dmarc=pass (policy=none) header.from=groups.io; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io From: Ard Biesheuvel The optimization that enabled entry with MMU and caches enabled at EL1 removed the strict alignment requirement for XIP code (roughly, any code that might execute with the MMU and caches off, which means SEC and PEI phase modules but also *all* BASE libraries), on the basis that QEMU can only run guest payloads at EL2 in TCG emulation, which used to ignore alignment violations, and execution at EL1 would always occur with the MMU enabled. This assumption no longer holds: not only does QEMU now enforce strict alignment for memory accesses with device semantics, there are also cases where this code might execute at EL2 under virtualization (i.e., under NV2 nested virtualization) where the strict alignment is required too. The latter case could be optimized too, by enabling VHE and pretending execution is occurring at EL1, which would allow the existing logic for entry with the MMU enabled to be reused. However, this would leave non-VHE CPUs behind. So in summary, strict alignment needs to be enforced for any code that may execute with the MMU off, so drop the override that sets the XIP flags to the empty string. Cc: Jonathan Cameron Cc: Richard Henderson Cc: Philippe Mathieu-Daud=EF=BF=BD Cc: Idan Horowitz Cc: qemu-arm@nongnu.org Signed-off-by: Ard Biesheuvel --- ArmVirtPkg/ArmVirtQemu.dsc | 2 -- 1 file changed, 2 deletions(-) diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc index e48c75b5e99f..f6f78359552d 100644 --- a/ArmVirtPkg/ArmVirtQemu.dsc +++ b/ArmVirtPkg/ArmVirtQemu.dsc @@ -124,8 +124,6 @@ [LibraryClasses.common.UEFI_DRIVER] [BuildOptions] !if $(CAVIUM_ERRATUM_27456) =3D=3D TRUE GCC:*_*_AARCH64_PP_FLAGS =3D -DCAVIUM_ERRATUM_27456 -!else - GCC:*_*_AARCH64_CC_XIPFLAGS =3D=3D !endif =20 !include NetworkPkg/NetworkBuildOptions.dsc.inc -- 2.44.0.769.g3c40516874-goog -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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