From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id 1FBC99419EB for ; Tue, 23 Apr 2024 14:56:02 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=WiBCe4krOoXuHmRaZhetZDHcAhN0bOMAqhMQ3+FSLEA=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20240206; t=1713884161; v=1; b=EwEmrHLhSpJ7Of59zF6UsRIUMGH+NhX/KXE7ruQlKYU2JnIwwK9LpIn3RK2d3wziiYV9hGnE GiBgY4RSPO1+R3SLxXLsqvfuj3mmOk+89+p7pw53lX0OBCcmrGHggyEA8tkN/XlWxs93moHKCSS NFVU2Atr6RTvrADyorTwhcQdAai9CevIEaz5W0ecA6E+O3eKBTQWH7NJDSebwfaAAF4At5M3E2J HQvBJJ2cqLv/d7jCOHwC0RfTnVOd5LX2Zg0vRwLMWzNe5MJBVtM3wfZf+k+2a6DfZH+6c5edlYB IVEZMgbwhlU9P26RmSCgsaNoKera0nRwPWBThU6rxzNUA== X-Received: by 127.0.0.2 with SMTP id cAf4YY7687511xsgGyAbfwtL; Tue, 23 Apr 2024 07:56:01 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.11906.1713851832510418591 for ; Mon, 22 Apr 2024 22:57:12 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4B36D339; Mon, 22 Apr 2024 22:57:40 -0700 (PDT) X-Received: from usa.arm.com (a077434.arm.com [10.162.46.143]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 91FC93F7BD; Mon, 22 Apr 2024 22:57:10 -0700 (PDT) From: "Sahil Kaushal" To: devel@edk2.groups.io Cc: Ard Biesheuvel , =?UTF-8?q?Leif=20Lindholm=20=C2=A0?= , Sami Mujawar , =?UTF-8?q?sahil=20=C2=A0?= Subject: [edk2-devel] [PATCH RESEND edk2-platforms][PATCH V2 10/14] Silicon/ARM/NeoverseN1Soc: Enable SCP QSPI flash region Date: Tue, 23 Apr 2024 11:26:34 +0530 Message-Id: <20240423055638.1271531-11-Sahil.Kaushal@arm.com> In-Reply-To: <20240423055638.1271531-1-Sahil.Kaushal@arm.com> References: <20240423055638.1271531-1-Sahil.Kaushal@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Tue, 23 Apr 2024 07:55:51 -0700 Resent-From: sahil.kaushal@arm.com Reply-To: devel@edk2.groups.io,sahil.kaushal@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 645tSXXhK32cljyMPtlINA4px7686176AA= Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=EwEmrHLh; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=arm.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io From: sahil Enable SCP QSPI flash region access by adding it in the PlatformLibMem. This flash is shared between AP core and System Control Processor. The lower addresses are used to store SCP and AP boot images and higher addresses will be used for variable storage. Signed-off-by: sahil --- Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 7 +++++++ Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 8 +++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/AR= M/NeoverseN1Soc/Include/NeoverseN1Soc.h index 5483e7bc5f68..2dae57a0f01a 100644 --- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h +++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h @@ -4,6 +4,9 @@ *=0D * SPDX-License-Identifier: BSD-2-Clause-Patent=0D *=0D +* Arm Neoverse N1 System Development Platform Technical Reference Manual=0D +* https://developer.arm.com/documentation/101489/0000/?lang=3Den=0D +*=0D **/=0D =0D #ifndef NEOVERSEN1SOC_PLATFORM_H_=0D @@ -41,6 +44,10 @@ #define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000=0D #define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000=0D =0D +// SCP QSPI flash device=0D +#define NEOVERSEN1SOC_SCP_QSPI_AHB_BASE 0x18000000=0D +#define NEOVERSEN1SOC_SCP_QSPI_AHB_SZ 0x2000000=0D +=0D /*=0D * Platform information structure stored in Non-secure SRAM. Platform=0D * information are passed from the trusted firmware with the below structu= re=0D diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c= b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c index 80daedb33416..282bfbc81736 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c @@ -14,7 +14,7 @@ #include =0D =0D // The total number of descriptors, including the final "end-of-table" des= criptor.=0D -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19=0D +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 20=0D =0D /**=0D Returns the Virtual Memory Map of the platform.=0D @@ -203,6 +203,12 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length =3D NEOVERSEN1SOC_EXP_PERIPH_B= ASE0_SZ;=0D VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE;=0D =0D + // SCP QSPI flash device=0D + VirtualMemoryTable[++Index].PhysicalBase =3D NEOVERSEN1SOC_SCP_QSPI_AHB= _BASE;=0D + VirtualMemoryTable[Index].VirtualBase =3D NEOVERSEN1SOC_SCP_QSPI_AHB= _BASE;=0D + VirtualMemoryTable[Index].Length =3D NEOVERSEN1SOC_SCP_QSPI_AHB= _SZ;=0D + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE;=0D +=0D if (PlatInfo->MultichipMode =3D=3D 1) {=0D //Remote DDR (2GB)=0D VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdExtMemorySp= ace) +=0D --=20 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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