[edk2-devel] [PATCH WIP edk2-platforms 0/3] SbsaQemu: add support for multiple PCI Express buses

["Marcin Juszkiewicz" <marcin.juszkiewicz@linaro.org>]

QEMU allows to have NUMA setup where each node has own cpus, memory and
i/o. We already handle cpus and memory. This patchset adds support for
having multiple PCI Express buses.

SbsaQemu assumed that there is only bus 0. First patch does PCIe bus
scan to find all host bridges (bus 0 one and additional 'pxb-pcie'
ones).

Second patch moves description of PCIe from DSDT to SSDT (one per each
PCIe bus). So Operating System will know about all of them.

Third patch moves generation of MCFG table to C. It is preparation to
move PCIe Pcds from being fixed to dynamic ones.

There are some booting issues with assigning resources for cards:

pci 0000:00:03.0: BAR 15: no space for [mem size 0x00200000 64bit pref]
pci 0000:00:03.0: BAR 15: failed to assign [mem size 0x00200000 64bit pref]
pci 0000:00:01.0: BAR 6: no space for [mem size 0x00040000 pref]
pci 0000:00:01.0: BAR 6: failed to assign [mem size 0x00040000 pref]
pci 0000:00:03.0: BAR 13: no space for [io  size 0x1000]
pci 0000:00:03.0: BAR 13: failed to assign [io  size 0x1000]

Boot log (Linux + lspci + ACPI tables dump):
https://people.linaro.org/~marcin.juszkiewicz/sbsa-ref/boot-linux-with-numa-multiple-pcie-buses.txt

I am wondering where I made mistakes in handling PCIe buses.

Thanks go to Leif for pointing me to use of Aml to generate SSDT tables.

Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Graeme Gregory <graeme@xora.org.uk>
Cc: Ray Ni <ray.ni@intel.com>
To: devel@edk2.groups.io

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
Marcin Juszkiewicz (3):
      SbsaQemu: scan for PCIe buses
      SbsaQemu: describe PCIe buses in SSDT tables
      SbsaQemu: generate MCFG table

 Platform/Qemu/SbsaQemu/SbsaQemu.dsc                 |   2 +
 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf     |   1 -
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf     |  37 +-
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiPcie.h      |  23 +
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c       | 170 +++++-
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiPcie.c      | 576 ++++++++++++++++++++
 .../SbsaQemuPciHostBridgeLib.c                      | 185 ++++---
 Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl           | 302 ----------
 Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc          |  43 --
 .../Drivers/SbsaQemuAcpiDxe/SsdtTemplate.asl        |  82 +++
 10 files changed, 982 insertions(+), 439 deletions(-)
---
base-commit: 73cfdc4afff3e641be217b31b985761ef8338412
change-id: 20240425-review-multiple-pcie-0425-54ce3817fd3f

Best regards,
-- 
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#118288): https://edk2.groups.io/g/devel/message/118288
Mute This Topic: https://groups.io/mt/105728624/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-