From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id 72D76AC11F9 for ; Thu, 25 Apr 2024 12:03:02 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=jeJJ4lbDiOq/MBDUarFtd1LK4ZaNJuT8zz+T6W6qWI4=; c=relaxed/simple; d=groups.io; h=From:Subject:Date:Message-Id:MIME-Version:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20240206; t=1714046581; v=1; b=OyTXys83+dUNeW2yXQvHoYVCVoQXMaas7SI7yqtGGzuOk1iyDGlbLBdRhVSTN1U3dm0UKMFC Y0C3N/sevPTiwq3UbSqUhw1Ceylscjbf9QtCICuuP1xihycmuaJDVT10Jju/bRm+8D9qhQ/YtPa CdX5BLAVbL68DkdWt2wZYRz1/1LgLeFFPbGos6bpkmTHHEPJWMr2xWzYnBIALRPGISfN0yhbs7Q lMzTqdacwLF3vF4tSNrj/GfdW0g4SBxXZXgTI4cpEkngnfiK2Tr2ZWy8h7tDGagAFSynbH43Kxb qsId4HpuOr1boOasmkV/uKp9uE8XJfmaJYrUg5yJIyCdg== X-Received: by 127.0.0.2 with SMTP id k6yvYY7687511xdJQ3uIFEiM; Thu, 25 Apr 2024 05:03:01 -0700 X-Received: from muminek.juszkiewicz.com.pl (muminek.juszkiewicz.com.pl [213.251.184.221]) by mx.groups.io with SMTP id smtpd.web10.15144.1714046579479856152 for ; Thu, 25 Apr 2024 05:02:59 -0700 X-Received: from localhost (localhost [127.0.0.1]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTP id 9DB7A260887; Thu, 25 Apr 2024 14:02:56 +0200 (CEST) X-Virus-Scanned: Debian amavis at juszkiewicz.com.pl X-Received: from muminek.juszkiewicz.com.pl ([127.0.0.1]) by localhost (muminek.juszkiewicz.com.pl [127.0.0.1]) (amavis, port 10024) with ESMTP id LxIwov4oYUah; Thu, 25 Apr 2024 14:02:54 +0200 (CEST) X-Received: from [192.168.168.24] (83.11.4.140.ipv4.supernova.orange.pl [83.11.4.140]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTPSA id BA6392601E2; Thu, 25 Apr 2024 14:02:53 +0200 (CEST) From: "Marcin Juszkiewicz" Subject: [edk2-devel] [PATCH WIP edk2-platforms 0/3] SbsaQemu: add support for multiple PCI Express buses Date: Thu, 25 Apr 2024 14:02:43 +0200 Message-Id: <20240425-review-multiple-pcie-0425-v1-0-68fdfd781f9e@linaro.org> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAGNGKmYC/42NSw6CMBCGr0Jm7Zi2FDGuvIdh0bRTmKRS0iJqC He3cAKX3/9cIVNiynCrVki0cOY4FpCnCuxgxp6QXWFQQmmhVYN7iN74fIWZp0A4WSY8nEZbqq+ y9a72UPpTIs+fY/vRFR44zzF9j6tF7uo/q4tEgcLY1hnvzcWpe+DRpHiOqYdu27Yfv4GLvcMAA AA= To: devel@edk2.groups.io Cc: Leif Lindholm , Ard Biesheuvel , Graeme Gregory , Ray Ni , Marcin Juszkiewicz Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Thu, 25 Apr 2024 05:02:59 -0700 Resent-From: marcin.juszkiewicz@linaro.org Reply-To: devel@edk2.groups.io,marcin.juszkiewicz@linaro.org List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: myBUMLxAHPunZLuqjO8H77Ysx7686176AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=OyTXys83; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=linaro.org (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io QEMU allows to have NUMA setup where each node has own cpus, memory and i/o. We already handle cpus and memory. This patchset adds support for having multiple PCI Express buses. SbsaQemu assumed that there is only bus 0. First patch does PCIe bus scan to find all host bridges (bus 0 one and additional 'pxb-pcie' ones). Second patch moves description of PCIe from DSDT to SSDT (one per each PCIe bus). So Operating System will know about all of them. Third patch moves generation of MCFG table to C. It is preparation to move PCIe Pcds from being fixed to dynamic ones. There are some booting issues with assigning resources for cards: pci 0000:00:03.0: BAR 15: no space for [mem size 0x00200000 64bit pref] pci 0000:00:03.0: BAR 15: failed to assign [mem size 0x00200000 64bit pref] pci 0000:00:01.0: BAR 6: no space for [mem size 0x00040000 pref] pci 0000:00:01.0: BAR 6: failed to assign [mem size 0x00040000 pref] pci 0000:00:03.0: BAR 13: no space for [io size 0x1000] pci 0000:00:03.0: BAR 13: failed to assign [io size 0x1000] Boot log (Linux + lspci + ACPI tables dump): https://people.linaro.org/~marcin.juszkiewicz/sbsa-ref/boot-linux-with-numa= -multiple-pcie-buses.txt I am wondering where I made mistakes in handling PCIe buses. Thanks go to Leif for pointing me to use of Aml to generate SSDT tables. Cc: Leif Lindholm Cc: Ard Biesheuvel Cc: Graeme Gregory Cc: Ray Ni To: devel@edk2.groups.io Signed-off-by: Marcin Juszkiewicz --- Marcin Juszkiewicz (3): SbsaQemu: scan for PCIe buses SbsaQemu: describe PCIe buses in SSDT tables SbsaQemu: generate MCFG table Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 2 + Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 - .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 37 +- .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiPcie.h | 23 + .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 170 +++++- .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiPcie.c | 576 ++++++++++++++++= ++++ .../SbsaQemuPciHostBridgeLib.c | 185 ++++--- Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 302 ---------- Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 43 -- .../Drivers/SbsaQemuAcpiDxe/SsdtTemplate.asl | 82 +++ 10 files changed, 982 insertions(+), 439 deletions(-) --- base-commit: 73cfdc4afff3e641be217b31b985761ef8338412 change-id: 20240425-review-multiple-pcie-0425-54ce3817fd3f Best regards, --=20 Marcin Juszkiewicz -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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