From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id 77CFD7803DA for ; Fri, 26 Apr 2024 12:17:52 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=1mag52gQ7LpmX6NYZzxUfcH9yKVy1H6ZzVagmQYyl3U=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20240206; t=1714133871; v=1; b=FhdFvDBUejm8V0rQ9+QWtU1n2dB5/7Vb/BgHtvQI26LxmBQqfAdmJyqG3/lnHuRjLG/6L2fs yoE8J2gDJFwnmrEwWgiXI3y2eHilehgZ6mKlK1J463ZGH7cCqi9BfmFokU/mkm1w9WhKbqcfk/K a2D4MQKYddvt5iIodbmj2tU5OIPIyeUcyp1q7BCV6lrH1w1pXy3G/4AVQ16vxrZtkCroUrdqnHL IyfCh8xZNN6BI5ys0sJVQrXxvKo/sw0hXXDjrJMczqviNJcNyKLxtBnMj6VZvEG4YF9OTSf9f60 oJxoVI4Lp7kNO1Ah9UQiZ/99zvckigeEdCfSEaFbKO7fg== X-Received: by 127.0.0.2 with SMTP id A6XBYY7687511xmLGTB8VhTv; Fri, 26 Apr 2024 05:17:51 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by mx.groups.io with SMTP id smtpd.web11.12554.1714133857432549514 for ; Fri, 26 Apr 2024 05:17:50 -0700 X-CSE-ConnectionGUID: PKAmMd1GTRuZglPvUDfQIA== X-CSE-MsgGUID: A6cWVvx6T662hcfR+dnsDw== X-IronPort-AV: E=McAfee;i="6600,9927,11055"; a="10027149" X-IronPort-AV: E=Sophos;i="6.07,232,1708416000"; d="scan'208";a="10027149" X-Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2024 05:17:51 -0700 X-CSE-ConnectionGUID: ocV9qcr3SAytpOIy9bsPhA== X-CSE-MsgGUID: 4/q5GY/qSGyfPgCDIxS1jw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,232,1708416000"; d="scan'208";a="62879131" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orviesa001.jf.intel.com with ESMTP; 26 Apr 2024 05:17:48 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Abdul Lateef Attar , Abner Chang , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v4 07/14] UefiCpuPkg/SmmRelocationLib: Add library instance for AMD Date: Fri, 26 Apr 2024 20:17:13 +0800 Message-Id: <20240426121720.54308-8-jiaxin.wu@intel.com> In-Reply-To: <20240426121720.54308-1-jiaxin.wu@intel.com> References: <20240426121720.54308-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Fri, 26 Apr 2024 05:17:50 -0700 Resent-From: jiaxin.wu@intel.com Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: WfZ7dH3356RAodup3uZnKIEYx7686176AA= X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=FhdFvDBU; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io Due to the definition difference of SMRAM Save State, SmmBase config in SMRAM Save State for AMD is also different. This patch provides the AmdSmmRelocationLib library instance to handle the SMRAM Save State difference. Cc: Abdul Lateef Attar Cc: Abner Chang Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu Acked-by: Ray Ni Reviewed-by: Abdul Lateef Attar --- ...mmRelocationLib.inf => AmdSmmRelocationLib.inf} | 5 +- ...SaveStateConfig.c => AmdSmramSaveStateConfig.c} | 91 ++++++++++------------ UefiCpuPkg/UefiCpuPkg.dsc | 1 + 3 files changed, 43 insertions(+), 54 deletions(-) copy UefiCpuPkg/Library/SmmRelocationLib/{SmmRelocationLib.inf => AmdSmmRelocationLib.inf} (89%) copy UefiCpuPkg/Library/SmmRelocationLib/{SmramSaveStateConfig.c => AmdSmramSaveStateConfig.c} (47%) diff --git a/UefiCpuPkg/Library/SmmRelocationLib/SmmRelocationLib.inf b/UefiCpuPkg/Library/SmmRelocationLib/AmdSmmRelocationLib.inf similarity index 89% copy from UefiCpuPkg/Library/SmmRelocationLib/SmmRelocationLib.inf copy to UefiCpuPkg/Library/SmmRelocationLib/AmdSmmRelocationLib.inf index 45fdaf35bc..e69079fa02 100644 --- a/UefiCpuPkg/Library/SmmRelocationLib/SmmRelocationLib.inf +++ b/UefiCpuPkg/Library/SmmRelocationLib/AmdSmmRelocationLib.inf @@ -13,18 +13,18 @@ ## [Defines] INF_VERSION = 0x00010005 BASE_NAME = SmmRelocationLib - FILE_GUID = 853E97B3-790C-4EA3-945C-8F622FC47FE8 + FILE_GUID = 65C74DCD-0D09-494A-8BFF-A64226EB8054 MODULE_TYPE = PEIM VERSION_STRING = 1.0 LIBRARY_CLASS = SmmRelocationLib [Sources] InternalSmmRelocationLib.h - SmramSaveStateConfig.c + AmdSmramSaveStateConfig.c SmmRelocationLib.c [Sources.Ia32] Ia32/Semaphore.c Ia32/SmmInit.nasm @@ -40,11 +40,10 @@ [LibraryClasses] BaseLib BaseMemoryLib CpuExceptionHandlerLib - CpuLib DebugLib HobLib LocalApicLib MemoryAllocationLib PcdLib diff --git a/UefiCpuPkg/Library/SmmRelocationLib/SmramSaveStateConfig.c b/UefiCpuPkg/Library/SmmRelocationLib/AmdSmramSaveStateConfig.c similarity index 47% copy from UefiCpuPkg/Library/SmmRelocationLib/SmramSaveStateConfig.c copy to UefiCpuPkg/Library/SmmRelocationLib/AmdSmramSaveStateConfig.c index 76d798aba5..068ae60887 100644 --- a/UefiCpuPkg/Library/SmmRelocationLib/SmramSaveStateConfig.c +++ b/UefiCpuPkg/Library/SmmRelocationLib/AmdSmramSaveStateConfig.c @@ -1,14 +1,17 @@ /** @file Config SMRAM Save State for SmmBases Relocation. + Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
Copyright (c) 2024, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include "InternalSmmRelocationLib.h" -#include +#include + +#define EFER_ADDRESS 0XC0000080ul /** Get the mode of the CPU at the time an SMI occurs @retval EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT 32 bit. @@ -18,44 +21,18 @@ UINT8 GetMmSaveStateRegisterLma ( VOID ) { - CPUID_VERSION_INFO_EAX RegEax; - CPUID_EXTENDED_CPU_SIG_EDX RegEdx; - UINTN FamilyId; - UINTN ModelId; - UINT32 Eax; - UINT8 SmmSaveStateRegisterLma; - - // - // Determine the mode of the CPU at the time an SMI occurs - // Intel(R) 64 and IA-32 Architectures Software Developer's Manual - // Volume 3C, Section 34.4.1.1 - // - RegEax.Uint32 = GetCpuFamilyModel (); - FamilyId = RegEax.Bits.FamilyId; - ModelId = RegEax.Bits.Model; - if ((FamilyId == 0x06) || (FamilyId == 0x0f)) { - ModelId = ModelId | RegEax.Bits.ExtendedModelId << 4; - } - - RegEdx.Uint32 = 0; - AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL); - if (Eax >= CPUID_EXTENDED_CPU_SIG) { - AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &(RegEdx.Uint32)); - } + UINT8 SmmSaveStateRegisterLma; + UINT32 LMAValue; SmmSaveStateRegisterLma = (UINT8)EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT; - if (RegEdx.Bits.LM) { - SmmSaveStateRegisterLma = (UINT8)EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT; - } - if (FamilyId == 0x06) { - if ((ModelId == 0x17) || (ModelId == 0x0f) || (ModelId == 0x1c)) { - SmmSaveStateRegisterLma = (UINT8)EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT; - } + LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA; + if (LMAValue) { + SmmSaveStateRegisterLma = (UINT8)EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT; } return SmmSaveStateRegisterLma; } @@ -69,22 +46,32 @@ VOID EFIAPI ConfigureSmBase ( IN UINT64 SmBase ) { - SMRAM_SAVE_STATE_MAP *CpuState; + AMD_SMRAM_SAVE_STATE_MAP *AmdCpuState; - CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET); + AmdCpuState = (AMD_SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET); - CpuState->x86.SMBASE = (UINT32)SmBase; + AmdCpuState->x64.SMBASE = (UINT32)SmBase; } /** - Hook the code executed immediately after an RSM instruction on the currently - executing CPU. The mode of code executed immediately after RSM must be - detected, and the appropriate hook must be selected. Always clear the auto - HALT restart flag if it is set. + This function updates the SMRAM save state on the currently executing CPU + to resume execution at a specific address after an RSM instruction. This + function must evaluate the SMRAM save state to determine the execution mode + the RSM instruction resumes and update the resume execution address with + either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart + flag in the SMRAM save state must always be cleared. This function returns + the value of the instruction pointer from the SMRAM save state that was + replaced. If this function returns 0, then the SMRAM save state was not + modified. + + This function is called during the very first SMI on each CPU after + SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode + to signal that the SMBASE of each CPU has been updated before the default + SMBASE address is used for the first SMI to the next CPU. @param[in,out] CpuState Pointer to SMRAM Save State Map for the currently executing CPU. @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to 32-bit mode from 64-bit SMM. @@ -100,37 +87,39 @@ HookReturnFromSmm ( IN OUT SMRAM_SAVE_STATE_MAP *CpuState, IN UINT64 NewInstructionPointer32, IN UINT64 NewInstructionPointer ) { - UINT64 OriginalInstructionPointer; + UINT64 OriginalInstructionPointer; + AMD_SMRAM_SAVE_STATE_MAP *AmdCpuState; - if (GetMmSaveStateRegisterLma () == EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT) { - OriginalInstructionPointer = (UINT64)CpuState->x86._EIP; - CpuState->x86._EIP = (UINT32)NewInstructionPointer; + AmdCpuState = (AMD_SMRAM_SAVE_STATE_MAP *)CpuState; + if (GetMmSaveStateRegisterLma () == EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT) { + OriginalInstructionPointer = (UINT64)AmdCpuState->x86._EIP; + AmdCpuState->x86._EIP = (UINT32)NewInstructionPointer; // // Clear the auto HALT restart flag so the RSM instruction returns // program control to the instruction following the HLT instruction. // - if ((CpuState->x86.AutoHALTRestart & BIT0) != 0) { - CpuState->x86.AutoHALTRestart &= ~BIT0; + if ((AmdCpuState->x86.AutoHALTRestart & BIT0) != 0) { + AmdCpuState->x86.AutoHALTRestart &= ~BIT0; } } else { - OriginalInstructionPointer = CpuState->x64._RIP; - if ((CpuState->x64.IA32_EFER & LMA) == 0) { - CpuState->x64._RIP = (UINT32)NewInstructionPointer32; + OriginalInstructionPointer = AmdCpuState->x64._RIP; + if ((AmdCpuState->x64.EFER & LMA) == 0) { + AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer32; } else { - CpuState->x64._RIP = (UINT32)NewInstructionPointer; + AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer; } // // Clear the auto HALT restart flag so the RSM instruction returns // program control to the instruction following the HLT instruction. // - if ((CpuState->x64.AutoHALTRestart & BIT0) != 0) { - CpuState->x64.AutoHALTRestart &= ~BIT0; + if ((AmdCpuState->x64.AutoHALTRestart & BIT0) != 0) { + AmdCpuState->x64.AutoHALTRestart &= ~BIT0; } } return OriginalInstructionPointer; } diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 8f67587e91..3d49f72588 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -200,10 +200,11 @@ } UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf UefiCpuPkg/Library/SmmRelocationLib/SmmRelocationLib.inf + UefiCpuPkg/Library/SmmRelocationLib/AmdSmmRelocationLib.inf [Components.X64] UefiCpuPkg/Library/CpuExceptionHandlerLib/UnitTest/DxeCpuExceptionHandlerLibUnitTest.inf [Components.RISCV64] -- 2.16.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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