From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id 0C31B78003C for ; Fri, 26 Apr 2024 19:51:53 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=+H8U/MTMWUHzmj08yJcLdWnU5aOV0g2mrCa9DYjOkfg=; c=relaxed/simple; d=groups.io; h=Received-SPF:From:To:CC:Subject:Date:Message-ID:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20240206; t=1714161112; v=1; b=QbvVUcgkRHsApDXsyRfm0/q2vCneTEsoURe04eqE+fKvG3ItF9XPro/1khc6OFgeppIbA3Le A87lWGxiG4XB/Jgvc/DjWZtAy/usew341nBLAfC27jU1zBTeMKqj7arvSCty7V3FKLswyWW12WO 5BCHg9FiDSRvgJBg3tsZlm5r183x89B04M16nhMYyqCzzZ1hBgcPfwGYA63COI/9EnAw4O/di4r tAuXuCAwkc7eRuFLmdMMiDm/HsTkLu8PF3atDN8ov6DlGFhJAYGlNzD/x7beJhsaiYYZq5H9uK3 v2xrZmZLNUD+k3RpQZEiKrquWszJRI7raUfFvKVrZXycA== X-Received: by 127.0.0.2 with SMTP id BW2sYY7687511x22D197bK7j; Fri, 26 Apr 2024 12:51:52 -0700 X-Received: from NAM12-MW2-obe.outbound.protection.outlook.com (NAM12-MW2-obe.outbound.protection.outlook.com [40.107.244.77]) by mx.groups.io with SMTP id smtpd.web11.5217.1714161111834261977 for ; Fri, 26 Apr 2024 12:51:52 -0700 X-Received: from MN2PR15CA0034.namprd15.prod.outlook.com (2603:10b6:208:1b4::47) by PH0PR12MB7813.namprd12.prod.outlook.com (2603:10b6:510:286::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7472.48; Fri, 26 Apr 2024 19:51:48 +0000 X-Received: from MN1PEPF0000ECD6.namprd02.prod.outlook.com (2603:10b6:208:1b4:cafe::91) by MN2PR15CA0034.outlook.office365.com (2603:10b6:208:1b4::47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.26 via Frontend Transport; Fri, 26 Apr 2024 19:51:48 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C X-Received: from SATLEXMB04.amd.com (165.204.84.17) by MN1PEPF0000ECD6.mail.protection.outlook.com (10.167.242.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7519.19 via Frontend Transport; Fri, 26 Apr 2024 19:51:48 +0000 X-Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 26 Apr 2024 14:51:47 -0500 From: "Roth, Michael via groups.io" To: CC: Tom Lendacky , Ard Biesheuvel , Gerd Hoffmann , Erdem Aktas , Jiewen Yao , Min Xu , Jianyong Wu , Anatol Belski Subject: [edk2-devel] [PATCH v3] OvmfPkg: Don't make APIC MMIO accesses with encryption bit set Date: Fri, 26 Apr 2024 14:50:07 -0500 Message-ID: <20240426195007.1964795-1-michael.roth@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD6:EE_|PH0PR12MB7813:EE_ X-MS-Office365-Filtering-Correlation-Id: ba64491f-aa11-4a6e-f6a9-08dc662a4f24 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?mu/VeNse2EcH5aFR1uGYgBCKP60UZzz/G4cWVJKL/4E86n91yIUavJAGLskg?= =?us-ascii?Q?ypNe/6GGKmhwllLcyRntKJHzLN/gssQCJGxamQ7eDvk+QPZh/rP114AA/M/2?= =?us-ascii?Q?nREaEd/KgiL3e1pTFLybwYsCQH9NsjODKnGj263XYyuCNJ33erxTNb78iVXE?= =?us-ascii?Q?bu0OtJptTaQyLIteEz3d9yix5hxtdILBtUkF1/vYGHSqWk+KcW4FfnvPL4h+?= =?us-ascii?Q?XjBy3qkjHclXsAIZI12eGjRGIBd60Q2jLno9xk+vEgXrG9Qn942WuVldhsdO?= =?us-ascii?Q?Q3LV2s8DQWTXFLfvJ5ALmRLiO0+vDruOc0Ovv689ukbGCeNU6FRuGTdURo30?= =?us-ascii?Q?Ak63nUcgl3TM2Lu3TX/mreZ9nJ2BHHMef+kd3uH4twHL+mjszkMPCQNY9zap?= =?us-ascii?Q?HavJzh+Uj39ymWlgJ6OZOeARIdC+/17C/gC4uWxLAokVMAIjHI5GhgE1GB/M?= =?us-ascii?Q?QHpaaxLjPUwde6mWt70i0tER7PgcZX5PVg8KEZ+G4QexCObAL8ui3Bv/3wVb?= =?us-ascii?Q?lvi8UjeQxFyuSjKwcCTN2ScHCUhNLoBLHP782OgWCiyFQ9qHnBUGecHuAUSL?= =?us-ascii?Q?gJ43pTT3lu2eemGD5Jy4Dnq76OGJ6D6g+q+eQsb3tlfVz2k9LvXSP3VUq+5g?= =?us-ascii?Q?to1KOLB0O+6Xuk/uDuHnvXU3lbaY+OHOmI0UBXcjunTKWjxtYY24v6TCam0J?= =?us-ascii?Q?s28Ob6wwDd9TfaLbPWpezFEUozNRPF+hpOSn/+QVq0WtMqBjAB1q7AAT52a3?= =?us-ascii?Q?XIgZ1G7mSExj7e+LY/rVhmJ7mdDE4Vqf+HCJveaUjqP5aBJSn2rmFvmjYhju?= =?us-ascii?Q?elM0n4r4h2k/T/GqPDmeEJmboaa8QoMGlG5P7BRj4UER9p06fivyoZn/0sc/?= =?us-ascii?Q?JWeurIebOWhofmwJwA4J8qSuwaPUaCIKaYPYzrfUJ3qRZPQbyLrLv0cCSWWn?= =?us-ascii?Q?SPv/K3IyvJj2F5Kco+vNG8sLFQPCPR+PJD4R45FDGXP87szLfT1MVnkYg6DD?= =?us-ascii?Q?bdRC3jGzb3vRb3cZ3vUoWx09XQ8kKFhuMtIf7klOcSLga+n9TQHLJOmaMQ+R?= =?us-ascii?Q?yM2EzEXp3iNfZBTIIixr54IcfxP7mQfX6aAKJHZs4DNAMzK5kCsFBYQ+fwgY?= =?us-ascii?Q?gNCho/H+2nZSgn/MN/8HWd5MR1cie08JV7Y6IBDKTo7/8LekhT2zIUP2qpTd?= =?us-ascii?Q?GbVxBIIClCixwMHKX3PC5b1tg7r1R5z9xHYdtDNqgl+X6/M9v9I39Kwi1L5G?= =?us-ascii?Q?M9yokjcCyyaWrOHnHSCYEP2tZjgd8DWD2BC1INLTf7Phgm6VOcoYWegvdk7J?= =?us-ascii?Q?s8rljDfoL+ENsVlWWdr+23N1?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Apr 2024 19:51:48.0999 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ba64491f-aa11-4a6e-f6a9-08dc662a4f24 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7813 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Fri, 26 Apr 2024 12:51:52 -0700 Resent-From: Michael.Roth@amd.com Reply-To: devel@edk2.groups.io,Michael.Roth@amd.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 57kdzCy94zrHoc48o1Gszx9vx7686176AA= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=QbvVUcgk; dmarc=pass (policy=none) header.from=groups.io; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io For the most part, OVMF will clear the encryption bit for MMIO regions, but there is currently one known exception during SEC when the APIC base address is accessed via MMIO with the encryption bit set for SEV-ES/SEV-SNP guests. In the case of SEV-SNP, this requires special handling on the hypervisor side which may not be available in the future[1], so make the necessary changes in the SEC-configured page table to clear the encryption bit for 4K region containing the APIC base address. Since CpuPageTableLib is used to handle the splitting, some additional care must be taken to clear the C-bit in all non-leaf PTEs since the library expects that to be the case. Add handling for that when setting up the SEC page table. While here, drop special handling for the APIC base address in the SEV-ES/SNP #VC handler. [1] https://lore.kernel.org/lkml/20240208002420.34mvemnzrwwsaesw@amd.com/#t Suggested-by: Tom Lendacky Cc: Ard Biesheuvel Cc: Gerd Hoffmann Cc: Erdem Aktas Cc: Jiewen Yao Cc: Min Xu Cc: Tom Lendacky Cc: Jianyong Wu Cc: Anatol Belski Signed-off-by: Michael Roth --- v3: - also clear C-bit for non-leaf PTEs containing GHCB range - add missing Cc's to commit log v2: - use CpuPageTableLib to handle splitting (Gerd, Tom) OvmfPkg/AmdSev/AmdSevX64.fdf | 5 +- OvmfPkg/Bhyve/BhyveX64.dsc | 1 + OvmfPkg/CloudHv/CloudHvX64.fdf | 5 +- OvmfPkg/Library/CcExitLib/CcExitVcHandler.c | 12 +---- OvmfPkg/Microvm/MicrovmX64.fdf | 3 ++ OvmfPkg/OvmfPkg.dec | 5 ++ OvmfPkg/OvmfPkgX64.fdf | 5 +- OvmfPkg/ResetVector/Ia32/AmdSev.asm | 5 +- OvmfPkg/ResetVector/Ia32/PageTables64.asm | 20 +++---- OvmfPkg/Sec/AmdSev.c | 58 +++++++++++++++++++++ OvmfPkg/Sec/AmdSev.h | 14 +++++ OvmfPkg/Sec/SecMain.c | 1 + OvmfPkg/Sec/SecMain.inf | 3 ++ 13 files changed, 112 insertions(+), 25 deletions(-) diff --git a/OvmfPkg/AmdSev/AmdSevX64.fdf b/OvmfPkg/AmdSev/AmdSevX64.fdf index d49555c6c8..595945181c 100644 --- a/OvmfPkg/AmdSev/AmdSevX64.fdf +++ b/OvmfPkg/AmdSev/AmdSevX64.fdf @@ -77,7 +77,10 @@ gUefiOvmfPkgTokenSpaceGuid.PcdSevLaunchSecretBase|gUefiO= vmfPkgTokenSpaceGuid.Pcd 0x010C00|0x000400 gUefiOvmfPkgTokenSpaceGuid.PcdQemuHashTableBase|gUefiOvmfPkgTokenSpaceGuid= .PcdQemuHashTableSize =20 -0x011000|0x00F000 +0x011000|0x001000 +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecApicPageTableBase|gUefiOvmfPkgTokenSp= aceGuid.PcdOvmfSecApicPageTableSize + +0x012000|0x00E000 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|gUefiOvmfPkgTokenSpace= Guid.PcdOvmfSecPeiTempRamSize =20 0x020000|0x0E0000 diff --git a/OvmfPkg/Bhyve/BhyveX64.dsc b/OvmfPkg/Bhyve/BhyveX64.dsc index 6f305d690d..78050959f8 100644 --- a/OvmfPkg/Bhyve/BhyveX64.dsc +++ b/OvmfPkg/Bhyve/BhyveX64.dsc @@ -174,6 +174,7 @@ PeiHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/PeiHardwareInfoLib.in= f DxeHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.in= f ImagePropertiesRecordLib|MdeModulePkg/Library/ImagePropertiesRecordLib/I= magePropertiesRecordLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf =20 CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf diff --git a/OvmfPkg/CloudHv/CloudHvX64.fdf b/OvmfPkg/CloudHv/CloudHvX64.fd= f index eae3ada191..3e6688b103 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.fdf +++ b/OvmfPkg/CloudHv/CloudHvX64.fdf @@ -76,7 +76,10 @@ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase|gUefiOvmfPkg= TokenSpaceGuid.PcdOvmfCp 0x00F000|0x001000 gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtr|gUefiOvmfPkgTokenS= paceGuid.PcdXenPvhStartOfDayStructPtrSize =20 -0x010000|0x010000 +0x010000|0x001000 +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecApicPageTableBase|gUefiOvmfPkgTokenSp= aceGuid.PcdOvmfSecApicPageTableSize + +0x011000|0x00F000 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|gUefiOvmfPkgTokenSpace= Guid.PcdOvmfSecPeiTempRamSize =20 0x020000|0x0E0000 diff --git a/OvmfPkg/Library/CcExitLib/CcExitVcHandler.c b/OvmfPkg/Library/= CcExitLib/CcExitVcHandler.c index 549375dfed..da8f1e5db9 100644 --- a/OvmfPkg/Library/CcExitLib/CcExitVcHandler.c +++ b/OvmfPkg/Library/CcExitLib/CcExitVcHandler.c @@ -98,7 +98,7 @@ UnsupportedExit ( Validate that the MMIO memory access is not to encrypted memory. =20 Examine the pagetable entry for the memory specified. MMIO should not be - performed against encrypted memory. MMIO to the APIC page is always allo= wed. + performed against encrypted memory. =20 @param[in] Ghcb Pointer to the Guest-Hypervisor Communication = Block @param[in] MemoryAddress Memory address to validate @@ -118,16 +118,6 @@ ValidateMmioMemory ( { MEM_ENCRYPT_SEV_ADDRESS_RANGE_STATE State; GHCB_EVENT_INJECTION GpEvent; - UINTN Address; - - // - // Allow APIC accesses (which will have the encryption bit set during - // SEC and PEI phases). - // - Address =3D MemoryAddress & ~(SIZE_4KB - 1); - if (Address =3D=3D GetLocalApicBaseAddress ()) { - return 0; - } =20 State =3D MemEncryptSevGetAddressRangeState ( 0, diff --git a/OvmfPkg/Microvm/MicrovmX64.fdf b/OvmfPkg/Microvm/MicrovmX64.fd= f index 825bf9f5e4..055e659a35 100644 --- a/OvmfPkg/Microvm/MicrovmX64.fdf +++ b/OvmfPkg/Microvm/MicrovmX64.fdf @@ -62,6 +62,9 @@ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase|gUefiOvmfP= kgTokenSpaceGuid.PcdOvm 0x00C000|0x001000 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase|gUefiOvmfPkgTokenSpace= Guid.PcdOvmfSecGhcbBackupSize =20 +0x00D000|0x001000 +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecApicPageTableBase|gUefiOvmfPkgTokenSp= aceGuid.PcdOvmfSecApicPageTableSize + 0x010000|0x010000 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|gUefiOvmfPkgTokenSpace= Guid.PcdOvmfSecPeiTempRamSize =20 diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 2f7bded926..b23219ebd4 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -277,6 +277,11 @@ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase|0|UINT32|0x44 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupSize|0|UINT32|0x45 =20 + ## Specify the extra page table needed to mark the APIC MMIO range as un= encrypted. + # The value should be a multiple of 4KB for each. + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecApicPageTableBase|0x0|UINT32|0x72 + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecApicPageTableSize|0x0|UINT32|0x73 + ## The base address and size of the SEV Launch Secret Area provisioned # after remote attestation. If this is set in the .fdf, the platform # is responsible for protecting the area from DXE phase overwrites. diff --git a/OvmfPkg/OvmfPkgX64.fdf b/OvmfPkg/OvmfPkgX64.fdf index c2d3cc901e..b6e8f43566 100644 --- a/OvmfPkg/OvmfPkgX64.fdf +++ b/OvmfPkg/OvmfPkgX64.fdf @@ -97,7 +97,10 @@ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase|gUefiOvmfPkg= TokenSpaceGuid.PcdOvmfCp 0x00F000|0x001000 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecSvsmCaaBase|gUefiOvmfPkgTokenSpaceGui= d.PcdOvmfSecSvsmCaaSize =20 -0x010000|0x010000 +0x010000|0x001000 +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecApicPageTableBase|gUefiOvmfPkgTokenSp= aceGuid.PcdOvmfSecApicPageTableSize + +0x011000|0x00F000 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|gUefiOvmfPkgTokenSpace= Guid.PcdOvmfSecPeiTempRamSize =20 0x020000|0x0E0000 diff --git a/OvmfPkg/ResetVector/Ia32/AmdSev.asm b/OvmfPkg/ResetVector/Ia32= /AmdSev.asm index 23e4c5ebbe..827c874312 100644 --- a/OvmfPkg/ResetVector/Ia32/AmdSev.asm +++ b/OvmfPkg/ResetVector/Ia32/AmdSev.asm @@ -162,11 +162,14 @@ SevClearPageEncMaskForGhcbPage: ; ; The initial GHCB will live at GHCB_BASE and needs to be un-encrypted= . ; This requires the 2MB page for this range be broken down into 512 4K= B - ; pages. All will be marked encrypted, except for the GHCB. + ; pages. All will be marked encrypted, except for the GHCB. Since the + ; original PMD entry is no longer a leaf entry, remove the encryption + ; bit when pointing to the PTE page. ; mov ecx, (GHCB_BASE >> 21) mov eax, GHCB_PT_ADDR + PAGE_PDP_ATTR mov [ecx * 8 + PT_ADDR (0x2000)], eax + mov [ecx * 8 + PT_ADDR (0x2000) + 4], strict dword 0 =20 ; ; Page Table Entries (512 * 4KB entries =3D> 2MB) diff --git a/OvmfPkg/ResetVector/Ia32/PageTables64.asm b/OvmfPkg/ResetVecto= r/Ia32/PageTables64.asm index 474d22dbfa..d913a39d46 100644 --- a/OvmfPkg/ResetVector/Ia32/PageTables64.asm +++ b/OvmfPkg/ResetVector/Ia32/PageTables64.asm @@ -67,7 +67,7 @@ BITS 32 ; ; Create page tables for 4-level paging ; -; Argument: upper 32 bits of the page table entries +; Argument: upper 32 bits of the leaf page table entries ; %macro CreatePageTables4Level 1 =20 @@ -78,19 +78,19 @@ BITS 32 ; Top level Page Directory Pointers (1 * 512GB entry) ; mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDE_DIRECTORY_ATTR - mov dword[PT_ADDR (4)], %1 + mov dword[PT_ADDR (4)], 0 =20 ; ; Next level Page Directory Pointers (4 * 1GB entries =3D> 4GB) ; mov dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDE_DIRECTORY= _ATTR - mov dword[PT_ADDR (0x1004)], %1 + mov dword[PT_ADDR (0x1004)], 0 mov dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDE_DIRECTORY= _ATTR - mov dword[PT_ADDR (0x100C)], %1 + mov dword[PT_ADDR (0x100C)], 0 mov dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDE_DIRECTORY= _ATTR - mov dword[PT_ADDR (0x1014)], %1 + mov dword[PT_ADDR (0x1014)], 0 mov dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDE_DIRECTORY= _ATTR - mov dword[PT_ADDR (0x101C)], %1 + mov dword[PT_ADDR (0x101C)], 0 =20 ; ; Page Table Entries (2048 * 2MB entries =3D> 4GB) @@ -141,7 +141,7 @@ BITS 32 ; ; Create page tables for 5-level paging with gigabyte pages ; -; Argument: upper 32 bits of the page table entries +; Argument: upper 32 bits of the leaf page table entries ; ; We have 6 pages available for the early page tables, ; we use four of them: @@ -164,15 +164,15 @@ BITS 32 =20 ; level 5 mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDE_DIRECTORY_ATTR - mov dword[PT_ADDR (4)], %1 + mov dword[PT_ADDR (4)], 0 =20 ; level 4 mov dword[PT_ADDR (0x1000)], PT_ADDR (0x3000) + PAGE_PDE_DIRECTORY= _ATTR - mov dword[PT_ADDR (0x1004)], %1 + mov dword[PT_ADDR (0x1004)], 0 =20 ; level 3 (1x -> level 2, 3x 1GB) mov dword[PT_ADDR (0x3000)], PT_ADDR (0x2000) + PAGE_PDE_DIRECTORY= _ATTR - mov dword[PT_ADDR (0x3004)], %1 + mov dword[PT_ADDR (0x3004)], 0 mov dword[PT_ADDR (0x3008)], (1 << 30) + PAGE_PDE_LARGEPAGE_ATTR mov dword[PT_ADDR (0x300c)], %1 mov dword[PT_ADDR (0x3010)], (2 << 30) + PAGE_PDE_LARGEPAGE_ATTR diff --git a/OvmfPkg/Sec/AmdSev.c b/OvmfPkg/Sec/AmdSev.c index 520b125132..89fba2fd18 100644 --- a/OvmfPkg/Sec/AmdSev.c +++ b/OvmfPkg/Sec/AmdSev.c @@ -8,7 +8,10 @@ **/ =20 #include +#include +#include #include +#include #include #include #include @@ -301,3 +304,58 @@ SecValidateSystemRam ( MemEncryptSevSnpPreValidateSystemRam (Start, EFI_SIZE_TO_PAGES ((UINTN= )(End - Start))); } } + +/** + Map known MMIO regions unencrypted if SEV-ES is active. + + During early booting, page table entries default to having the encryptio= n bit + set for SEV-ES/SEV-SNP guests. In cases where there is MMIO to an addres= s, the + encryption bit should be cleared. Clear it here for any known MMIO acces= ses + during SEC, which is currently just the APIC base address. + +**/ +VOID +SecMapApicBaseUnencrypted ( + VOID + ) +{ + PHYSICAL_ADDRESS Cr3; + UINT64 ApicAddress; + VOID *Buffer; + UINTN BufferSize; + IA32_MAP_ATTRIBUTE MapAttribute; + IA32_MAP_ATTRIBUTE MapMask; + RETURN_STATUS Status; + + if (!SevEsIsEnabled ()) { + return; + } + + ApicAddress =3D (UINT64)GetLocalApicBaseAddress (); + Buffer =3D (VOID *)(UINTN)FixedPcdGet32 (PcdOvmfSecApicPageTableBas= e); + Cr3 =3D AsmReadCr3 (); + + MapAttribute.Uint64 =3D ApicAddress; + MapAttribute.Bits.Present =3D 1; + MapAttribute.Bits.ReadWrite =3D 1; + MapMask.Uint64 =3D MAX_UINT64; + BufferSize =3D SIZE_4KB; + + Status =3D PageTableMap ( + (UINTN *)&Cr3, + Paging4Level, + Buffer, + &BufferSize, + ApicAddress, + SIZE_4KB, + &MapAttribute, + &MapMask, + NULL + ); + if (RETURN_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to map APIC MMIO region as unencrypted: %= d\n", Status)); + ASSERT (FALSE); + } + + CpuFlushTlb (); +} diff --git a/OvmfPkg/Sec/AmdSev.h b/OvmfPkg/Sec/AmdSev.h index f75877096e..c5ab0d5a0b 100644 --- a/OvmfPkg/Sec/AmdSev.h +++ b/OvmfPkg/Sec/AmdSev.h @@ -91,4 +91,18 @@ SevSnpIsEnabled ( VOID ); =20 +/** + Map MMIO regions unencrypted if SEV-ES is active. + + During early booting, page table entries default to having the encryptio= n bit + set for SEV-ES/SEV-SNP guests. In cases where there is MMIO to an addres= s, the + encryption bit should be cleared. Clear it here for any known MMIO acces= ses + during SEC, which is currently just the APIC base address. + +**/ +VOID +SecMapApicBaseUnencrypted ( + VOID + ); + #endif diff --git a/OvmfPkg/Sec/SecMain.c b/OvmfPkg/Sec/SecMain.c index a30d4ce09e..60dfa61842 100644 --- a/OvmfPkg/Sec/SecMain.c +++ b/OvmfPkg/Sec/SecMain.c @@ -938,6 +938,7 @@ SecCoreStartupWithStack ( // interrupts before initializing the Debug Agent and the debug timer is // enabled. // + SecMapApicBaseUnencrypted (); InitializeApicTimer (0, MAX_UINT32, TRUE, 5); DisableApicTimerInterrupt (); =20 diff --git a/OvmfPkg/Sec/SecMain.inf b/OvmfPkg/Sec/SecMain.inf index dca932a474..88c2d3fb6d 100644 --- a/OvmfPkg/Sec/SecMain.inf +++ b/OvmfPkg/Sec/SecMain.inf @@ -55,6 +55,7 @@ MemEncryptSevLib CpuExceptionHandlerLib CcProbeLib + CpuPageTableLib =20 [Ppis] gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED @@ -83,6 +84,8 @@ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase gUefiOvmfPkgTokenSpaceGuid.PcdTdxAcceptPageSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecApicPageTableBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecApicPageTableSize =20 [FeaturePcd] gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#118349): https://edk2.groups.io/g/devel/message/118349 Mute This Topic: https://groups.io/mt/105757219/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-