From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id 6075EAC107D for ; Fri, 10 May 2024 10:09:17 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=CuvwKBH81z5tZG/hUD1e0ePGpf7fFyaRN8CzBy2WlBI=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20240206; t=1715335756; v=1; b=QHcdb5kox/M29zLcf5Rnzo/HrXiDqJXH9WC6nTSrKxQQjmqofaAVLtgLAVEMSfwOivfAK5oI YRlKJELJY93usOagLqmBsFTAbQKvdUV0NZdWhHKN5svCbiOOqdO9of7HFhK6YofeK6en0OfSfb1 Dz7GQ18l5jLR95h8qdkY8eLNZHYYe5O+eA0WYQszLec0f/9dsVnXAppQZ0f67/p2ll7riYA5U6E Cv0ktFjOPOxPqC8hIP0Fyha4kJmu2uiHrCai9QBDcrv16Vu032ovh0/9q7D9rQkNizzZbDJRnZw 6Miu6VF4gDYJVVYV1cIdbm16glSWVbJE3iCfemcwnEaSQ== X-Received: by 127.0.0.2 with SMTP id oeYHYY7687511xRzXAjCCMrO; Fri, 10 May 2024 03:09:16 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by mx.groups.io with SMTP id smtpd.web10.9485.1715335727366928454 for ; Fri, 10 May 2024 03:09:14 -0700 X-CSE-ConnectionGUID: w5qA0zNjREKrE44kNIDLZA== X-CSE-MsgGUID: 5oowM++ETTuThs9sctImxg== X-IronPort-AV: E=McAfee;i="6600,9927,11068"; a="28819185" X-IronPort-AV: E=Sophos;i="6.08,150,1712646000"; d="scan'208";a="28819185" X-Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2024 03:09:14 -0700 X-CSE-ConnectionGUID: 9ZXeqPqgSR2mTtDOQppcZA== X-CSE-MsgGUID: lKj22f0jQGqJ+9vnPp5nyg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,150,1712646000"; d="scan'208";a="60424297" X-Received: from unknown (HELO shwdeopenlab702.ccr.corp.intel.com) ([10.239.55.43]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2024 03:09:13 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek , Rahul Kumar , Gerd Hoffmann , Jiaxin Wu Subject: [edk2-devel] [PATCH 10/18] UefiCpuPkg:Relocate AP to new safe buffer in PeiMpLib Date: Fri, 10 May 2024 18:08:19 +0800 Message-Id: <20240510100827.1903-11-dun.tan@intel.com> In-Reply-To: <20240510100827.1903-1-dun.tan@intel.com> References: <20240510100827.1903-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Fri, 10 May 2024 03:09:14 -0700 Resent-From: dun.tan@intel.com Reply-To: devel@edk2.groups.io,dun.tan@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: BW9aeK6I8xEfe9opKhqOghjpx7686176AA= Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=QHcdb5ko; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io In this commit, change PeiMpLib to install callback of gEdkiiEndOfS3ResumeGuid to relocate AP to new safe buffer. The gEdkiiEndOfS3ResumeGuid is installed in S3Resume.c before jmping to OS waking vector. Previously, code in CpuS3.c of PiSmmCpuDxe driver will prepare the new safe buffer for AP and place AP in hlt loop state. With this code change, we can remove the Machine Instructions of mApHltLoopCode in PiSmmCpuDxe. Also we can reuse the related code in DxeMpLib for PeiMpLib. Signed-off-by: Dun Tan Cc: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Jiaxin Wu --- UefiCpuPkg/Library/MpInitLib/MpLib.h | 3 +++ UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 4 ++++ UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 152 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 159 insertions(+) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpInitLib/MpLib.h index 11e0d2661f..3efd913395 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -33,6 +33,7 @@ #include #include #include +#include #include #include @@ -68,6 +69,8 @@ // #define DEFAULT_MAX_MICROCODE_PATCH_NUM 8 +#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull + // // Data structure for microcode patch information // diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf index e31e34b6f9..8736690348 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf @@ -25,10 +25,12 @@ [Sources.IA32] Ia32/AmdSev.c Ia32/MpFuncs.nasm + Ia32/CreatePageTable.c [Sources.X64] X64/AmdSev.c X64/MpFuncs.nasm + X64/CreatePageTable.c [Sources.IA32, Sources.X64] AmdSev.c @@ -64,6 +66,7 @@ LocalApicLib MicrocodeLib MtrrLib + CpuPageTableLib [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## CONSUMES @@ -87,6 +90,7 @@ gEdkiiS3SmmInitDoneGuid gEdkiiMicrocodePatchHobGuid gGhcbApicIdsGuid ## SOMETIMES_CONSUMES + gEdkiiEndOfS3ResumeGuid [Guids.LoongArch64] gProcessorResourceHobGuid ## SOMETIMES_CONSUMES ## HOB diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c index 4d3acb491f..deb5fc3aac 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c @@ -9,6 +9,7 @@ #include "MpLib.h" #include #include +#include #include STATIC UINT64 mSevEsPeiWakeupBuffer = BASE_1MB; @@ -449,6 +450,47 @@ BuildMicrocodeCacheHob ( return; } +/** + S3 SMM Init Done notification function. + + @param PeiServices Indirect reference to the PEI Services Table. + @param NotifyDesc Address of the notification descriptor data structure. + @param InvokePpi Address of the PPI that was invoked. + + @retval EFI_SUCCESS The function completes successfully. + +**/ +EFI_STATUS +EFIAPI +NotifyOnEndOfS3Resume ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc, + IN VOID *InvokePpi + ) +{ + CPU_MP_DATA *CpuMpData; + + CpuMpData = GetCpuMpData (); + mNumberToFinish = CpuMpData->CpuCount - 1; + WakeUpAP (CpuMpData, TRUE, 0, RelocateApLoop, NULL, TRUE); + while (mNumberToFinish > 0) { + CpuPause (); + } + + DEBUG ((DEBUG_INFO, "%a() done!\n", __func__)); + + return EFI_SUCCESS; +} + +// +// Global function +// +EFI_PEI_NOTIFY_DESCRIPTOR mEndOfS3ResumeNotifyDesc = { + EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gEdkiiEndOfS3ResumeGuid, + NotifyOnEndOfS3Resume +}; + /** Initialize global data for MP support. @@ -463,12 +505,16 @@ InitMpGlobalData ( BuildMicrocodeCacheHob (CpuMpData); SaveCpuMpData (CpuMpData); + PrepareApLoopCode (CpuMpData); /// /// Install Notify /// Status = PeiServicesNotifyPpi (&mS3SmmInitDoneNotifyDesc); ASSERT_EFI_ERROR (Status); + + Status = PeiServicesNotifyPpi (&mEndOfS3ResumeNotifyDesc); + ASSERT_EFI_ERROR (Status); } /** @@ -815,3 +861,109 @@ PlatformShadowMicrocode ( return EFI_SUCCESS; } + +/** + Allocate buffer for ApLoopCode. + + @param[in] Pages Number of pages to allocate. + @param[in, out] Address Pointer to the allocated buffer. +**/ +VOID +AllocateApLoopCodeBuffer ( + IN UINTN Pages, + IN OUT EFI_PHYSICAL_ADDRESS *Address + ) +{ + EFI_STATUS Status; + + Status = PeiServicesAllocatePages (EfiACPIMemoryNVS, Pages, Address); + if (EFI_ERROR (Status)) { + *Address = 0; + } +} + +/** + Remove Nx protection for the range specific by BaseAddress and Length. + + The PEI implementation uses CpuPageTableLib to change the attribute. + The DXE implementation uses gDS to change the attribute. + + @param[in] BaseAddress BaseAddress of the range. + @param[in] Length Length of the range. +**/ +VOID +RemoveNxprotection ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINTN Length + ) +{ + EFI_STATUS Status; + UINTN PageTable; + EFI_PHYSICAL_ADDRESS Buffer; + UINTN BufferSize; + IA32_MAP_ATTRIBUTE MapAttribute; + IA32_MAP_ATTRIBUTE MapMask; + PAGING_MODE PagingMode; + IA32_CR4 Cr4; + BOOLEAN Page5LevelSupport; + UINT32 RegEax; + BOOLEAN Page1GSupport; + CPUID_EXTENDED_CPU_SIG_EDX RegEdx; + + if (sizeof (UINTN) == sizeof (UINT64)) { + // + // Check Page5Level Support or not. + // + Cr4.UintN = AsmReadCr4 (); + Page5LevelSupport = (Cr4.Bits.LA57 ? TRUE : FALSE); + + // + // Check Page1G Support or not. + // + Page1GSupport = FALSE; + AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); + if (RegEax >= CPUID_EXTENDED_CPU_SIG) { + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx.Uint32); + if (RegEdx.Bits.Page1GB != 0) { + Page1GSupport = TRUE; + } + } + + // + // Decide Paging Mode according Page5LevelSupport & Page1GSupport. + // + if (Page5LevelSupport) { + PagingMode = Page1GSupport ? Paging5Level1GB : Paging5Level; + } else { + PagingMode = Page1GSupport ? Paging4Level1GB : Paging4Level; + } + } else { + PagingMode = PagingPae; + } + + MapAttribute.Uint64 = 0; + MapMask.Uint64 = 0; + MapMask.Bits.Nx = 1; + PageTable = AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; + BufferSize = 0; + + // + // Get required buffer size for changing the pagetable. + // + Status = PageTableMap (&PageTable, PagingMode, 0, &BufferSize, BaseAddress, Length, &MapAttribute, &MapMask, NULL); + if (Status == EFI_BUFFER_TOO_SMALL) { + // + // Allocate required Buffer. + // + Status = PeiServicesAllocatePages ( + EfiBootServicesData, + EFI_SIZE_TO_PAGES (BufferSize), + &Buffer + ); + ASSERT_EFI_ERROR (Status); + Status = PageTableMap (&PageTable, PagingMode, (VOID *)(UINTN)Buffer, &BufferSize, BaseAddress, Length, &MapAttribute, &MapMask, NULL); + } + + ASSERT_EFI_ERROR (Status); + AsmWriteCr3 (PageTable); +} -- 2.31.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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