From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id E61E774004A for ; Tue, 28 May 2024 10:31:57 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=Qz0ujN3Y20B0PbqgVsPyrxLWdK0Ujypj4X+OsMLC/fk=; c=relaxed/simple; d=groups.io; h=From:Subject:Date:Message-Id:MIME-Version:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20240206; t=1716892317; v=1; b=ze4fRM6TZVId8hwFQGFf1fYtM8uwZHxXjdB05uYTUpTxRyKtCJ5zehB1VYkETKNstCApEJDn SqbZJaB6VlVc6BNhF34yMommT0hLQV2PZ1mujkcSOvKOa5V+sfXqd6eH+/T2BOmU4alOniIqrwP 0RSrPaT4q2+NTaH0IMF2EDgNmRhdjtXk/7qCpDZF51J9s5YON/TzMETCqeb3xOToW57cRZxNczx ESJqD1R9h2IpfmBzEzOBLD2YLiiGApOEqY/k+P3xku9iYsLgW3+Ujn4npketCraH4uOca56e6Qq O/eQNzptdWjYkUSNyeliePsLhFdoAgRVpf3jqGV+R+0aw== X-Received: by 127.0.0.2 with SMTP id C3l4YY7687511xc8tHcRZv7f; Tue, 28 May 2024 03:31:56 -0700 X-Received: from muminek.juszkiewicz.com.pl (muminek.juszkiewicz.com.pl [213.251.184.221]) by mx.groups.io with SMTP id smtpd.web10.18795.1716892315268477200 for ; Tue, 28 May 2024 03:31:55 -0700 X-Received: from localhost (localhost [127.0.0.1]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTP id DED6726124D; Tue, 28 May 2024 12:31:52 +0200 (CEST) X-Virus-Scanned: Debian amavis at juszkiewicz.com.pl X-Received: from muminek.juszkiewicz.com.pl ([127.0.0.1]) by localhost (muminek.juszkiewicz.com.pl [127.0.0.1]) (amavis, port 10024) with ESMTP id ZHKK2eDo4UiJ; Tue, 28 May 2024 12:31:50 +0200 (CEST) X-Received: from applejack.lan (83.11.37.15.ipv4.supernova.orange.pl [83.11.37.15]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTPSA id BB6582600D1; Tue, 28 May 2024 12:31:49 +0200 (CEST) From: "Marcin Juszkiewicz" Subject: [edk2-devel] [PATCH edk2-platforms v2 0/3] SbsaQemu: support multiple PCI Express buses Date: Tue, 28 May 2024 12:31:37 +0200 Message-Id: <20240528-review-multiple-pcie-0425-v2-0-e2ec9f098a78@linaro.org> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAImyVWYC/42Nyw6CMBBFf8V07Zi2PHXlfxgWTTsDkyAlLaKG8 O8WVi5Znntnzl1ExMAYxe20iIAzR/ZDAn0+CduZoUVgl1hoqXOZ6wK2I3zD89VPPPYIo2WEvSl yi1mtKnIZifQ/BiT+7O5Hk7jjOPnw3admtaVHrLMCCdLYyhkiUzp973kwwV98aLeVo4qyJkeuq hVd8V/RrOv6AxWn1FkGAQAA To: devel@edk2.groups.io Cc: Leif Lindholm , Ard Biesheuvel , Graeme Gregory , Ray Ni , Marcin Juszkiewicz Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Tue, 28 May 2024 03:31:55 -0700 Resent-From: marcin.juszkiewicz@linaro.org Reply-To: devel@edk2.groups.io,marcin.juszkiewicz@linaro.org List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: T2mGPEWJ7WpiWRl76oaLYqY0x7686176AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=ze4fRM6T; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=linaro.org (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io QEMU allows to have NUMA setup where each node has own cpus, memory and i/o. We already handle cpus and memory. This patchset adds support for having multiple PCI Express buses. SbsaQemu assumed that there is only bus 0. First patch does PCIe bus scan to find all host bridges (bus 0 one and additional 'pxb-pcie' ones). Second patch moves description of PCIe from DSDT to SSDT (one per each PCIe bus). So Operating System will know about all of them. Third patch moves generation of MCFG table to C. It is preparation to move PCIe Pcds from being fixed to dynamic ones. There are some booting issues with assigning resources for cards: pci 0000:00:03.0: BAR 15: no space for [mem size 0x00200000 64bit pref] pci 0000:00:03.0: BAR 15: failed to assign [mem size 0x00200000 64bit pref] pci 0000:00:01.0: BAR 6: no space for [mem size 0x00040000 pref] pci 0000:00:01.0: BAR 6: failed to assign [mem size 0x00040000 pref] pci 0000:00:03.0: BAR 13: no space for [io size 0x1000] pci 0000:00:03.0: BAR 13: failed to assign [io size 0x1000] Boot log (Linux + lspci + ACPI tables dump): https://people.linaro.org/~marcin.juszkiewicz/sbsa-ref/boot-linux-with-numa= -multiple-pcie-buses.txt I am wondering where I made mistakes in handling PCIe buses. Thanks go to Leif for pointing me to use of Aml to generate SSDT tables. Cc: Leif Lindholm Cc: Ard Biesheuvel Cc: Graeme Gregory Cc: Ray Ni To: devel@edk2.groups.io Signed-off-by: Marcin Juszkiewicz --- Changes in v2: - Dropped [WIP] status - Link to v1: https://openfw.io/edk2-devel/20240425-review-multiple-pcie-04= 25-v1-0-68fdfd781f9e@linaro.org/ --- Marcin Juszkiewicz (3): SbsaQemu: scan for PCIe buses SbsaQemu: describe PCIe buses in SSDT tables SbsaQemu: generate MCFG table Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 2 + Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 - .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 37 +- .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiPcie.h | 23 + .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 170 +++++- .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiPcie.c | 576 ++++++++++++++++= ++++ .../SbsaQemuPciHostBridgeLib.c | 185 ++++--- Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 302 ---------- Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 43 -- .../Drivers/SbsaQemuAcpiDxe/SsdtTemplate.asl | 82 +++ 10 files changed, 982 insertions(+), 439 deletions(-) --- base-commit: 4bbd0ed440322e49edffdebe15e12aa76916d1b0 change-id: 20240425-review-multiple-pcie-0425-54ce3817fd3f Best regards, --=20 Marcin Juszkiewicz -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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