From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id B31AFAC0EF9 for ; Tue, 28 May 2024 10:31:58 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=lde5iVRcrJGtyR//nTvhnH04KSsLGX8qfj+qohTCbIU=; c=relaxed/simple; d=groups.io; h=From:Date:Subject:MIME-Version:Message-Id:References:In-Reply-To:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20240206; t=1716892318; v=1; b=v2+UD0Hsvi6otmyx3/SXys9yrziAGw9oH+ZClzbska5uBf0A2MgIFvlksJtpN1xwe4gx7Kd4 VnVlvYTt9SCrH0SCjjjnIZeKYuPxYdCmDrEc5co2oK05D/U59Siad0WMRkAG+DdIstDZ+JwAJdx eW0QwKKerzqGn4bhd2eAXO8w/AZYLAqXZzRKvTeit7YmiS2EXIilsC7SSv1FOVFon4dBtUoY9Ax HWZfrGKiesBWEZMmY1567PO6jgkTxFCMqTmDJc1N/TlZYUgvAk1ouo6j+KSAE9DUGu4qebJAgSU irTp7dNdhRnXpCXUa+I6VNlEmkOWNQ2ITPpcnVfR8GyyQ== X-Received: by 127.0.0.2 with SMTP id uEnYYY7687511xbH8fyD4c5V; Tue, 28 May 2024 03:31:57 -0700 X-Received: from muminek.juszkiewicz.com.pl (muminek.juszkiewicz.com.pl [213.251.184.221]) by mx.groups.io with SMTP id smtpd.web11.19089.1716892316135401417 for ; Tue, 28 May 2024 03:31:56 -0700 X-Received: from localhost (localhost [127.0.0.1]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTP id B30C12600D1; Tue, 28 May 2024 12:31:53 +0200 (CEST) X-Virus-Scanned: Debian amavis at juszkiewicz.com.pl X-Received: from muminek.juszkiewicz.com.pl ([127.0.0.1]) by localhost (muminek.juszkiewicz.com.pl [127.0.0.1]) (amavis, port 10024) with ESMTP id UIpjyXt2TEwV; Tue, 28 May 2024 12:31:50 +0200 (CEST) X-Received: from applejack.lan (83.11.37.15.ipv4.supernova.orange.pl [83.11.37.15]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTPSA id 79BA926074C; Tue, 28 May 2024 12:31:50 +0200 (CEST) From: "Marcin Juszkiewicz" Date: Tue, 28 May 2024 12:31:38 +0200 Subject: [edk2-devel] [PATCH edk2-platforms v2 1/3] SbsaQemu: scan for PCIe buses MIME-Version: 1.0 Message-Id: <20240528-review-multiple-pcie-0425-v2-1-e2ec9f098a78@linaro.org> References: <20240528-review-multiple-pcie-0425-v2-0-e2ec9f098a78@linaro.org> In-Reply-To: <20240528-review-multiple-pcie-0425-v2-0-e2ec9f098a78@linaro.org> To: devel@edk2.groups.io Cc: Leif Lindholm , Ard Biesheuvel , Graeme Gregory , Ray Ni , Marcin Juszkiewicz Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Tue, 28 May 2024 03:31:56 -0700 Resent-From: marcin.juszkiewicz@linaro.org Reply-To: devel@edk2.groups.io,marcin.juszkiewicz@linaro.org List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: UxpoGe0kvzs5H8WNT0deVrsCx7686176AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=v2+UD0Hs; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=linaro.org (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io SbsaQemu assumes that there is only one PCI Express bus. But there can be multiple PCIe buses as NUMA systems can get 'pxb-pcie' HostBridge devices added. Let scan for all PCIe buses and report them back so EDK2 will be able to find all expansions. Signed-off-by: Marcin Juszkiewicz --- .../SbsaQemuPciHostBridgeLib.c | 185 ++++++++++++----= ---- 1 file changed, 109 insertions(+), 76 deletions(-) diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQem= uPciHostBridgeLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLi= b/SbsaQemuPciHostBridgeLib.c index 9739c7500def..1c4ed1c74e52 100644 --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHos= tBridgeLib.c +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHos= tBridgeLib.c @@ -6,10 +6,14 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ +#include +#include +#include #include #include #include #include +#include #include =20 #include @@ -52,76 +56,49 @@ CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] =3D = { L"Mem", L"I/O", L"Bus" }; =20 -STATIC PCI_ROOT_BRIDGE mRootBridge =3D { - /* UINT32 Segment; Segment number */ - 0, - - /* UINT64 Supports; Supported attributes */ - EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | - EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16, - - /* UINT64 Attributes; Initial attributes */ - EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | - EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16, - - /* BOOLEAN DmaAbove4G; DMA above 4GB memory */ - TRUE, - - /* BOOLEAN NoExtendedConfigSpace; When FALSE, the root bridge supports - Extended (4096-byte) Configuration Space. When TRUE, the root bridge - supports 256-byte Configuration Space only. */ - FALSE, - - /* BOOLEAN ResourceAssigned; Resource assignment status of the root brid= ge. - Set to TRUE if Bus/IO/MMIO resources for root bridge have been assign= ed */ - FALSE, - - /* UINT64 AllocationAttributes; Allocation attributes. */ - EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, /* as Mmio64Size > 0 */ - - { - /* PCI_ROOT_BRIDGE_APERTURE Bus; Bus aperture which can be used by th= e - * root bridge. */ - FixedPcdGet32 (PcdPciBusMin), - FixedPcdGet32 (PcdPciBusMax) - }, - - /* PCI_ROOT_BRIDGE_APERTURE Io; IO aperture which can be used by the roo= t - bridge */ - { - FixedPcdGet64 (PcdPciIoBase), - FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1 - }, - - /* PCI_ROOT_BRIDGE_APERTURE Mem; MMIO aperture below 4GB which can be us= ed by - the root bridge - (gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation as 0x0) */ - { - FixedPcdGet32 (PcdPciMmio32Base), - FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - = 1, - }, - - /* PCI_ROOT_BRIDGE_APERTURE MemAbove4G; MMIO aperture above 4GB which ca= n be - used by the root bridge. - (gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation as 0x0) */ - { - FixedPcdGet64 (PcdPciMmio64Base), - FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - = 1 - }, - - /* PCI_ROOT_BRIDGE_APERTURE PMem; Prefetchable MMIO aperture below 4GB w= hich - can be used by the root bridge. - In our case, there are no separate ranges for prefetchable and - non-prefetchable BARs */ - { MAX_UINT64, 0 }, - - /* PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; Prefetchable MMIO aperture abov= e 4GB - which can be used by the root bridge. */ - { MAX_UINT64, 0 }, - /* EFI_DEVICE_PATH_PROTOCOL *DevicePath; Device path. */ - (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath, -}; +EFI_STATUS +EFIAPI +PciHostBridgeUtilityInitRootBridge ( + IN UINTN RootBusNumber, + OUT PCI_ROOT_BRIDGE *RootBus + ) +{ + EFI_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath; + UINTN MaxSubBusNumber =3D 255; + + DevicePath =3D AllocateCopyPool ( + sizeof mEfiPciRootBridgeDevicePath, + &mEfiPciRootBridgeDevicePath + ); + if (DevicePath =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: %r\n", __func__, EFI_OUT_OF_RESOURCES)); + return EFI_OUT_OF_RESOURCES; + } + + DevicePath->AcpiDevicePath.UID =3D RootBusNumber; + + RootBus->Segment =3D 0; + RootBus->Supports =3D 0; + RootBus->Attributes =3D 0; + RootBus->DmaAbove4G =3D TRUE; + RootBus->AllocationAttributes =3D EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM = | EFI_PCI_HOST_BRIDGE_MEM64_DECODE, /* as Mmio64Size > 0 */ + RootBus->Bus.Base =3D RootBusNumber; + RootBus->Bus.Limit =3D MaxSubBusNumber; + RootBus->Io.Base =3D PcdGet64 (PcdPciIoBase); + RootBus->Io.Limit =3D PcdGet64 (PcdPciIoBase) + PcdGet64 (P= cdPciIoSize) - 1; + RootBus->Mem.Base =3D PcdGet32 (PcdPciMmio32Base); + RootBus->Mem.Limit =3D PcdGet32 (PcdPciMmio32Base) + PcdGet3= 2 (PcdPciMmio32Size) - 1; + RootBus->MemAbove4G.Base =3D PcdGet64 (PcdPciMmio64Base); + RootBus->MemAbove4G.Limit =3D PcdGet64 (PcdPciMmio64Base) + PcdGet6= 4 (PcdPciMmio64Size) - 1; + RootBus->PMem.Base =3D MAX_UINT64; + RootBus->PMem.Limit =3D 0; + RootBus->PMemAbove4G.Base =3D MAX_UINT64; + RootBus->PMemAbove4G.Limit =3D 0; + RootBus->NoExtendedConfigSpace =3D FALSE; + RootBus->DevicePath =3D (EFI_DEVICE_PATH_PROTOCOL *)DevicePat= h; + + return EFI_SUCCESS; +} =20 /** Return all the root bridge instances in an array. @@ -135,11 +112,67 @@ STATIC PCI_ROOT_BRIDGE mRootBridge =3D { PCI_ROOT_BRIDGE * EFIAPI PciHostBridgeGetRootBridges ( - UINTN *Count + UINTN *Count ) { - *Count =3D 1; - return &mRootBridge; + PCI_ROOT_BRIDGE *Bridges; + int BusId, BusMin =3D 0, BusMax =3D 255, Index =3D 0; + int AvailableBusses[255] =3D { INT_MAX }; // INT_MAX as "th= ere is no bus" + + *Count =3D 0; + + // + // Scan all root buses. If function 0 of any device on a bus returns a + // VendorId register value different from all-bits-one, then that bus is + // alive. + // + for (BusId =3D BusMin; BusId <=3D BusMax; ++BusId) { + UINTN Device; + + for (Device =3D 0; Device <=3D PCI_MAX_DEVICE; ++Device) { + if (PciRead16 ( + PCI_LIB_ADDRESS ( + BusId, + Device, + 0, + PCI_VENDOR_ID_OFFSET + ) + ) !=3D MAX_UINT16) + { + break; + } + } + + if (Device <=3D PCI_MAX_DEVICE) { + DEBUG ((DEBUG_ERROR, "%a: found bus: 0x%02x\n", __func__, BusId)); + AvailableBusses[Index++] =3D BusId; + *Count +=3D 1; + } + } + + // + // Allocate the "main" root bridge, and any extra root bridges. + // + Bridges =3D AllocateZeroPool (*Count * sizeof *Bridges); + if (Bridges =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: %r\n", __func__, EFI_OUT_OF_RESOURCES)); + return NULL; + } + + for (Index =3D 0; Index < *Count; Index++) { + if (AvailableBusses[Index] =3D=3D INT_MAX) { + break; + } + + PciHostBridgeUtilityInitRootBridge (AvailableBusses[Index], &Bridges[I= ndex]); + + // limit previous RootBridge bus range + if (Index > 0) { + Bridges[Index - 1].Bus.Limit =3D AvailableBusses[Index] - 1; + } + } + + return Bridges; } =20 /** @@ -152,11 +185,11 @@ PciHostBridgeGetRootBridges ( VOID EFIAPI PciHostBridgeFreeRootBridges ( - PCI_ROOT_BRIDGE *Bridges, - UINTN Count + PCI_ROOT_BRIDGE *Bridges, + UINTN Count ) { - ASSERT (Count =3D=3D 1); + FreePool (Bridges); } =20 /** --=20 2.45.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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