From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id CDE66740034 for ; Wed, 29 May 2024 08:55:57 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=qOE2hn9815JVVWUhrv7hmIhHtVMOqzyBKQIzDZVySeM=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20240206; t=1716972957; v=1; b=XbUmh/X21q72IjY9VE192i8UqWs1zbo75GwzcTP13cpVrwNuEo8DU7iwHrjKA4Wxq33R/AX/ sMO2nPzyK4mjYat7aCxIgkTJIZrTQ5OkmY1ovcHrTHAW9/yQMtQ0xYfjP+0gobtYxTaskrIOvuo hc99t9hbaJRvm9/y/+NLwt11ciN2Op/QQaCNBExPbkTRcpnfwjNysk4Dp7kXrKL6KGkRsw40dL7 27zOzfJqOI2eFUtF+Ab2YwZyBEebKjal8ff1L0q2nkouhWYe9Pnw/cv4P4SGnC1medp1OiEBvYu 5BTsJGsTXAUvcNhXDoXZHvlWc4n81s3afazrzMszOmxLQ== X-Received: by 127.0.0.2 with SMTP id 6wTvYY7687511xLLFAKwKX34; Wed, 29 May 2024 01:55:56 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.9256.1716972955669741107 for ; Wed, 29 May 2024 01:55:55 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 992261596; Wed, 29 May 2024 01:56:19 -0700 (PDT) X-Received: from usa.arm.com (a077434.arm.com [10.162.46.143]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B52C33F762; Wed, 29 May 2024 01:55:53 -0700 (PDT) From: "Sahil Kaushal" To: devel@edk2.groups.io Cc: Ard Biesheuvel , =?UTF-8?q?Leif=20Lindholm=20=C2=A0?= , Sami Mujawar , =?UTF-8?q?sahil=20=C2=A0?= Subject: [edk2-devel] [edk2-platforms][PATCH V4 13/17] Silicon/ARM/NeoverseN1Soc: Enable SCP QSPI flash region Date: Wed, 29 May 2024 14:25:13 +0530 Message-Id: <20240529085517.1074417-14-Sahil.Kaushal@arm.com> In-Reply-To: <20240529085517.1074417-1-Sahil.Kaushal@arm.com> References: <20240529085517.1074417-1-Sahil.Kaushal@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Wed, 29 May 2024 01:55:55 -0700 Resent-From: sahil.kaushal@arm.com Reply-To: devel@edk2.groups.io,sahil.kaushal@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: rELCZHHAkpKlFvi5m9Q6iRLhx7686176AA= Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b="XbUmh/X2"; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=arm.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io From: sahil Enable SCP QSPI flash region access by adding it in the PlatformLibMem. This flash is shared between AP core and System Control Processor. The lower addresses are used to store SCP and AP boot images and higher addresses will be used for variable storage. Signed-off-by: sahil --- Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 7 +++++= ++ Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 8 +++++= ++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/= ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h index 5483e7bc5f68..2dae57a0f01a 100644 --- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h +++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h @@ -4,6 +4,9 @@ * * SPDX-License-Identifier: BSD-2-Clause-Patent * +* Arm Neoverse N1 System Development Platform Technical Reference Manual +* https://developer.arm.com/documentation/101489/0000/?lang=3Den +* **/ =20 #ifndef NEOVERSEN1SOC_PLATFORM_H_ @@ -41,6 +44,10 @@ #define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000 #define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000 =20 +// SCP QSPI flash device +#define NEOVERSEN1SOC_SCP_QSPI_AHB_BASE 0x18000000 +#define NEOVERSEN1SOC_SCP_QSPI_AHB_SZ 0x2000000 + /* * Platform information structure stored in Non-secure SRAM. Platform * information are passed from the trusted firmware with the below struc= ture diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem= .c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c index 80daedb33416..282bfbc81736 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c @@ -14,7 +14,7 @@ #include =20 // The total number of descriptors, including the final "end-of-table" d= escriptor. -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19 +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 20 =20 /** Returns the Virtual Memory Map of the platform. @@ -203,6 +203,12 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length =3D NEOVERSEN1SOC_EXP_PERIPH= _BASE0_SZ; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; =20 + // SCP QSPI flash device + VirtualMemoryTable[++Index].PhysicalBase =3D NEOVERSEN1SOC_SCP_QSPI_A= HB_BASE; + VirtualMemoryTable[Index].VirtualBase =3D NEOVERSEN1SOC_SCP_QSPI_A= HB_BASE; + VirtualMemoryTable[Index].Length =3D NEOVERSEN1SOC_SCP_QSPI_A= HB_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; + if (PlatInfo->MultichipMode =3D=3D 1) { //Remote DDR (2GB) VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdExtMemory= Space) + --=20 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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