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From: "Rebecca Cran" <rebecca@bsdio.com>
To: devel@edk2.groups.io, nhi@os.amperecomputing.com
Cc: Rebecca Cran <rebecca@bsdio.com>,
	Chuong Tran <chuong@os.amperecomputing.com>,
	Leif Lindholm <quic_llindhol@quicinc.com>
Subject: [edk2-devel] [PATCH edk2-platforms 2/6] Silicon/Ampere: Reduce DEBUG_INFO spam in PciSegmentLibPci
Date: Wed,  5 Jun 2024 21:04:35 -0600	[thread overview]
Message-ID: <20240606030439.46610-3-rebecca@bsdio.com> (raw)
In-Reply-To: <20240606030439.46610-1-rebecca@bsdio.com>

Reduce the spam when DEBUG_INFO is enabled by switching DEBUG prints in
PciSegmentLibPci from DEBUG_INFO to DEBUG_VERBOSE.

Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
---
 Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLib.c | 24 ++++++++++----------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLib.c
index 898558db8d3b..483da44d131c 100644
--- a/Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLib.c
+++ b/Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLib.c
@@ -143,7 +143,7 @@ PciSegmentRead8 (
   Value = WORD_GET_BYTE (Val32, CfgBase & WORD_ALIGN_MASK);
 
   DEBUG ((
-    DEBUG_INFO,
+    DEBUG_VERBOSE,
     "PCIe CFG RD8: 0x%p value: 0x%02X (0x%08llX 0x%08X)\n",
     CfgBase,
     Value,
@@ -190,7 +190,7 @@ PciSegmentWrite8 (
   MmioWrite32 (AlignedAddr, Val32);
 
   DEBUG ((
-    DEBUG_INFO,
+    DEBUG_VERBOSE,
     "PCIe CFG WR8: 0x%p value: 0x%02X (0x%08llX 0x%08X)\n",
     CfgBase,
     Value,
@@ -522,7 +522,7 @@ PciSegmentRead16 (
   if ((GET_BUS_NUM (CfgBase) > 0) && (GET_DEV_NUM (CfgBase) > 0) && (GET_REG_NUM (CfgBase) == 0)) {
     Value = MmioRead32 (CfgBase);
     DEBUG ((
-      DEBUG_INFO,
+      DEBUG_VERBOSE,
       "PCIe CFG RD16: B%X|D%X 0x%p value: 0x%08X\n",
       GET_BUS_NUM (CfgBase),
       GET_DEV_NUM (CfgBase),
@@ -534,7 +534,7 @@ PciSegmentRead16 (
       Val32 = MmioRead32 (CfgBase + HEADER_TYPE_REG);
 
       HeaderType = GET_HEADER_TYPE (Val32);
-      DEBUG ((DEBUG_INFO, "  Peek RD: HeaderType=0x%02X\n", HeaderType));
+      DEBUG ((DEBUG_VERBOSE, "  Peek RD: HeaderType=0x%02X\n", HeaderType));
 
       // Type 1 Configuration Space Header
       if (HeaderType != 0) {
@@ -545,7 +545,7 @@ PciSegmentRead16 (
       if ((HeaderType == 0) || (PrimaryBus != 0)) {
         Value = 0xFFFF;
         DEBUG ((
-          DEBUG_INFO,
+          DEBUG_VERBOSE,
           "  Skip RD16 B%X|D%X PCIe CFG RD: 0x%p return 0xFFFF\n",
           GET_BUS_NUM (CfgBase),
           GET_DEV_NUM (CfgBase),
@@ -560,7 +560,7 @@ PciSegmentRead16 (
   Value = WORD_GET_HALF_WORD (Val32, CfgBase & WORD_ALIGN_MASK);
 
   DEBUG ((
-    DEBUG_INFO,
+    DEBUG_VERBOSE,
     "PCIe CFG RD16: 0x%p value: 0x%04X (0x%08llX 0x%08X)\n",
     CfgBase,
     Value,
@@ -614,7 +614,7 @@ PciSegmentWrite16 (
   MmioWrite32 (AlignedAddr, Val32);
 
   DEBUG ((
-    DEBUG_INFO,
+    DEBUG_VERBOSE,
     "PCIe CFG WR16: 0x%p value: 0x%04X (0x%08llX 0x%08X)\n",
     CfgBase,
     Value,
@@ -955,7 +955,7 @@ PciSegmentRead32 (
   if ((GET_BUS_NUM (CfgBase) > 0) && (GET_DEV_NUM (CfgBase) > 0) && (GET_REG_NUM (CfgBase) == 0)) {
     Value = MmioRead32 (CfgBase);
     DEBUG ((
-      DEBUG_INFO,
+      DEBUG_VERBOSE,
       "PCIe CFG RD32: B%X|D%X 0x%p value: 0x%08X\n",
       GET_BUS_NUM (CfgBase),
       GET_DEV_NUM (CfgBase),
@@ -967,7 +967,7 @@ PciSegmentRead32 (
       Val32 = MmioRead32 (CfgBase + HEADER_TYPE_REG);
 
       HeaderType = GET_HEADER_TYPE (Val32);
-      DEBUG ((DEBUG_INFO, "  Peek RD: HeaderType=0x%02X\n", HeaderType));
+      DEBUG ((DEBUG_VERBOSE, "  Peek RD: HeaderType=0x%02X\n", HeaderType));
 
       // Type 1 Configuration Space Header
       if (HeaderType != 0) {
@@ -978,7 +978,7 @@ PciSegmentRead32 (
       if ((HeaderType == 0) || (PrimaryBus != 0)) {
         Value = 0xFFFFFFFF;
         DEBUG ((
-          DEBUG_INFO,
+          DEBUG_VERBOSE,
           "  Skip RD32 B%X|D%X PCIe CFG RD: 0x%p return 0xFFFFFFFF\n",
           GET_BUS_NUM (CfgBase),
           GET_DEV_NUM (CfgBase),
@@ -991,7 +991,7 @@ PciSegmentRead32 (
     Value = MmioRead32 (CfgBase);
   }
 
-  DEBUG ((DEBUG_INFO, "PCIe CFG RD32: 0x%p value: 0x%08X\n", CfgBase, Value));
+  DEBUG ((DEBUG_VERBOSE, "PCIe CFG RD32: 0x%p value: 0x%08X\n", CfgBase, Value));
 
   return Value;
 }
@@ -1025,7 +1025,7 @@ PciSegmentWrite32 (
   CfgBase = GetMmcfgBase (GET_SEG_NUM (Address)) + (Address & 0x0FFFFFFC);
   MmioWrite32 (CfgBase, Value);
   DEBUG ((
-    DEBUG_INFO,
+    DEBUG_VERBOSE,
     "PCIe CFG WR32: 0x%p value: 0x%08X (0x%08X)\n",
     CfgBase,
     Value,
-- 
2.45.1



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  parent reply	other threads:[~2024-06-06  3:04 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-06  3:04 [edk2-devel] [PATCH edk2-platforms 0/6] JadePkg and common Ampere code fixes Rebecca Cran
2024-06-06  3:04 ` [edk2-devel] [PATCH edk2-platforms 1/6] Silicon/Ampere: Fix capitalization of Cache strings in PlatformInfoDxe Rebecca Cran
2024-06-06  3:04 ` Rebecca Cran [this message]
2024-06-06  3:04 ` [edk2-devel] [PATCH edk2-platforms 3/6] Silicon/Ampere: Add TimerLib to DwGpioLib.inf for MicroSecondDelay Rebecca Cran
2024-06-06  3:04 ` [edk2-devel] [PATCH edk2-platforms 4/6] Platform/Ampere: Don't try and close the ACPI table if OpenSdt fails Rebecca Cran
2024-06-06  3:04 ` [edk2-devel] [PATCH edk2-platforms 5/6] Silicon/Ampere: Set default SMBIOS fw major/minor version to 0xFF Rebecca Cran
2024-06-06  3:04 ` [edk2-devel] [PATCH edk2-platforms 6/6] Silicon/Ampere: Remove bogus ASSERT that *PpiList is non-NULL Rebecca Cran
2024-06-07  4:49 ` [edk2-devel] [PATCH edk2-platforms 0/6] JadePkg and common Ampere code fixes Nhi Pham via groups.io
2024-07-31  8:00   ` Nhi Pham via groups.io

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