From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id CFD64D80CF6 for ; Tue, 2 Jul 2024 16:33:29 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=F/mCQ7p/Wz7VDVhD8Jjd0q8PAMmUZaFLfTFJVnDit3s=; c=relaxed/simple; d=groups.io; h=From:Date:Subject:MIME-Version:Message-Id:References:In-Reply-To:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20240206; t=1719938009; v=1; b=XCClhmEkor5LlNdTac2HJE3QMTBILujecz9NbBr6cCWnkyybi+ECdutzigh450LJWSwp01x7 +ssS/NGVvOIMgvv8hVdLFGhDmQvre3gWIbEF5wLNzAaTu52PMV+2G8gIk7YUS4QI3QukEkSUNTE RvbcfXOt3KIAnFATVnKL/Unv9vn+KrREH3bdIxKDfDha7M33aSc47cAVe+IxOCMQ9BEXlkivkXt pbdHGV9Dv3NvWdyEtdwybKmJKOkdljx1DyN2mi4KmfJRYKaBT7tb2Dl5S2686CLVid+NwHWCxYs ZTbaRJS+a2H1Ke7AWs8hnBDxhG0bqQhcm7YNBETY/fxCQ== X-Received: by 127.0.0.2 with SMTP id fDDSYY7687511x8jf4ai48vM; Tue, 02 Jul 2024 09:33:28 -0700 X-Received: from muminek.juszkiewicz.com.pl (muminek.juszkiewicz.com.pl [213.251.184.221]) by mx.groups.io with SMTP id smtpd.web11.29548.1719938007247111813 for ; Tue, 02 Jul 2024 09:33:27 -0700 X-Received: from localhost (localhost [127.0.0.1]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTP id 5BA712602ED; Tue, 2 Jul 2024 18:33:24 +0200 (CEST) X-Virus-Scanned: Debian amavis at juszkiewicz.com.pl X-Received: from muminek.juszkiewicz.com.pl ([127.0.0.1]) by localhost (muminek.juszkiewicz.com.pl [127.0.0.1]) (amavis, port 10024) with ESMTP id xF7eyrM_RcF8; Tue, 2 Jul 2024 18:33:22 +0200 (CEST) X-Received: from applejack.lan (83.8.74.165.ipv4.supernova.orange.pl [83.8.74.165]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTPSA id D0B29260988; Tue, 2 Jul 2024 18:33:19 +0200 (CEST) From: "Marcin Juszkiewicz" Date: Tue, 02 Jul 2024 18:33:03 +0200 Subject: [edk2-devel] [PATCH edk2-platforms v2 2/3] Silicon/SbsaQemu: align the PPTT tables with QEMU MIME-Version: 1.0 Message-Id: <20240702-acpi65-v2-2-3cb18a892221@linaro.org> References: <20240702-acpi65-v2-0-3cb18a892221@linaro.org> In-Reply-To: <20240702-acpi65-v2-0-3cb18a892221@linaro.org> To: devel@edk2.groups.io Cc: Leif Lindholm , Ard Biesheuvel , Graeme Gregory , Chen Baozi , Xiong Yining , Marcin Juszkiewicz Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Tue, 02 Jul 2024 09:33:27 -0700 Resent-From: marcin.juszkiewicz@linaro.org Reply-To: devel@edk2.groups.io,marcin.juszkiewicz@linaro.org List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: xXWhFbCyQmASsGMDyJwzEDrtx7686176AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=XCClhmEk; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=linaro.org (policy=none) From: Xiong Yining To align the CPU topology information recognized by the operating system with the CPU topology information configured by QEMU, we need to make use of the CPU topology information to create complex PPTT tables setups. We get the CPU topology information via SMC. Signed-off-by: Xiong Yining Signed-off-by: Marcin Juszkiewicz --- .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 17 +- .../Include/IndustryStandard/SbsaQemuAcpi.h | 78 +++----- .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 190 +++++++++++++++-= ---- 3 files changed, 180 insertions(+), 105 deletions(-) diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= h b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h index e5f0748bb16e..5e50749051c9 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h @@ -61,8 +61,7 @@ typedef struct { =20 #define GTDT_WDTIMER_FLAGS (GTDT_WDTIMER_ACTIVE_HIGH | GTDT_WDTIMER_LEVEL= _TRIGGERED) =20 -#define SBSAQEMU_ACPI_MEMORY_AFFINITY_STRUCTURE_INIT( = \ - = ProximityDomain, Base, Length, Flags) = \ +#define SBSAQEMU_ACPI_MEMORY_AFFINITY_STRUCTURE_INIT(ProximityDomain, Base= , Length, Flags) \ { = \ 1, /* Type */ = \ sizeof (EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE), /* Length */ = \ @@ -77,8 +76,7 @@ typedef struct { 0 /* Reserved */ = \ } =20 -#define SBSAQEMU_ACPI_GICC_AFFINITY_STRUCTURE_INIT( = \ - = ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) = \ +#define SBSAQEMU_ACPI_GICC_AFFINITY_STRUCTURE_INIT(ProximityDomain, ACPIPr= ocessorUID, Flags, ClockDomain) \ { = \ 3, /* Type */ = \ sizeof (EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE), /* Length */ = \ @@ -88,4 +86,15 @@ typedef struct { ClockDomain /* Clock Domain */= \ } =20 +#define SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT(Flags, Paren= t, ACPIProcessorID, NumberOfPrivateResources) \ + { = \ + EFI_ACPI_6_5_PPTT_TYPE_PROCESSOR, = /* Type */ \ + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResour= ces * sizeof (UINT32), /* Length */ \ + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, = /* Reserved */ \ + Flags, = /* Flags */ \ + Parent, = /* Parent */ \ + ACPIProcessorID, = /* ACPI Processor ID */ \ + NumberOfPrivateResources = /* Number of private resources */ \ + } + #endif diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h = b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h index ae151210c2c6..fa2e2b30bb7d 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h @@ -87,13 +87,13 @@ typedef struct { #define SBSAQEMU_L2_CACHE_ASSC 8 =20 #define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER)) -#define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUC= TURE_PROCESSOR)) -#define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_ST= RUCTURE_CACHE)) -#define L2_CACHE_INDEX (L1_I_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_ST= RUCTURE_CACHE)) +#define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_5_PPTT_STRUC= TURE_PROCESSOR)) +#define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_5_PPTT_ST= RUCTURE_CACHE)) +#define L2_CACHE_INDEX (L1_I_CACHE_INDEX + sizeof (EFI_ACPI_6_5_PPTT_ST= RUCTURE_CACHE)) =20 #define SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT { = \ - EFI_ACPI_6_3_PPTT_TYPE_CACHE, = \ - sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), = \ + EFI_ACPI_6_5_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE), = \ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, = \ { = \ 1, /* SizePropertyValid */ = \ @@ -103,22 +103,24 @@ typedef struct { 1, /* CacheTypeValid */ = \ 1, /* WritePolicyValid */ = \ 1, /* LineSizeValid */ = \ + 1, /* CacheIdValid */ = \ }, = \ 0, /* NextLevelOfCache */ = \ SBSAQEMU_L1_D_CACHE_SIZE, /* Size */ = \ SBSAQEMU_L1_D_CACHE_SETS, /* NumberOfSets */ = \ SBSAQEMU_L1_D_CACHE_ASSC, /* Associativity */ = \ { = \ - EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ - EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, = \ - EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ + EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, = \ + EFI_ACPI_6_5_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ }, = \ - 64 /* LineSize */ = \ + 64, /* LineSize */ = \ + 0 /* CacheId */ = \ } =20 #define SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT { = \ - EFI_ACPI_6_3_PPTT_TYPE_CACHE, = \ - sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), = \ + EFI_ACPI_6_5_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE), = \ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, = \ { = \ 1, /* SizePropertyValid */ = \ @@ -128,22 +130,24 @@ typedef struct { 1, /* CacheTypeValid */ = \ 1, /* WritePolicyValid */ = \ 1, /* LineSizeValid */ = \ + 1, /* CacheIdValid */ = \ }, = \ 0, /* NextLevelOfCache */ = \ SBSAQEMU_L1_I_CACHE_SIZE, /* Size */ = \ SBSAQEMU_L1_I_CACHE_SETS, /* NumberOfSets */ = \ SBSAQEMU_L1_I_CACHE_ASSC, /* Associativity */ = \ { = \ - EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, = \ - EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, = \ + EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ, = \ + EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, = \ 0, = \ }, = \ - 64 /* LineSize */ = \ + 64, /* LineSize */ = \ + 0 /* CacheId */ = \ } =20 #define SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT { = \ - EFI_ACPI_6_3_PPTT_TYPE_CACHE, = \ - sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), = \ + EFI_ACPI_6_5_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE), = \ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, = \ { = \ 1, /* SizePropertyValid */ = \ @@ -153,49 +157,19 @@ typedef struct { 1, /* CacheTypeValid */ = \ 1, /* WritePolicyValid */ = \ 1, /* LineSizeValid */ = \ + 1, /* CacheIdValid */ = \ }, = \ 0, /* NextLevelOfCache */ = \ SBSAQEMU_L2_CACHE_SIZE, /* Size */ = \ SBSAQEMU_L2_CACHE_SETS, /* NumberOfSets */ = \ SBSAQEMU_L2_CACHE_ASSC, /* Associativity */ = \ { = \ - EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ - EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, = \ - EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ + EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, = \ + EFI_ACPI_6_5_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ }, = \ - 64 /* LineSize */ = \ - } - -#define SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT { = \ - EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, = \ - sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR), = \ - { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, = \ - { = \ - EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, /* PhysicalPackage */ = \ - EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid = */ \ - EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ = \ - EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, /* Not Leaf */ = \ - EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ = \ - }, = \ - 0, /* Parent */ = \ - 0, /* AcpiProcessorId */ = \ - 0, /* NumberOfPrivateResources = */ \ - } - -#define SBSAQEMU_ACPI_PPTT_CORE_STRUCT { = \ - EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, = \ - (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + (2 * sizeof (UINT32)= )), \ - { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, = \ - { = \ - EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, /* PhysicalPackage */ = \ - EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorValid */= \ - EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ = \ - EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, /* Leaf */ = \ - EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ = \ - }, = \ - 0, /* Parent */ = \ - 0, /* AcpiProcessorId */ = \ - 2, /* NumberOfPrivateResources = */ \ + 64, /* LineSize */ = \ + 0 /* CacheId */ = \ } =20 #endif diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index e0eef54ff907..4c275faf7de6 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -505,27 +505,70 @@ AddPpttTable ( EFI_PHYSICAL_ADDRESS PageAddress; UINT8 *New; UINT32 CpuId; - UINT32 NumCores =3D GetCpuCount (); + CpuTopology CpuTopo; + UINT32 CacheId; =20 - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1DCache =3D SBSAQEMU_ACPI_PPTT_L1_D_= CACHE_STRUCT; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1ICache =3D SBSAQEMU_ACPI_PPTT_L1_I_= CACHE_STRUCT; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache =3D SBSAQEMU_ACPI_PPTT_L2_CA= CHE_STRUCT; + GetCpuTopology (&CpuTopo); =20 - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster =3D SBSAQEMU_ACPI_PPTT_CL= USTER_STRUCT; - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core =3D SBSAQEMU_ACPI_PPTT_CO= RE_STRUCT; + EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1DCache =3D SBSAQEMU_ACPI_PPTT_L1_D_= CACHE_STRUCT; + EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1ICache =3D SBSAQEMU_ACPI_PPTT_L1_I_= CACHE_STRUCT; + EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L2Cache =3D SBSAQEMU_ACPI_PPTT_L2_CA= CHE_STRUCT; =20 - EFI_ACPI_DESCRIPTION_HEADER Header =3D - SBSAQEMU_ACPI_HEADER ( - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE= , - EFI_ACPI_DESCRIPTION_HEADER, - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION - ); + EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS SocketFlags =3D { + EFI_ACPI_6_5_PPTT_PACKAGE_PHYSICAL, + EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID, + EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF, + EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL + }; + + EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS ClusterFlags =3D { + EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID, + EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF, + EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL + }; + + EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS CoreFlags =3D { + EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID, + EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_5_PPTT_NODE_IS_LEAF, + EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL + }; + + if (CpuTopo.Threads > 1) { + // The Thread structure is the leaf structure, adjust the value of Cor= eFlags. + CoreFlags.AcpiProcessorIdValid =3D EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVA= LID; + CoreFlags.NodeIsALeaf =3D EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF; + } + + EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS ThreadFlags =3D { + EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID, + EFI_ACPI_6_5_PPTT_PROCESSOR_IS_THREAD, + EFI_ACPI_6_5_PPTT_NODE_IS_LEAF, + EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL + }; + + EFI_ACPI_DESCRIPTION_HEADER Header =3D SBSAQEMU_ACPI_HEADER ( + EFI_ACPI_6_5_PROCESSOR_PROPERTIE= S_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_DESCRIPTION_HEADER, + EFI_ACPI_6_5_PROCESSOR_PROPERTIE= S_TOPOLOGY_TABLE_REVISION + ); =20 TableSize =3D sizeof (EFI_ACPI_DESCRIPTION_HEADER) + - sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + - (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3) + - (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) * NumCores) = + - (sizeof (UINT32) * 2 * NumCores); + CpuTopo.Sockets * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCE= SSOR) + + CpuTopo.Clusters * (sizeof (EFI_ACPI_6_5_= PPTT_STRUCTURE_PROCESSOR) + + sizeof (EFI_ACPI_6_5_= PPTT_STRUCTURE_CACHE) * 3 + + CpuTopo.Cores * (size= of (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + + size= of (UINT32) * 2))); + + if (CpuTopo.Threads > 1) { + TableSize +=3D CpuTopo.Sockets * CpuTopo.Clusters * CpuTopo.Cores * Cp= uTopo.Threads * + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR); + } =20 Status =3D gBS->AllocatePages ( AllocateAnyPages, @@ -546,39 +589,88 @@ AddPpttTable ( ((EFI_ACPI_DESCRIPTION_HEADER *)New)->Length =3D TableSize; New +=3D sizeof (EFI_ACPI_DESCRI= PTION_HEADER); =20 - // Add the Cluster PPTT structure - CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR)); - New +=3D sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR); - - // Add L1 D Cache structure - CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)); - ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache =3D L2_CACH= E_INDEX; - New +=3D sizeof = (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE); - - // Add L1 I Cache structure - CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)); - ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache =3D L2_CACH= E_INDEX; - New +=3D sizeof = (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE); - - // Add L2 Cache structure - CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)); - ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache =3D 0; /* L= 2 is LLC */ - New +=3D sizeof = (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE); - - for (CpuId =3D 0; CpuId < NumCores; CpuId++) { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *CorePtr; - UINT32 *PrivateResourcePtr; - - CopyMem (New, &Core, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR)); - CorePtr =3D (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *)= New; - CorePtr->Parent =3D CLUSTER_INDEX; - CorePtr->AcpiProcessorId =3D CpuId; - New +=3D sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCE= SSOR); - - PrivateResourcePtr =3D (UINT32 *)New; - PrivateResourcePtr[0] =3D L1_D_CACHE_INDEX; - PrivateResourcePtr[1] =3D L1_I_CACHE_INDEX; - New +=3D (2 * sizeof (UINT32)); + UINT32 SocketNum, ClusterNum, CoreNum, ThreadNum; + UINT32 SocketIndex, ClusterIndex, CoreIndex, L1DCacheIndex, L1ICacheInd= ex, L2CacheIndex; + + CpuId =3D 0; + CacheId =3D 1; // 0 is not a valid Cache ID. + SocketIndex =3D sizeof (EFI_ACPI_DESCRIPTION_HEADER); + + for (SocketNum =3D 0; SocketNum < CpuTopo.Sockets; SocketNum++) { + // Add the Socket PPTT structure + EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Socket =3D SBSAQEMU_ACPI_PROCES= SOR_HIERARCHY_NODE_STRUCTURE_INIT (SocketFlags, 0, 0, 0); + CopyMem (New, &Socket, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR))= ; + New +=3D sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR); + + ClusterIndex =3D SocketIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PRO= CESSOR); + for (ClusterNum =3D 0; ClusterNum < CpuTopo.Clusters; ClusterNum++) { + L1DCacheIndex =3D ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE= _PROCESSOR); + L1ICacheIndex =3D L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTUR= E_CACHE); + L2CacheIndex =3D L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTUR= E_CACHE); + CoreIndex =3D L2CacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE= _CACHE); + + // Add the Cluster PPTT structure + EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Cluster =3D SBSAQEMU_ACPI_PRO= CESSOR_HIERARCHY_NODE_STRUCTURE_INIT (ClusterFlags, SocketIndex, 0, 0); + CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSO= R)); + New +=3D sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR); + + L1DCache.CacheId =3D CacheId++; + // Add L1 D Cache structure + CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))= ; + ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache =3D L2C= acheIndex; + New +=3D siz= eof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); + + L1ICache.CacheId =3D CacheId++; + // Add L1 I Cache structure + CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))= ; + ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache =3D L2C= acheIndex; + New +=3D siz= eof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); + + L2Cache.CacheId =3D CacheId++; + // Add L2 Cache structure + CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE)); + New +=3D sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); + + for (CoreNum =3D 0; CoreNum < CpuTopo.Cores; CoreNum++) { + UINT32 *PrivateResourcePtr; + UINT32 CoreCpuId; + + if (CpuTopo.Threads =3D=3D 1) { + CoreCpuId =3D CpuId; + } else { + CoreCpuId =3D 0; + } + + EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Core =3D SBSAQEMU_ACPI_PROC= ESSOR_HIERARCHY_NODE_STRUCTURE_INIT (CoreFlags, ClusterIndex, CoreCpuId, 2)= ; + CopyMem (New, &Core, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR= )); + New +=3D sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR); + + PrivateResourcePtr =3D (UINT32 *)New; + PrivateResourcePtr[0] =3D L1DCacheIndex; + PrivateResourcePtr[1] =3D L1ICacheIndex; + New +=3D (2 * sizeof (UINT32)); + + if (CpuTopo.Threads =3D=3D 1) { + CpuId++; + } else { + // Add the Thread PPTT structure + for (ThreadNum =3D 0; ThreadNum < CpuTopo.Threads; ThreadNum++) = { + EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Thread =3D SBSAQEMU_ACP= I_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (ThreadFlags, CoreIndex, CpuId, 0= ); + CopyMem (New, &Thread, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PRO= CESSOR)); + New +=3D sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR); + CpuId++; + } + + CoreIndex +=3D CpuTopo.Threads * sizeof (EFI_ACPI_6_5_PPTT_STRU= CTURE_PROCESSOR); + } + + CoreIndex +=3D sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + si= zeof (UINT32) * 2; + } + + ClusterIndex =3D CoreIndex; + } + + SocketIndex =3D ClusterIndex; } =20 // Perform Checksum --=20 2.45.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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