public inbox for devel@edk2.groups.io
 help / color / mirror / Atom feed
From: "Marcin Juszkiewicz" <marcin.juszkiewicz@linaro.org>
To: devel@edk2.groups.io
Cc: Xiong Yining <xiongyining1480@phytium.com.cn>,
	 Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>,
	 Leif Lindholm <quic_llindhol@quicinc.com>,
	 Ard Biesheuvel <ardb+tianocore@kernel.org>,
	 Graeme Gregory <graeme@xora.org.uk>,
	Chen Baozi <chenbaozi@phytium.com.cn>
Subject: [edk2-devel] [PATCH edk2-platforms v3 4/5] SbsaQemu: provide cache info per core in PPTT
Date: Tue, 09 Jul 2024 12:47:09 +0200	[thread overview]
Message-ID: <20240709-acpi65-v3-4-ee93ba536fcf@linaro.org> (raw)
In-Reply-To: <20240709-acpi65-v3-0-ee93ba536fcf@linaro.org>

During Linaro Connect MAD24 I was asked to move cache information from
being 'per cluster' to be 'per core'. This is a move for implementing
MPAM support.

So topology moves from:

Socket -> Clusters -> Cores + Caches -> Threads (if exist)

to:

Socket -> Clusters -> Cores -> Caches + Threads (if exist)

Cache sizes are still 32+32+512KB (L1d, L1i, L2) as QEMU does not
implement them at all so we can tell whatever.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c        | 47 +++++++++++---------
 1 file changed, 25 insertions(+), 22 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index cf0102d11f1f..a7a9664abdcb 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -562,8 +562,8 @@ AddPpttTable (
   TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
               CpuTopo.Sockets * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
                                  CpuTopo.Clusters * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
-                                                     sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
                                                      CpuTopo.Cores * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
+                                                                      sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
                                                                       sizeof (UINT32) * 2)));
 
   if (CpuTopo.Threads > 1) {
@@ -609,10 +609,7 @@ AddPpttTable (
 
     ClusterIndex = SocketIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
     for (ClusterNum = 0; ClusterNum < CpuTopo.Clusters; ClusterNum++) {
-      L1DCacheIndex = ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
-      L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-      L2CacheIndex  = L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-      CoreIndex     = L2CacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+      CoreIndex = ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
 
       // Add the Cluster PPTT structure
       EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR  Cluster = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
@@ -624,27 +621,15 @@ AddPpttTable (
       CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
       New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
 
-      // Add L1 D Cache structure
-      L1DCache.CacheId = CacheId++;
-      CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
-      ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
-      New                                                         += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
-      // Add L1 I Cache structure
-      L1ICache.CacheId = CacheId++;
-      CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
-      ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
-      New                                                         += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
-      // Add L2 Cache structure
-      L2Cache.CacheId = CacheId++;
-      CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
-      New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
       for (CoreNum = 0; CoreNum < CpuTopo.Cores; CoreNum++) {
         UINT32  *PrivateResourcePtr;
         UINT32  CoreCpuId;
 
+        // two UINT32s for PrivateResourcePtr data
+        L1DCacheIndex = CoreIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
+        L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+        L2CacheIndex  = L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
         if (CpuTopo.Threads == 1) {
           CoreCpuId = CpuId;
         } else {
@@ -665,6 +650,23 @@ AddPpttTable (
         PrivateResourcePtr[1] = L1ICacheIndex;
         New                  += (2 * sizeof (UINT32));
 
+        // Add L1 D Cache structure
+        L1DCache.CacheId = CacheId++;
+        CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+        ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
+        New                                                         += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+        // Add L1 I Cache structure
+        L1ICache.CacheId = CacheId++;
+        CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+        ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex;
+        New                                                         += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+        // Add L2 Cache structure
+        L2Cache.CacheId = CacheId++;
+        CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+        New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
         if (CpuTopo.Threads == 1) {
           CpuId++;
         } else {
@@ -685,6 +687,7 @@ AddPpttTable (
         }
 
         CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
+        CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3;
       }
 
       ClusterIndex = CoreIndex;

-- 
2.45.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#119834): https://edk2.groups.io/g/devel/message/119834
Mute This Topic: https://groups.io/mt/107120146/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-



  parent reply	other threads:[~2024-07-09 10:47 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-09 10:47 [edk2-devel] [PATCH edk2-platforms v3 0/5] SbsaQemu: Align the PPTT tables with QEMU Marcin Juszkiewicz
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 1/5] SbsaQemu: get the information of CPU topology via SMC calls Marcin Juszkiewicz
2024-07-09 12:40   ` Leif Lindholm
     [not found]   ` <17E08BE30DD079C5.26166@groups.io>
2024-07-09 12:42     ` Leif Lindholm
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 2/5] SbsaQemu: align the PPTT tables with QEMU Marcin Juszkiewicz
2024-07-09 12:43   ` Leif Lindholm
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 3/5] SbsaQemu: update PPTT to ACPI 6.5 Marcin Juszkiewicz
2024-07-09 12:44   ` Leif Lindholm
2024-07-09 10:47 ` Marcin Juszkiewicz [this message]
2024-07-09 13:01   ` [edk2-devel] [PATCH edk2-platforms v3 4/5] SbsaQemu: provide cache info per core in PPTT Leif Lindholm
2024-07-10 13:58     ` Jonathan Cameron via groups.io
2024-07-10 14:39       ` Leif Lindholm
2024-07-09 10:47 ` [edk2-devel] [PATCH edk2-platforms v3 5/5] SbsaQemu: introduce helper in PPTT generation Marcin Juszkiewicz
2024-07-09 13:00   ` Leif Lindholm
2024-07-09 13:12     ` Marcin Juszkiewicz
2024-07-09 13:15       ` Leif Lindholm

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-list from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20240709-acpi65-v3-4-ee93ba536fcf@linaro.org \
    --to=devel@edk2.groups.io \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox