From: "Marcin Juszkiewicz" <marcin.juszkiewicz@linaro.org>
To: devel@edk2.groups.io
Cc: Xiong Yining <xiongyining1480@phytium.com.cn>,
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>,
Leif Lindholm <quic_llindhol@quicinc.com>,
Ard Biesheuvel <ardb+tianocore@kernel.org>,
Graeme Gregory <graeme@xora.org.uk>,
Chen Baozi <chenbaozi@phytium.com.cn>,
Jonathan Cameron <Jonathan.Cameron@Huawei.com>
Subject: [edk2-devel] [PATCH edk2-platforms v4 4/6] SbsaQemu: provide cache info per core in PPTT
Date: Wed, 10 Jul 2024 19:52:22 +0200 [thread overview]
Message-ID: <20240710-acpi65-v4-4-bc32224e4be4@linaro.org> (raw)
In-Reply-To: <20240710-acpi65-v4-0-bc32224e4be4@linaro.org>
During Linaro Connect MAD24 I was asked to move cache information from
being 'per cluster' to be 'per core'. This is a move for implementing
MPAM support.
So topology moves from:
Socket -> Clusters -> Cores + Caches -> Threads (if exist)
to:
Socket -> Clusters -> Cores -> Caches + Threads (if exist)
Cache sizes are still 32+32+512KB (L1d, L1i, L2) as QEMU does not
implement them at all so we can tell whatever.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 50 ++++++++++----------
1 file changed, 26 insertions(+), 24 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 8770b2293b92..e4bdd5edbd95 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -572,8 +572,8 @@ AddPpttTable (
TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
CpuTopo.Sockets * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
CpuTopo.Clusters * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
- sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
CpuTopo.Cores * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
+ sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
sizeof (UINT32) * 2)));
if (CpuTopo.Threads > 1) {
@@ -617,11 +617,6 @@ AddPpttTable (
ClusterOffset = SocketOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
for (ClusterIndex = 0; ClusterIndex < CpuTopo.Clusters; ClusterIndex++) {
- L1DCacheOffset = ClusterOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
- L1ICacheOffset = L1DCacheOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
- L2CacheOffset = L1ICacheOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
- CoreOffset = L2CacheOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
// Add the Cluster PPTT structure
EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
ClusterFlags,
@@ -632,27 +627,16 @@ AddPpttTable (
CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
- // Add L1 D Cache structure
- L1DCache.CacheId = CacheId++;
- CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheOffset;
- New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
- // Add L1 I Cache structure
- L1ICache.CacheId = CacheId++;
- CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheOffset;
- New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
- // Add L2 Cache structure
- L2Cache.CacheId = CacheId++;
- CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
- New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
+ CoreOffset = ClusterOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
for (CoreIndex = 0; CoreIndex < CpuTopo.Cores; CoreIndex++) {
UINT32 *PrivateResourcePtr;
UINT32 CoreCpuId;
+ // two UINT32s for PrivateResourcePtr data
+ L1DCacheOffset = CoreOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
+ L1ICacheOffset = L1DCacheOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+ L2CacheOffset = L1ICacheOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
if (CpuTopo.Threads == 1) {
CoreCpuId = CpuId;
} else {
@@ -673,6 +657,23 @@ AddPpttTable (
PrivateResourcePtr[1] = L1ICacheOffset;
New += (2 * sizeof (UINT32));
+ // Add L1 D Cache structure
+ L1DCache.CacheId = CacheId++;
+ CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheOffset;
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+ // Add L1 I Cache structure
+ L1ICache.CacheId = CacheId++;
+ CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheOffset;
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+ // Add L2 Cache structure
+ L2Cache.CacheId = CacheId++;
+ CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
if (CpuTopo.Threads == 1) {
CpuId++;
} else {
@@ -692,7 +693,8 @@ AddPpttTable (
CoreOffset += CpuTopo.Threads * sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
}
- CoreOffset += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
+ CoreOffset += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
+ CoreOffset += 3 * sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
}
ClusterOffset = CoreOffset;
--
2.45.2
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next prev parent reply other threads:[~2024-07-10 17:52 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-10 17:52 [edk2-devel] [PATCH edk2-platforms v4 0/6] SbsaQemu: Align the PPTT tables with QEMU Marcin Juszkiewicz
2024-07-10 17:52 ` [edk2-devel] [PATCH edk2-platforms v4 1/6] SbsaQemu: get the information of CPU topology via SMC calls Marcin Juszkiewicz
2024-07-10 17:52 ` [edk2-devel] [PATCH edk2-platforms v4 2/6] SbsaQemu: align the PPTT tables with QEMU Marcin Juszkiewicz
2024-07-10 17:52 ` [edk2-devel] [PATCH edk2-platforms v4 3/6] SbsaQemu: update PPTT to ACPI 6.5 Marcin Juszkiewicz
2024-07-10 17:52 ` Marcin Juszkiewicz [this message]
2024-07-10 17:52 ` [edk2-devel] [PATCH edk2-platforms v4 5/6] SbsaQemu: introduce helper in PPTT generation Marcin Juszkiewicz
2024-07-10 17:52 ` [edk2-devel] [PATCH edk2-platforms v4 6/6] SbsaQemu: export proper cache values in PPTT Marcin Juszkiewicz
[not found] ` <17E0EB7A956FDF20.24858@groups.io>
2024-07-11 10:46 ` Marcin Juszkiewicz
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