From: "Marcin Juszkiewicz" <marcin.juszkiewicz@linaro.org>
To: devel@edk2.groups.io
Cc: Xiong Yining <xiongyining1480@phytium.com.cn>,
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>,
Leif Lindholm <quic_llindhol@quicinc.com>,
Ard Biesheuvel <ardb+tianocore@kernel.org>,
Graeme Gregory <graeme@xora.org.uk>,
Chen Baozi <chenbaozi@phytium.com.cn>,
Jonathan Cameron <Jonathan.Cameron@Huawei.com>
Subject: [edk2-devel] [PATCH edk2-platforms v5 2/6] SbsaQemu: align the PPTT tables with QEMU
Date: Thu, 11 Jul 2024 13:31:58 +0200 [thread overview]
Message-ID: <20240711-acpi65-v5-2-a30180b74964@linaro.org> (raw)
In-Reply-To: <20240711-acpi65-v5-0-a30180b74964@linaro.org>
From: Xiong Yining <xiongyining1480@phytium.com.cn>
To align the CPU topology information recognized by the operating system
with the CPU topology information configured by QEMU, we need to make
use of the CPU topology information to create complex PPTT tables
setups.
We can get the CPU topology information via SMC.
Signed-off-by: Xiong Yining <xiongyining1480@phytium.com.cn>
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 11 ++
.../Include/IndustryStandard/SbsaQemuAcpi.h | 32 ----
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 195 ++++++++++++++++----
3 files changed, 166 insertions(+), 72 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
index e5f0748bb16e..085c681ba55f 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
@@ -88,4 +88,15 @@ typedef struct {
ClockDomain /* Clock Domain */ \
}
+#define SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT(Flags, Parent, ACPIProcessorID, NumberOfPrivateResources) \
+ { \
+ EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, /* Type */ \
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources * sizeof (UINT32), /* Length */ \
+ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, /* Reserved */ \
+ Flags, /* Flags */ \
+ Parent, /* Parent */ \
+ ACPIProcessorID, /* ACPI Processor ID */ \
+ NumberOfPrivateResources /* Number of private resources */ \
+ }
+
#endif
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index ae151210c2c6..2f87591e737a 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -166,36 +166,4 @@ typedef struct {
64 /* LineSize */ \
}
-#define SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT { \
- EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR), \
- { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
- { \
- EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, /* PhysicalPackage */ \
- EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \
- EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \
- EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, /* Not Leaf */ \
- EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ \
- }, \
- 0, /* Parent */ \
- 0, /* AcpiProcessorId */ \
- 0, /* NumberOfPrivateResources */ \
- }
-
-#define SBSAQEMU_ACPI_PPTT_CORE_STRUCT { \
- EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \
- (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + (2 * sizeof (UINT32))), \
- { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
- { \
- EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, /* PhysicalPackage */ \
- EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorValid */ \
- EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \
- EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, /* Leaf */ \
- EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ \
- }, \
- 0, /* Parent */ \
- 0, /* AcpiProcessorId */ \
- 2, /* NumberOfPrivateResources */ \
- }
-
#endif
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index e0eef54ff907..48cec24721d6 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -505,14 +505,61 @@ AddPpttTable (
EFI_PHYSICAL_ADDRESS PageAddress;
UINT8 *New;
UINT32 CpuId;
- UINT32 NumCores = GetCpuCount ();
+ CpuTopology CpuTopo;
+ UINT32 SocketIndex;
+ UINT32 ClusterIndex;
+ UINT32 CoreIndex;
+ UINT32 ThreadIndex;
+ UINT32 SocketOffset;
+ UINT32 ClusterOffset;
+ UINT32 CoreOffset;
+ UINT32 L1DCacheOffset;
+ UINT32 L1ICacheOffset;
+ UINT32 L2CacheOffset;
+
+ GetCpuTopology (&CpuTopo);
EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT;
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PPTT_CORE_STRUCT;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS SocketFlags = {
+ EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ };
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS ClusterFlags = {
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ };
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS CoreFlags = {
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ };
+
+ if (CpuTopo.Threads > 1) {
+ // The Thread structure is the leaf structure, adjust the value of CoreFlags.
+ CoreFlags.AcpiProcessorIdValid = EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID;
+ CoreFlags.NodeIsALeaf = EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF;
+ }
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS ThreadFlags = {
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ };
EFI_ACPI_DESCRIPTION_HEADER Header =
SBSAQEMU_ACPI_HEADER (
@@ -522,10 +569,16 @@ AddPpttTable (
);
TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
- (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3) +
- (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) * NumCores) +
- (sizeof (UINT32) * 2 * NumCores);
+ CpuTopo.Sockets * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
+ CpuTopo.Clusters * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3 +
+ CpuTopo.Cores * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
+ sizeof (UINT32) * 2)));
+
+ if (CpuTopo.Threads > 1) {
+ TableSize += CpuTopo.Sockets * CpuTopo.Clusters * CpuTopo.Cores * CpuTopo.Threads *
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ }
Status = gBS->AllocatePages (
AllocateAnyPages,
@@ -546,39 +599,101 @@ AddPpttTable (
((EFI_ACPI_DESCRIPTION_HEADER *)New)->Length = TableSize;
New += sizeof (EFI_ACPI_DESCRIPTION_HEADER);
- // Add the Cluster PPTT structure
- CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
-
- // Add L1 D Cache structure
- CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2_CACHE_INDEX;
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
-
- // Add L1 I Cache structure
- CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2_CACHE_INDEX;
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
-
- // Add L2 Cache structure
- CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 0; /* L2 is LLC */
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
-
- for (CpuId = 0; CpuId < NumCores; CpuId++) {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *CorePtr;
- UINT32 *PrivateResourcePtr;
-
- CopyMem (New, &Core, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
- CorePtr = (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *)New;
- CorePtr->Parent = CLUSTER_INDEX;
- CorePtr->AcpiProcessorId = CpuId;
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
-
- PrivateResourcePtr = (UINT32 *)New;
- PrivateResourcePtr[0] = L1_D_CACHE_INDEX;
- PrivateResourcePtr[1] = L1_I_CACHE_INDEX;
- New += (2 * sizeof (UINT32));
+ CpuId = 0;
+
+ SocketOffset = sizeof (EFI_ACPI_DESCRIPTION_HEADER);
+ for (SocketIndex = 0; SocketIndex < CpuTopo.Sockets; SocketIndex++) {
+ // Add the Socket PPTT structure
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Socket = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ SocketFlags,
+ 0,
+ 0,
+ 0
+ );
+ CopyMem (New, &Socket, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+
+ ClusterOffset = SocketOffset + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ for (ClusterIndex = 0; ClusterIndex < CpuTopo.Clusters; ClusterIndex++) {
+ L1DCacheOffset = ClusterOffset + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ L1ICacheOffset = L1DCacheOffset + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+ L2CacheOffset = L1ICacheOffset + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+ CoreOffset = L2CacheOffset + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+
+ // Add the Cluster PPTT structure
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ ClusterFlags,
+ SocketOffset,
+ 0,
+ 0
+ );
+ CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+
+ // Add L1 D Cache structure
+ CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheOffset;
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+
+ // Add L1 I Cache structure
+ CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheOffset;
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+
+ // Add L2 Cache structure
+ CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+
+ for (CoreIndex = 0; CoreIndex < CpuTopo.Cores; CoreIndex++) {
+ UINT32 *PrivateResourcePtr;
+ UINT32 CoreCpuId;
+
+ if (CpuTopo.Threads == 1) {
+ CoreCpuId = CpuId;
+ } else {
+ CoreCpuId = 0;
+ }
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ CoreFlags,
+ ClusterOffset,
+ CoreCpuId,
+ 2
+ );
+ CopyMem (New, &Core, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+
+ PrivateResourcePtr = (UINT32 *)New;
+ PrivateResourcePtr[0] = L1DCacheOffset;
+ PrivateResourcePtr[1] = L1ICacheOffset;
+ New += (2 * sizeof (UINT32));
+
+ if (CpuTopo.Threads == 1) {
+ CpuId++;
+ } else {
+ // Add the Thread PPTT structure
+ for (ThreadIndex = 0; ThreadIndex < CpuTopo.Threads; ThreadIndex++) {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Thread = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ ThreadFlags,
+ CoreOffset,
+ CpuId,
+ 0
+ );
+ CopyMem (New, &Thread, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ CpuId++;
+ }
+
+ CoreOffset += CpuTopo.Threads * sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ }
+
+ CoreOffset += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
+ }
+
+ ClusterOffset = CoreOffset;
+ }
+
+ SocketOffset = ClusterOffset;
}
// Perform Checksum
--
2.45.2
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next prev parent reply other threads:[~2024-07-11 11:32 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-11 11:31 [edk2-devel] [PATCH edk2-platforms v5 0/6] SbsaQemu: Align the PPTT tables with QEMU Marcin Juszkiewicz
2024-07-11 11:31 ` [edk2-devel] [PATCH edk2-platforms v5 1/6] SbsaQemu: get the information of CPU topology via SMC calls Marcin Juszkiewicz
2024-07-11 11:31 ` Marcin Juszkiewicz [this message]
2024-07-11 11:31 ` [edk2-devel] [PATCH edk2-platforms v5 3/6] SbsaQemu: update PPTT to ACPI 6.5 Marcin Juszkiewicz
2024-07-11 11:32 ` [edk2-devel] [PATCH edk2-platforms v5 4/6] SbsaQemu: provide cache info per core in PPTT Marcin Juszkiewicz
2024-07-11 11:32 ` [edk2-devel] [PATCH edk2-platforms v5 5/6] SbsaQemu: introduce helper in PPTT generation Marcin Juszkiewicz
2024-07-11 11:32 ` [edk2-devel] [PATCH edk2-platforms v5 6/6] SbsaQemu: export proper cache values in PPTT Marcin Juszkiewicz
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