From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id F04C67803CF for ; Thu, 11 Jul 2024 11:32:26 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=+RKB/4rm8kW7B9IIsw8YEwiZLacZEcFoJI6tpn0QfXk=; c=relaxed/simple; d=groups.io; h=From:Date:Subject:MIME-Version:Message-Id:References:In-Reply-To:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20240206; t=1720697546; v=1; b=B6v8j9r6Dc9feYOT9or9leeOYThbo7vXhAmGlDK1xuu6YXjGq11mxZoO/M4pSAdJBC3rzPv9 Z0+QFLos9xYUzv062TlghPVkcg77MeHMZ1NXu3NPIzUUgI3IyfhhDh36ySwJHyEzMm/1elJGctx MOgYSZ2YsbajC2WEfl74k1I29hry9tG2oq9zgq/XpLcOVDgBkKZZxSfMYY2zxO1ONQn9ftmM/Ra hc2cROGg9KHOLUGjlklA4cL+rVeWtt3l002++Y0kjv8ewkWpq2OB1K59pGGeiTY0mzLXsvR9GO2 4ClGU5voP8cgTjh6RwyXSE3fJg2T5z+fkKIAZQbz4wiCw== X-Received: by 127.0.0.2 with SMTP id X8vkYY7687511xfkyZAhhDJZ; Thu, 11 Jul 2024 04:32:25 -0700 X-Received: from muminek.juszkiewicz.com.pl (muminek.juszkiewicz.com.pl [213.251.184.221]) by mx.groups.io with SMTP id smtpd.web11.9671.1720697544220986858 for ; Thu, 11 Jul 2024 04:32:24 -0700 X-Received: from localhost (localhost [127.0.0.1]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTP id 2DF3B260885; Thu, 11 Jul 2024 13:32:22 +0200 (CEST) X-Virus-Scanned: Debian amavis at juszkiewicz.com.pl X-Received: from muminek.juszkiewicz.com.pl ([127.0.0.1]) by localhost (muminek.juszkiewicz.com.pl [127.0.0.1]) (amavis, port 10024) with ESMTP id dyJOy0i8ti6p; Thu, 11 Jul 2024 13:32:20 +0200 (CEST) X-Received: from applejack.lan (83.8.74.165.ipv4.supernova.orange.pl [83.8.74.165]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTPSA id A306A260CF0; Thu, 11 Jul 2024 13:32:17 +0200 (CEST) From: "Marcin Juszkiewicz" Date: Thu, 11 Jul 2024 13:32:02 +0200 Subject: [edk2-devel] [PATCH edk2-platforms v5 6/6] SbsaQemu: export proper cache values in PPTT MIME-Version: 1.0 Message-Id: <20240711-acpi65-v5-6-a30180b74964@linaro.org> References: <20240711-acpi65-v5-0-a30180b74964@linaro.org> In-Reply-To: <20240711-acpi65-v5-0-a30180b74964@linaro.org> To: devel@edk2.groups.io Cc: Xiong Yining , Marcin Juszkiewicz , Leif Lindholm , Ard Biesheuvel , Graeme Gregory , Chen Baozi , Jonathan Cameron Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Thu, 11 Jul 2024 04:32:24 -0700 Resent-From: marcin.juszkiewicz@linaro.org Reply-To: devel@edk2.groups.io,marcin.juszkiewicz@linaro.org List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: t2iIufvAOktNBqkuWTm6QUfEx7686176AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=B6v8j9r6; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=linaro.org (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io We were exporting fake cpu cache values instead of reading them from CCSIDR registers. This change gets rid of fake values in favour of existing ones. Based on Ampere platform core. Added support for cpus with FEAT_CCIDX (Neoverse-V1 and above). Reported-by: Jonathan Cameron Signed-off-by: Marcin Juszkiewicz --- .../SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 32 +++++--------- .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 45 ++++++++++++++++= ++++ 2 files changed, 55 insertions(+), 22 deletions(-) diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h = b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h index fa2e2b30bb7d..9a7c96fc6970 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h @@ -74,18 +74,6 @@ typedef struct { UINT8 uid[8]; } SBSAQEMU_ACPI_CPU_DEVICE; =20 -#define SBSAQEMU_L1_D_CACHE_SIZE SIZE_32KB -#define SBSAQEMU_L1_D_CACHE_SETS 256 -#define SBSAQEMU_L1_D_CACHE_ASSC 2 - -#define SBSAQEMU_L1_I_CACHE_SIZE SIZE_32KB -#define SBSAQEMU_L1_I_CACHE_SETS 256 -#define SBSAQEMU_L1_I_CACHE_ASSC 2 - -#define SBSAQEMU_L2_CACHE_SIZE SIZE_512KB -#define SBSAQEMU_L2_CACHE_SETS 1024 -#define SBSAQEMU_L2_CACHE_ASSC 8 - #define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER)) #define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_5_PPTT_STRUC= TURE_PROCESSOR)) #define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_5_PPTT_ST= RUCTURE_CACHE)) @@ -106,9 +94,9 @@ typedef struct { 1, /* CacheIdValid */ = \ }, = \ 0, /* NextLevelOfCache */ = \ - SBSAQEMU_L1_D_CACHE_SIZE, /* Size */ = \ - SBSAQEMU_L1_D_CACHE_SETS, /* NumberOfSets */ = \ - SBSAQEMU_L1_D_CACHE_ASSC, /* Associativity */ = \ + 0, /* Size */ = \ + 0, /* NumberOfSets */ = \ + 0, /* Associativity */ = \ { = \ EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, = \ @@ -133,9 +121,9 @@ typedef struct { 1, /* CacheIdValid */ = \ }, = \ 0, /* NextLevelOfCache */ = \ - SBSAQEMU_L1_I_CACHE_SIZE, /* Size */ = \ - SBSAQEMU_L1_I_CACHE_SETS, /* NumberOfSets */ = \ - SBSAQEMU_L1_I_CACHE_ASSC, /* Associativity */ = \ + 0, /* Size */ = \ + 0, /* NumberOfSets */ = \ + 0, /* Associativity */ = \ { = \ EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ, = \ EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, = \ @@ -159,10 +147,10 @@ typedef struct { 1, /* LineSizeValid */ = \ 1, /* CacheIdValid */ = \ }, = \ - 0, /* NextLevelOfCache */ = \ - SBSAQEMU_L2_CACHE_SIZE, /* Size */ = \ - SBSAQEMU_L2_CACHE_SETS, /* NumberOfSets */ = \ - SBSAQEMU_L2_CACHE_ASSC, /* Associativity */ = \ + 0, /* NextLevelOfCache */ = \ + 0, /* Size */ = \ + 0, /* NumberOfSets */ = \ + 0, /* Associativity */ = \ { = \ EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, = \ diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index 61f9de45d082..9554956432c3 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -2,15 +2,18 @@ * This file is an ACPI driver for the Qemu SBSA platform. * * Copyright (c) 2020-2024, Linaro Ltd. All rights reserved. +* Copyright (c) 2020-2021, Ampere Computing LLC. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * **/ #include #include +#include #include #include #include +#include #include #include #include @@ -494,6 +497,44 @@ AddSsdtTable ( return Status; } =20 +STATIC VOID +AcpiPpttFillCacheSizeInfo ( + EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *Node, + UINT32 Level, + BOOLEAN DataCache, + BOOLEAN UnifiedCache + ) +{ + CSSELR_DATA CsselrData; + CCSIDR_DATA CcsidrData; + + CsselrData.Data =3D 0; + CsselrData.Bits.Level =3D Level - 1; + CsselrData.Bits.InD =3D (!DataCache && !UnifiedCache); + + CcsidrData.Data =3D ReadCCSIDR (CsselrData.Data); + + Node->Flags.LineSizeValid =3D 1; + Node->Flags.NumberOfSetsValid =3D 1; + Node->Flags.AssociativityValid =3D 1; + Node->Flags.SizePropertyValid =3D 1; + Node->Flags.CacheTypeValid =3D 1; + + if (ArmHasCcidx ()) { + Node->NumberOfSets =3D CcsidrData.BitsCcidxAA64.NumSets + 1; + Node->Associativity =3D CcsidrData.BitsCcidxAA64.Associativity + 1; + Node->LineSize =3D (1 << (CcsidrData.BitsCcidxAA64.LineSize + 4))= ; + } else { + Node->NumberOfSets =3D (UINT16)CcsidrData.BitsNonCcidx.NumSets + 1; + Node->Associativity =3D (UINT16)CcsidrData.BitsNonCcidx.Associativity = + 1; + Node->LineSize =3D (UINT16)(1 << (CcsidrData.BitsNonCcidx.LineSiz= e + 4)); + } + + Node->Size =3D Node->NumberOfSets * + Node->Associativity * + Node->LineSize; +} + STATIC UINT32 AddCoresToPpttTable ( @@ -538,6 +579,10 @@ AddCoresToPpttTable ( EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1ICache =3D SBSAQEMU_ACPI_PPTT_L1_I_= CACHE_STRUCT; EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L2Cache =3D SBSAQEMU_ACPI_PPTT_L2_CA= CHE_STRUCT; =20 + AcpiPpttFillCacheSizeInfo (&L1DCache, 1, TRUE, FALSE); + AcpiPpttFillCacheSizeInfo (&L1ICache, 1, FALSE, FALSE); + AcpiPpttFillCacheSizeInfo (&L2Cache, 2, FALSE, TRUE); + CoreOffset =3D ClusterOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCE= SSOR); Offset =3D CoreOffset; =20 --=20 2.45.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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