From: "Marcin Juszkiewicz" <marcin.juszkiewicz@linaro.org>
To: devel@edk2.groups.io
Cc: Xiong Yining <xiongyining1480@phytium.com.cn>,
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>,
Leif Lindholm <quic_llindhol@quicinc.com>,
Ard Biesheuvel <ardb+tianocore@kernel.org>,
Graeme Gregory <graeme@xora.org.uk>,
Chen Baozi <chenbaozi@phytium.com.cn>,
Jonathan Cameron <Jonathan.Cameron@Huawei.com>
Subject: [edk2-devel] [PATCH edk2-platforms v6 6/6] SbsaQemu: export proper cache values in PPTT
Date: Wed, 07 Aug 2024 13:34:44 +0200 [thread overview]
Message-ID: <20240807-acpi65-v6-6-fc426e4abfe2@linaro.org> (raw)
In-Reply-To: <20240807-acpi65-v6-0-fc426e4abfe2@linaro.org>
We were exporting fake cpu cache values instead of reading them from
CCSIDR registers.
This change gets rid of fake values in favour of existing ones.
Based on Ampere platform core. Added support for cpus with FEAT_CCIDX
(Neoverse-V1 and above).
Reported-by: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
.../SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 32 +++++---------
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 45 ++++++++++++++++++++
2 files changed, 55 insertions(+), 22 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index fa2e2b30bb7d..9a7c96fc6970 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -74,18 +74,6 @@ typedef struct {
UINT8 uid[8];
} SBSAQEMU_ACPI_CPU_DEVICE;
-#define SBSAQEMU_L1_D_CACHE_SIZE SIZE_32KB
-#define SBSAQEMU_L1_D_CACHE_SETS 256
-#define SBSAQEMU_L1_D_CACHE_ASSC 2
-
-#define SBSAQEMU_L1_I_CACHE_SIZE SIZE_32KB
-#define SBSAQEMU_L1_I_CACHE_SETS 256
-#define SBSAQEMU_L1_I_CACHE_ASSC 2
-
-#define SBSAQEMU_L2_CACHE_SIZE SIZE_512KB
-#define SBSAQEMU_L2_CACHE_SETS 1024
-#define SBSAQEMU_L2_CACHE_ASSC 8
-
#define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER))
#define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR))
#define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))
@@ -106,9 +94,9 @@ typedef struct {
1, /* CacheIdValid */ \
}, \
0, /* NextLevelOfCache */ \
- SBSAQEMU_L1_D_CACHE_SIZE, /* Size */ \
- SBSAQEMU_L1_D_CACHE_SETS, /* NumberOfSets */ \
- SBSAQEMU_L1_D_CACHE_ASSC, /* Associativity */ \
+ 0, /* Size */ \
+ 0, /* NumberOfSets */ \
+ 0, /* Associativity */ \
{ \
EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
@@ -133,9 +121,9 @@ typedef struct {
1, /* CacheIdValid */ \
}, \
0, /* NextLevelOfCache */ \
- SBSAQEMU_L1_I_CACHE_SIZE, /* Size */ \
- SBSAQEMU_L1_I_CACHE_SETS, /* NumberOfSets */ \
- SBSAQEMU_L1_I_CACHE_ASSC, /* Associativity */ \
+ 0, /* Size */ \
+ 0, /* NumberOfSets */ \
+ 0, /* Associativity */ \
{ \
EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ, \
EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
@@ -159,10 +147,10 @@ typedef struct {
1, /* LineSizeValid */ \
1, /* CacheIdValid */ \
}, \
- 0, /* NextLevelOfCache */ \
- SBSAQEMU_L2_CACHE_SIZE, /* Size */ \
- SBSAQEMU_L2_CACHE_SETS, /* NumberOfSets */ \
- SBSAQEMU_L2_CACHE_ASSC, /* Associativity */ \
+ 0, /* NextLevelOfCache */ \
+ 0, /* Size */ \
+ 0, /* NumberOfSets */ \
+ 0, /* Associativity */ \
{ \
EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 61f9de45d082..9554956432c3 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -2,15 +2,18 @@
* This file is an ACPI driver for the Qemu SBSA platform.
*
* Copyright (c) 2020-2024, Linaro Ltd. All rights reserved.
+* Copyright (c) 2020-2021, Ampere Computing LLC. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <IndustryStandard/Acpi.h>
#include <IndustryStandard/AcpiAml.h>
+#include <IndustryStandard/ArmCache.h>
#include <IndustryStandard/IoRemappingTable.h>
#include <IndustryStandard/SbsaQemuAcpi.h>
#include <IndustryStandard/SbsaQemuPlatformVersion.h>
+#include <Library/ArmLib/AArch64/AArch64Lib.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/BaseMemoryLib.h>
@@ -494,6 +497,44 @@ AddSsdtTable (
return Status;
}
+STATIC VOID
+AcpiPpttFillCacheSizeInfo (
+ EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *Node,
+ UINT32 Level,
+ BOOLEAN DataCache,
+ BOOLEAN UnifiedCache
+ )
+{
+ CSSELR_DATA CsselrData;
+ CCSIDR_DATA CcsidrData;
+
+ CsselrData.Data = 0;
+ CsselrData.Bits.Level = Level - 1;
+ CsselrData.Bits.InD = (!DataCache && !UnifiedCache);
+
+ CcsidrData.Data = ReadCCSIDR (CsselrData.Data);
+
+ Node->Flags.LineSizeValid = 1;
+ Node->Flags.NumberOfSetsValid = 1;
+ Node->Flags.AssociativityValid = 1;
+ Node->Flags.SizePropertyValid = 1;
+ Node->Flags.CacheTypeValid = 1;
+
+ if (ArmHasCcidx ()) {
+ Node->NumberOfSets = CcsidrData.BitsCcidxAA64.NumSets + 1;
+ Node->Associativity = CcsidrData.BitsCcidxAA64.Associativity + 1;
+ Node->LineSize = (1 << (CcsidrData.BitsCcidxAA64.LineSize + 4));
+ } else {
+ Node->NumberOfSets = (UINT16)CcsidrData.BitsNonCcidx.NumSets + 1;
+ Node->Associativity = (UINT16)CcsidrData.BitsNonCcidx.Associativity + 1;
+ Node->LineSize = (UINT16)(1 << (CcsidrData.BitsNonCcidx.LineSize + 4));
+ }
+
+ Node->Size = Node->NumberOfSets *
+ Node->Associativity *
+ Node->LineSize;
+}
+
STATIC
UINT32
AddCoresToPpttTable (
@@ -538,6 +579,10 @@ AddCoresToPpttTable (
EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
+ AcpiPpttFillCacheSizeInfo (&L1DCache, 1, TRUE, FALSE);
+ AcpiPpttFillCacheSizeInfo (&L1ICache, 1, FALSE, FALSE);
+ AcpiPpttFillCacheSizeInfo (&L2Cache, 2, FALSE, TRUE);
+
CoreOffset = ClusterOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
Offset = CoreOffset;
--
2.45.2
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next prev parent reply other threads:[~2024-08-07 11:35 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-07 11:34 [edk2-devel] [PATCH edk2-platforms v6 0/6] SbsaQemu: Align the PPTT tables with QEMU Marcin Juszkiewicz
2024-08-07 11:34 ` [edk2-devel] [PATCH edk2-platforms v6 1/6] SbsaQemu: get the information of CPU topology via SMC calls Marcin Juszkiewicz
2024-08-07 11:34 ` [edk2-devel] [PATCH edk2-platforms v6 2/6] SbsaQemu: align the PPTT tables with QEMU Marcin Juszkiewicz
2024-08-07 11:34 ` [edk2-devel] [PATCH edk2-platforms v6 3/6] SbsaQemu: update PPTT to ACPI 6.5 Marcin Juszkiewicz
2024-08-07 11:34 ` [edk2-devel] [PATCH edk2-platforms v6 4/6] SbsaQemu: provide cache info per core in PPTT Marcin Juszkiewicz
2024-08-07 11:34 ` [edk2-devel] [PATCH edk2-platforms v6 5/6] SbsaQemu: introduce helper in PPTT generation Marcin Juszkiewicz
2024-08-07 11:34 ` Marcin Juszkiewicz [this message]
2024-08-07 16:29 ` [edk2-devel] [PATCH edk2-platforms v6 0/6] SbsaQemu: Align the PPTT tables with QEMU Leif Lindholm
2024-08-07 16:42 ` Marcin Juszkiewicz
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