From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id 70373AC0B4C for ; Wed, 7 Aug 2024 11:35:31 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=yJiDrM6mZ/nZxHvcbfZJKKfhc1zDQDVtTnUZ1OfjVUo=; c=relaxed/simple; d=groups.io; h=From:Date:Subject:MIME-Version:Message-Id:References:In-Reply-To:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20240206; t=1723030531; v=1; b=FduLAYoYfCq2o/i4sMXiH/nN/TsUVT1XOJmVavIcPiNd6vYv+IrdiYf5odgw9VhvYDvCYTLQ nDJo6YWAV5EbqdftemGy8hQB/8526Qav8XnW9cmGow5lgae8KhVj13iY1Y/QB1m99Wb15PVIxip dBTNnyoPya+tGOSUuFaNbtaOFZ0f+rDk4pGoLO3KWnCrNFISlI7ATTAp5wmJC7P/EKMUCbwex9h gUJm+l47x0z5mO6DAK1aX34K29Ua2EgFY6t++z9E8FBFfHt5VeZUxb+oAwax+k9qvKkcjWN+NS4 c3hf8Ydr9SNRx0kAL+91fHBOq3JcE3yGRuQGJ5sp+U7uA== X-Received: by 127.0.0.2 with SMTP id lDTKYY7687511xdULbgomIIY; Wed, 07 Aug 2024 04:35:29 -0700 X-Received: from muminek.juszkiewicz.com.pl (muminek.juszkiewicz.com.pl [213.251.184.221]) by mx.groups.io with SMTP id smtpd.web10.31182.1723030524077984810 for ; Wed, 07 Aug 2024 04:35:24 -0700 X-Received: from localhost (localhost [127.0.0.1]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTP id 5DE5326018D; Wed, 7 Aug 2024 13:35:22 +0200 (CEST) X-Virus-Scanned: Debian amavis at juszkiewicz.com.pl X-Received: from muminek.juszkiewicz.com.pl ([127.0.0.1]) by localhost (muminek.juszkiewicz.com.pl [127.0.0.1]) (amavis, port 10024) with ESMTP id PDIpPpgT0nc6; Wed, 7 Aug 2024 13:35:20 +0200 (CEST) X-Received: from applejack.lan (83.8.56.232.ipv4.supernova.orange.pl [83.8.56.232]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTPSA id 49A83261997; Wed, 7 Aug 2024 13:35:17 +0200 (CEST) From: "Marcin Juszkiewicz" Date: Wed, 07 Aug 2024 13:34:44 +0200 Subject: [edk2-devel] [PATCH edk2-platforms v6 6/6] SbsaQemu: export proper cache values in PPTT MIME-Version: 1.0 Message-Id: <20240807-acpi65-v6-6-fc426e4abfe2@linaro.org> References: <20240807-acpi65-v6-0-fc426e4abfe2@linaro.org> In-Reply-To: <20240807-acpi65-v6-0-fc426e4abfe2@linaro.org> To: devel@edk2.groups.io Cc: Xiong Yining , Marcin Juszkiewicz , Leif Lindholm , Ard Biesheuvel , Graeme Gregory , Chen Baozi , Jonathan Cameron Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Wed, 07 Aug 2024 04:35:24 -0700 Resent-From: marcin.juszkiewicz@linaro.org Reply-To: devel@edk2.groups.io,marcin.juszkiewicz@linaro.org List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: uGUvjv2hZTdNgRde0Se5nKWxx7686176AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=FduLAYoY; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=linaro.org (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io We were exporting fake cpu cache values instead of reading them from CCSIDR registers. This change gets rid of fake values in favour of existing ones. Based on Ampere platform core. Added support for cpus with FEAT_CCIDX (Neoverse-V1 and above). Reported-by: Jonathan Cameron Signed-off-by: Marcin Juszkiewicz --- .../SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 32 +++++--------- .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 45 ++++++++++++++++= ++++ 2 files changed, 55 insertions(+), 22 deletions(-) diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h = b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h index fa2e2b30bb7d..9a7c96fc6970 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h @@ -74,18 +74,6 @@ typedef struct { UINT8 uid[8]; } SBSAQEMU_ACPI_CPU_DEVICE; =20 -#define SBSAQEMU_L1_D_CACHE_SIZE SIZE_32KB -#define SBSAQEMU_L1_D_CACHE_SETS 256 -#define SBSAQEMU_L1_D_CACHE_ASSC 2 - -#define SBSAQEMU_L1_I_CACHE_SIZE SIZE_32KB -#define SBSAQEMU_L1_I_CACHE_SETS 256 -#define SBSAQEMU_L1_I_CACHE_ASSC 2 - -#define SBSAQEMU_L2_CACHE_SIZE SIZE_512KB -#define SBSAQEMU_L2_CACHE_SETS 1024 -#define SBSAQEMU_L2_CACHE_ASSC 8 - #define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER)) #define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_5_PPTT_STRUC= TURE_PROCESSOR)) #define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_5_PPTT_ST= RUCTURE_CACHE)) @@ -106,9 +94,9 @@ typedef struct { 1, /* CacheIdValid */ = \ }, = \ 0, /* NextLevelOfCache */ = \ - SBSAQEMU_L1_D_CACHE_SIZE, /* Size */ = \ - SBSAQEMU_L1_D_CACHE_SETS, /* NumberOfSets */ = \ - SBSAQEMU_L1_D_CACHE_ASSC, /* Associativity */ = \ + 0, /* Size */ = \ + 0, /* NumberOfSets */ = \ + 0, /* Associativity */ = \ { = \ EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, = \ @@ -133,9 +121,9 @@ typedef struct { 1, /* CacheIdValid */ = \ }, = \ 0, /* NextLevelOfCache */ = \ - SBSAQEMU_L1_I_CACHE_SIZE, /* Size */ = \ - SBSAQEMU_L1_I_CACHE_SETS, /* NumberOfSets */ = \ - SBSAQEMU_L1_I_CACHE_ASSC, /* Associativity */ = \ + 0, /* Size */ = \ + 0, /* NumberOfSets */ = \ + 0, /* Associativity */ = \ { = \ EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ, = \ EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, = \ @@ -159,10 +147,10 @@ typedef struct { 1, /* LineSizeValid */ = \ 1, /* CacheIdValid */ = \ }, = \ - 0, /* NextLevelOfCache */ = \ - SBSAQEMU_L2_CACHE_SIZE, /* Size */ = \ - SBSAQEMU_L2_CACHE_SETS, /* NumberOfSets */ = \ - SBSAQEMU_L2_CACHE_ASSC, /* Associativity */ = \ + 0, /* NextLevelOfCache */ = \ + 0, /* Size */ = \ + 0, /* NumberOfSets */ = \ + 0, /* Associativity */ = \ { = \ EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, = \ diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index 61f9de45d082..9554956432c3 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -2,15 +2,18 @@ * This file is an ACPI driver for the Qemu SBSA platform. * * Copyright (c) 2020-2024, Linaro Ltd. All rights reserved. +* Copyright (c) 2020-2021, Ampere Computing LLC. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * **/ #include #include +#include #include #include #include +#include #include #include #include @@ -494,6 +497,44 @@ AddSsdtTable ( return Status; } =20 +STATIC VOID +AcpiPpttFillCacheSizeInfo ( + EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *Node, + UINT32 Level, + BOOLEAN DataCache, + BOOLEAN UnifiedCache + ) +{ + CSSELR_DATA CsselrData; + CCSIDR_DATA CcsidrData; + + CsselrData.Data =3D 0; + CsselrData.Bits.Level =3D Level - 1; + CsselrData.Bits.InD =3D (!DataCache && !UnifiedCache); + + CcsidrData.Data =3D ReadCCSIDR (CsselrData.Data); + + Node->Flags.LineSizeValid =3D 1; + Node->Flags.NumberOfSetsValid =3D 1; + Node->Flags.AssociativityValid =3D 1; + Node->Flags.SizePropertyValid =3D 1; + Node->Flags.CacheTypeValid =3D 1; + + if (ArmHasCcidx ()) { + Node->NumberOfSets =3D CcsidrData.BitsCcidxAA64.NumSets + 1; + Node->Associativity =3D CcsidrData.BitsCcidxAA64.Associativity + 1; + Node->LineSize =3D (1 << (CcsidrData.BitsCcidxAA64.LineSize + 4))= ; + } else { + Node->NumberOfSets =3D (UINT16)CcsidrData.BitsNonCcidx.NumSets + 1; + Node->Associativity =3D (UINT16)CcsidrData.BitsNonCcidx.Associativity = + 1; + Node->LineSize =3D (UINT16)(1 << (CcsidrData.BitsNonCcidx.LineSiz= e + 4)); + } + + Node->Size =3D Node->NumberOfSets * + Node->Associativity * + Node->LineSize; +} + STATIC UINT32 AddCoresToPpttTable ( @@ -538,6 +579,10 @@ AddCoresToPpttTable ( EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1ICache =3D SBSAQEMU_ACPI_PPTT_L1_I_= CACHE_STRUCT; EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L2Cache =3D SBSAQEMU_ACPI_PPTT_L2_CA= CHE_STRUCT; =20 + AcpiPpttFillCacheSizeInfo (&L1DCache, 1, TRUE, FALSE); + AcpiPpttFillCacheSizeInfo (&L1ICache, 1, FALSE, FALSE); + AcpiPpttFillCacheSizeInfo (&L2Cache, 2, FALSE, TRUE); + CoreOffset =3D ClusterOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCE= SSOR); Offset =3D CoreOffset; =20 --=20 2.45.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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