From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id B26A3780091 for ; Wed, 23 Oct 2024 17:00:13 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=eUdRkhw+Hm0KH5+CUIPHMcMLXH7w+AI8d2nffOamJDc=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20240830; t=1729702813; v=1; x=1729962012; b=QdZLugpp8dbc5ap/dcQOt3iz8U/1meSQteja/aQ8ZaVWnh9RAwQMEz/opvfiEZIFohbrDmNn mcWVJQd7iy0rgScNTdDGAJgPGA02/PrRrqnSyyYr7l9k9ebzAGoxMw+benzwIBB80mGrmOR1q6D PJ3bYgGdJBUzWdppE3pEA5wimknCOOSPchoEAqaREDObeZpzk48oolT6M/Km/E23uN4fvNibETn yM8vWT6BMzcxi6jhVjUMaFpGvwf84QEFrNAK1B+yo0bHtga+o2TikjMeNC9DaItPsPzqzQy2AT0 MejEp0GLOlj+IXb00FfTPJ8mAy04JB0j8E03Tv+T+4BFA== X-Received: by 127.0.0.2 with SMTP id AUeDYY7687511xmA7LVnxbuD; Wed, 23 Oct 2024 10:00:12 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by mx.groups.io with SMTP id smtpd.web10.12510.1729212931247833055 for ; Thu, 17 Oct 2024 17:55:32 -0700 X-CSE-ConnectionGUID: hj/aXWUQTHGy274tiEk6BA== X-CSE-MsgGUID: EDnypjY2Q5mrJocHSI5FRA== X-IronPort-AV: E=McAfee;i="6700,10204,11228"; a="39364009" X-IronPort-AV: E=Sophos;i="6.11,212,1725346800"; d="scan'208";a="39364009" X-Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Oct 2024 17:55:32 -0700 X-CSE-ConnectionGUID: 5k6Nri8jR/+i2x/QKnbV9A== X-CSE-MsgGUID: L8bvpSFPQfiw6dTYBThF9w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,212,1725346800"; d="scan'208";a="82676863" X-Received: from shwdeopenlab108.ccr.corp.intel.com ([10.239.55.64]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Oct 2024 17:55:31 -0700 From: Foster Nong To: devel@edk2.groups.io Cc: Foster Nong , Michael D Kinney , Liming Gao , Ray Ni Subject: [edk2-devel] [PATCH v2 2/2] MdeModulePkg:New Pcd to platform constrain BarSize Date: Fri, 18 Oct 2024 08:55:09 +0800 Message-Id: <20241018005509.2913-2-foster.nong@intel.com> In-Reply-To: <20241018005509.2913-1-foster.nong@intel.com> References: <20241018005509.2913-1-foster.nong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Wed, 23 Oct 2024 10:00:07 -0700 Resent-From: foster.nong@intel.com Reply-To: devel@edk2.groups.io,foster.nong@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: Gk8fCAgkMYmmsNqnPJC6Lg18x7686176AA= Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240830 header.b=QdZLugpp; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4868 1. Define a new dynamic PCD in MdeModulePkg gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableMaxBarSize 2. Modify PciProgramResizableBar() to implement configure BAR Size within platform constrain provided in PcdPcieResizableMaxBarSize Signed-off-by: Foster Nong Cc: Michael D Kinney Cc: Liming Gao Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 1 + MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c | 25 +++++++++++++++++--- MdeModulePkg/MdeModulePkg.dec | 5 ++++ 3 files changed, 28 insertions(+), 3 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf b/MdeModulePkg/Bu= s/Pci/PciBusDxe/PciBusDxe.inf index e317169d9c..f038b6eef2 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf @@ -107,6 +107,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport ## CONSUME= S=0D gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration ## SOMETIM= ES_CONSUMES=0D gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport ## CONSUME= S=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableMaxBarSize ## CONSUME= S=0D =0D [UserExtensions.TianoCore."ExtraFiles"]=0D PciBusDxeExtra.uni=0D diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciLib.c index dc5fd27665..95f331d0af 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c @@ -1797,6 +1797,7 @@ PciProgramResizableBar ( {=0D EFI_PCI_IO_PROTOCOL *PciIo;=0D UINT64 Capabilities;=0D + UINT64 CapabilitiesMask;= =0D UINT32 Index;=0D UINT32 Offset;=0D INTN Bit;=0D @@ -1804,12 +1805,17 @@ PciProgramResizableBar ( PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Entries[PCI_MAX_B= AR];=0D =0D ASSERT (PciIoDevice->ResizableBarOffset !=3D 0);=0D -=0D + //=0D + // PCIE SPEC v6.0 section 7.8.6.3 Resizable BAR Control Register=0D + // Bits[13:8] BAR Size define 43(8 EB) as maximum=0D + //=0D + CapabilitiesMask =3D LShiftU64 (1, MIN (PcdGet8 (PcdPcieResizableMaxBarS= ize), 43) + 1) - 1;=0D DEBUG ((=0D DEBUG_INFO,=0D - " Programs Resizable BAR register, offset: 0x%08x, number: %d\n",=0D + " Programs Resizable BAR register, offset: 0x%08x, number: %d, PcdPc= ieResizableMaxBarSize: %d\n",=0D PciIoDevice->ResizableBarOffset,=0D - PciIoDevice->ResizableBarNumber=0D + PciIoDevice->ResizableBarNumber,=0D + PcdGet8 (PcdPcieResizableMaxBarSize)=0D ));=0D =0D if ((PciIoDevice->ResizableBarNumber > PCI_MAX_BAR) || (PciIoDevice->Res= izableBarNumber =3D=3D 0)) {=0D @@ -1853,9 +1859,22 @@ PciProgramResizableBar ( // Bit 0 is set: supports operating with the BAR sized to 1 MB=0D // Bit 1 is set: supports operating with the BAR sized to 2 MB=0D // Bit n is set: supports operating with the BAR sized to (2^n) MB=0D + // Platform may impose limitation on the BAR size it supports using Pc= dPcieResizableMaxBarSize.=0D //=0D Capabilities =3D LShiftU64 (Entries[Index].ResizableBarControl.Bits.Ba= rSizeCapability, 28)=0D | Entries[Index].ResizableBarCapability.Bits.BarSizeCap= ability;=0D + Capabilities &=3D CapabilitiesMask;=0D +=0D + if (Capabilities =3D=3D 0) {=0D + DEBUG ((=0D + DEBUG_ERROR,=0D + " WARNING: Resizable BAR Entry[%d] skip, Capabilities=3D0x%llx Cap= abilitiesMask=3D0x%llx\n",=0D + Index,=0D + Entries[Index].ResizableBarCapability.Bits.BarSizeCapability,=0D + CapabilitiesMask=0D + ));=0D + continue;=0D + }=0D =0D if (ResizableBarOp =3D=3D PciResizableBarMax) {=0D Bit =3D HighBitSet64 (Capabilities);=0D diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 1324b6d100..59fa506bd8 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -2264,6 +2264,11 @@ # @Prompt The value is use for Usb Network rate limiting supported.=0D gEfiMdeModulePkgTokenSpaceGuid.PcdUsbNetworkRateLimitingFactor|100|UINT3= 2|0x10000028=0D =0D + # This PCD set maximum size of all PCIE Resizable BARs=0D + # The max size equals to (2^PcdPcieResizableMaxBarSize) MB=0D + # @Prompt Maximum size of PCIE Resizable BARs=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableMaxBarSize|0x2B|UINT8|0x0= 0030009=0D +=0D [PcdsPatchableInModule]=0D ## Specify memory size with page number for PEI code when=0D # Loading Module at Fixed Address feature is enabled.=0D --=20 2.37.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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