From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id 460B49416E2 for ; Tue, 5 Nov 2024 10:31:01 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=a6cEZEkhWeGbFB8dQSAZkfyXN/vPrG8YtOgl4QclqqE=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20240830; t=1730802660; v=1; x=1731061859; b=ntt9lQG/0nfytRh0SRwOxl0em/n2zlWRqGOHp/C7as2kIXW8OrEw2WE49Msuxowt8+xWIqrU 0yYBS5z3AlMZP+89o2jw7AUGx/RIv3S6688z2snVIgroVH8/S36jdHQtR2+RiWT9OJ30dOQMxcE g1qF6khbMxzTLWn7lMp27/vmOrjL90NtD+570knBtEfeqTKld9IGBfnnxYQN1t7rxEfU54r697o jenZykYgJYUN3bAwws6YCg5tbU0NiZM6GyyQOqtyIflVwI6Tf65zOlcigZJ2kxl4h3pk+ijSsCl FRVfGjlYwwKKqHLzupCkRzzYeR/qd7kb25aAqa2OM9xIw== X-Received: by 127.0.0.2 with SMTP id l6d7YY7687511xEJaID3Rxnc; Tue, 05 Nov 2024 02:30:59 -0800 X-Received: from zg8tmja5ljk3lje4ms43mwaa.icoremail.net (zg8tmja5ljk3lje4ms43mwaa.icoremail.net [209.97.181.73]) by mx.groups.io with SMTP id smtpd.web11.14566.1730802647343452906 for ; Tue, 05 Nov 2024 02:30:49 -0800 X-Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-6 (Coremail) with SMTP id AQAAfwDHz_PT8yln7Xs3AA--.5575S2; Tue, 05 Nov 2024 18:30:43 +0800 (CST) X-Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAfwC3DXrM8ylnFotHAA--.15276S4; Tue, 05 Nov 2024 18:30:39 +0800 (CST) From: "Yuquan Wang" To: Jonathan.Cameron@Huawei.com, marcin.juszkiewicz@linaro.org, gaoliming@byosoft.com.cn, michael.d.kinney@intel.com, ardb+tianocore@kernel.org Cc: chenbaozi@phytium.com.cn, devel@edk2.groups.io, Yuquan Wang Subject: [edk2-devel] [RFC EDK2 PATCH v3 1/1] MdePkg/IndustryStandard: add definitions for CXL CEDT Date: Tue, 5 Nov 2024 18:30:25 +0800 Message-Id: <20241105103025.414786-2-wangyuquan1236@phytium.com.cn> In-Reply-To: <20241105103025.414786-1-wangyuquan1236@phytium.com.cn> References: <20241105103025.414786-1-wangyuquan1236@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAfwC3DXrM8ylnFotHAA--.15276S4 X-CM-SenderInfo: 5zdqw5pxtxt0arstlqxsk13x1xpou0fpof0/1tbiAQAAAWcpJZAFcAAAsO X-Coremail-Antispam: 1Uk129KBjvJXoWxXFWrtFy3JFWkuFWrCrykZrb_yoW7Jr45pF 4kAayYgayDJayfWrWSva15Zr1fCFs7Kw1DGF9Ivry3ZFWUtw1kWF4DAr1jqrykAr40k342 gFs2q34UuFnrC3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj DUYxn0WfASr-VFAU7a7-sFnT9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUU UUUUU Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Tue, 05 Nov 2024 02:30:49 -0800 Resent-From: wangyuquan1236@phytium.com.cn Reply-To: devel@edk2.groups.io,wangyuquan1236@phytium.com.cn List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 5BECe2wX6M5PynsBeIJzHsEXx7686176AA= Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240830 header.b="ntt9lQG/"; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io This adds #defines and struct typedefs for the various structure types in the CXL Early Discovery Table (CEDT). Signed-off-by: Yuquan Wang --- MdePkg/Include/IndustryStandard/Cxl20.h | 38 ++++++++++++++++++++ MdePkg/Include/IndustryStandard/Cxl30.h | 46 +++++++++++++++++++++++++ MdePkg/Include/IndustryStandard/Cxl31.h | 45 ++++++++++++++++++++++++ 3 files changed, 129 insertions(+) create mode 100644 MdePkg/Include/IndustryStandard/Cxl31.h diff --git a/MdePkg/Include/IndustryStandard/Cxl20.h b/MdePkg/Include/IndustryStandard/Cxl20.h index 574f78688180..9f9eb0bbaacc 100755 --- a/MdePkg/Include/IndustryStandard/Cxl20.h +++ b/MdePkg/Include/IndustryStandard/Cxl20.h @@ -14,6 +14,7 @@ #define CXL20_H_ #include +#include // // CXL DVSEC IDs @@ -102,6 +103,15 @@ #define CXL_MEM_DEVICE_MEDIA_STATUS_ERROR 0x2 #define CXL_MEM_DEVICE_MEDIA_STATUS_DISABLED 0x3 +/// +/// "CEDT" CXL Early Discovery Table +/// +#define CXL_EARLY_DISCOVERY_TABLE_SIGNATURE SIGNATURE_32 ('C', 'E', 'D', 'T') + +#define CXL_EARLY_DISCOVERY_TABLE_REVISION_01 0x1 + +#define CEDT_TYPE_CHBS 0x0 + // // Ensure proper structure formats // @@ -458,6 +468,34 @@ typedef union { UINT64 Uint64; } CXL_MEMORY_DEVICE_STATUS_REGISTER; +/// +/// CEDT header +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +} CXL_EARLY_DISCOVERY_TABLE; + +/// +/// Node header definition shared by all CEDT structure types +/// +typedef struct { + UINT8 Type; + UINT8 Reserved; + UINT16 Length; +} CEDT_STRUCTURE; + +/// +/// Definition for CXL Host Bridge Structure (CHBS) +/// +typedef struct { + CEDT_STRUCTURE Header; + UINT32 UID; + UINT32 CXLVersion; + UINT32 Reserved; + UINT64 Base; + UINT64 Length; +} CXL_HOST_BRIDGE_STRUCTURE; + #pragma pack() #endif diff --git a/MdePkg/Include/IndustryStandard/Cxl30.h b/MdePkg/Include/IndustryStandard/Cxl30.h index 7a9a6d69405d..f0125f8900aa 100644 --- a/MdePkg/Include/IndustryStandard/Cxl30.h +++ b/MdePkg/Include/IndustryStandard/Cxl30.h @@ -45,6 +45,13 @@ #define CXL_HDM_6_WAY_INTERLEAVING 0x9 #define CXL_HDM_12_WAY_INTERLEAVING 0xA +/// +/// "CEDT" CXL Early Discovery Table +/// +#define CEDT_TYPE_CFMWS 0x1 +#define CEDT_TYPE_CXIMS 0x2 +#define CEDT_TYPE_RDPAS 0x3 + // // Ensure proper structure formats // @@ -311,6 +318,45 @@ typedef struct { CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_STATUS TimeoutAndIsolationStatus; } CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CAPABILITY_STRUCTURE; +/// +/// Definition for CXL Fixed Memory Window Structure (CFMWS) +/// +typedef struct { + CEDT_STRUCTURE Header; + UINT32 Reserved; + UINT64 BaseHPA; + UINT64 WindowSize; + UINT8 InterleaveMembers; + UINT8 InterleaveArithmetic; + UINT16 Reserved1; + UINT32 Granularity; + UINT16 Restrictions; + UINT16 QtgId; + UINT32 TargetList[16]; +} CXL_FIXED_MEMORY_WINDOW_STRUCTURE; + +/// +/// Definition for CXL XOR Interleave Math Structure (CXIMS) +/// +typedef struct { + CEDT_STRUCTURE Header; + UINT16 Reserved; + UINT8 HBIG; + UINT8 NIB; + UINT64 XORMAPLIST[4]; +} CXL_XOR_INTERLEAVE_MATH_STRUCTURE; + +/// +/// Definition for RCEC Downstream Port Association Structure (RDPAS) +/// +typedef struct { + CEDT_STRUCTURE Header; + UINT16 SegmentNumber; + UINT16 BDF; + UINT8 ProtocolType; + UINT64 BaseAddress; +} RCEC_DOWNSTREAM_PORT_ASSOCIATION_STRUCTURE; + #pragma pack() #endif diff --git a/MdePkg/Include/IndustryStandard/Cxl31.h b/MdePkg/Include/IndustryStandard/Cxl31.h new file mode 100644 index 000000000000..4a62c971b045 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Cxl31.h @@ -0,0 +1,45 @@ +/** @file + CXL 3.1 definitions + + This file contains the register definitions and firmware interface based + on the Compute Express Link (CXL) Specification Revision 3.1. + + Copyright (c) 2024, Phytium Technology Co Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Reference(s): + - Compute Express Link (CXL) Specification Revision 3.1. + (https://computeexpresslink.org/cxl-specification/) + +**/ + +#ifndef CXL31_H_ +#define CXL31_H_ + +#include + +/// +/// "CEDT" CXL Early Discovery Table +/// +#define CXL_EARLY_DISCOVERY_TABLE_REVISION_02 0x2 + +#define CEDT_TYPE_CSDS 0x4 + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// Definition for CXL System Description Structure (CSDS) +/// +typedef struct { + CEDT_STRUCTURE Header; + UINT16 Capabilities; + UINT16 Reserved; +} CXL_DOWNSTREAM_PORT_ASSOCIATION_STRUCTURE; + +#pragma pack() + +#endif -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#120717): https://edk2.groups.io/g/devel/message/120717 Mute This Topic: https://groups.io/mt/109403424/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-