From: "Yuquan Wang" <wangyuquan1236@phytium.com.cn>
To: Jonathan.Cameron@Huawei.com, marcin.juszkiewicz@linaro.org,
ardb+tianocore@kernel.org, quic_llindhol@quicinc.com,
peter.maydell@linaro.org
Cc: chenbaozi@phytium.com.cn, devel@edk2.groups.io,
linux-cxl@vger.kernel.org, asa-dev@op-lists.linaro.org,
Yuquan Wang <wangyuquan1236@phytium.com.cn>
Subject: [edk2-devel] [RFC PATCH edk2-platforms v2 0/1] add basic support for CXL on sbsa-ref
Date: Tue, 5 Nov 2024 18:39:44 +0800 [thread overview]
Message-ID: <20241105103945.416494-1-wangyuquan1236@phytium.com.cn> (raw)
v1 -> v2:
- PCDs values about CXL exclusive MMIO32 & MMIO64 space
- CXL Bus range: 0xc0 ~ 0xff
- PCIE ecam space & Cxl ecam space
- CEDT format
RFC because
- Many contents are ported from Jonathan' patch on qemu virt design
- Bring plenty of PCDs values and modifying the original PCIE values
- Less experience and not particularly confident in ACPI area
This series leverages Jonathan's patches[1] to add acpi0016 & acpi0017 objects into the
previous DSDT table of sbsa-ref. Since the acpi0016 implementation model on qemu side is
the pxb-cxl, this cxl Bus would share ECAM sapce of PCIE Bus. Thus I divide some space
from Pcie Ecam to support cxl-related values.
To prevent breaking the original pcie mmio space, this adds exclusive mmio32 & mmio64
space for cxl host.
This defines the pcie bus range of cxl host is 0xc0 ~ 0xff, since the pxb-cxl-host as
well as cxl components on it would occupy the original pcie buses, the original pcie
ecam space should divided some range for pxb-cxl-host.
Based on the new CEDT definitions patch on edk2[2], this series adds a static Cedt.aslc to
support the [SBSA_CXL_HOST] & [SBSA_CXL_FIXED_WINDOW] space on sbsa-ref.
DSDT:
Device (CXL0)
{
Name (_HID, "ACPI0016" /* Compute Express Link Host Bridge */) // _HID: Hardware ID
Name (_CID, Package (0x02) // _CID: Compatible ID
{
EisaId ("PNP0A08") /* PCI Express Bus */,
EisaId ("PNP0A03") /* PCI Bus */
})
Name (_BBN, 0xC0) // _BBN: BIOS Bus Number
Name (_UID, One) // _UID: Unique ID
Name (_STR, Unicode ("pxb Device")) // _STR: Description String
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_PRT, Package (0x80) // _PRT: PCI Routing Table
{
Package (0x04)
{
0xFFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0xFFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0xFFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0xFFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0001FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0001FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0001FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0001FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0002FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0002FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0002FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0002FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0003FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0003FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0003FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0003FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0004FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0004FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0004FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0004FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0005FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0005FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0005FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0005FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0006FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0006FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0006FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0006FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0007FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0007FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0007FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0007FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0008FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0008FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0008FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0008FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0009FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0009FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0009FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0009FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x000AFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x000AFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x000AFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x000AFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x000BFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x000BFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x000BFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x000BFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x000CFFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x000CFFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x000CFFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x000CFFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x000DFFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x000DFFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x000DFFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x000DFFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x000EFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x000EFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x000EFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x000EFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x000FFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x000FFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x000FFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x000FFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0010FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0010FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0010FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0010FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0011FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0011FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0011FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0011FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0012FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0012FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0012FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0012FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0013FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0013FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0013FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0013FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0014FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0014FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0014FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0014FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0015FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0015FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0015FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0015FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0016FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0016FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0016FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0016FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0017FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0017FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0017FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0017FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0018FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0018FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0018FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0018FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0019FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0019FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0019FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0019FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x001AFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x001AFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x001AFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x001AFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x001BFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x001BFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x001BFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x001BFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x001CFFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x001CFFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x001CFFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x001CFFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x001DFFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x001DFFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x001DFFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x001DFFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x001EFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x001EFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x001EFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x001EFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x001FFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x001FFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x03,
GSI2,
Zero
}
})
Device (GSI0)
{
Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000023,
}
})
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000023,
}
})
Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
{
}
}
Device (GSI1)
{
Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
Name (_UID, One) // _UID: Unique ID
Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000024,
}
})
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000024,
}
})
Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
{
}
}
Device (GSI2)
{
Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
Name (_UID, 0x02) // _UID: Unique ID
Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000025,
}
})
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000025,
}
})
Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
{
}
}
Device (GSI3)
{
Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
Name (_UID, 0x03) // _UID: Unique ID
Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000026,
}
})
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000026,
}
})
Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
{
}
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000, // Granularity
0x60130000, // Range Minimum
0x6212FFFF, // Range Maximum
0x00000000, // Translation Offset
0x02000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000090000000000, // Range Minimum
0x00000900000FFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000000100000, // Length
,, , AddressRangeMemory, TypeStatic)
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x00C0, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0040, // Length
,, )
})
Device (RES0)
{
Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x00000000FC000000, // Range Minimum
0x00000000FFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000004000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
}
Name (SUPP, Zero)
Name (CTRL, Zero)
Name (SUPC, Zero)
Name (CTRC, Zero)
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
If (((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */) || (Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc") /* Unknown UUID */)))
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
Local0 = CDW3 /* \_SB_.CXL0._OSC.CDW3 */
Local0 &= 0x1F
If ((Arg1 != One))
{
CDW1 |= 0x08
}
If ((CDW3 != Local0))
{
CDW1 |= 0x10
}
SUPP = CDW2 /* \_SB_.CXL0._OSC.CDW2 */
CTRL = CDW3 /* \_SB_.CXL0._OSC.CDW3 */
CDW3 = Local0
If ((Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc") /* Unknown UUID */))
{
CreateDWordField (Arg3, 0x0C, CDW4)
CreateDWordField (Arg3, 0x10, CDW5)
SUPC = CDW4 /* \_SB_.CXL0._OSC.CDW4 */
CTRC = CDW5 /* \_SB_.CXL0._OSC.CDW5 */
CDW5 |= One
}
Return (Arg3)
}
Else
{
CDW1 |= 0x04
Return (Arg3)
}
}
}
CEDT:
[000h 0000 004h] Signature : "CEDT" [CXL Early Discovery Table]
[004h 0004 004h] Table Length : 000000A8
[008h 0008 001h] Revision : 01
[009h 0009 001h] Checksum : 50
[00Ah 0010 006h] Oem ID : "LINARO"
[010h 0016 008h] Oem Table ID : "SBSAQEMU"
[018h 0024 004h] Oem Revision : 20240625
[01Ch 0028 004h] Asl Compiler ID : "LNRO"
[020h 0032 004h] Asl Compiler Revision : 00000001
[024h 0036 001h] Subtable Type : 00 [CXL Host Bridge Structure]
[025h 0037 001h] Reserved : 00
[026h 0038 002h] Length : 0020
[028h 0040 004h] Associated host bridge : 00000001
[02Ch 0044 004h] Specification version : 00000001
[030h 0048 004h] Reserved : 00000000
[034h 0052 008h] Register base : 0000000060120000
[03Ch 0060 008h] Register length : 0000000000010000
[044h 0068 001h] Subtable Type : 01 [CXL Fixed Memory Window Structure]
[045h 0069 001h] Reserved : 00
[046h 0070 002h] Length : 0064
[048h 0072 004h] Reserved : 00000000
[04Ch 0076 008h] Window base address : 00000A0000000000
[054h 0084 008h] Window size : 0000010000000000
[05Ch 0092 001h] Interleave Members : 00
[05Dh 0093 001h] Interleave Arithmetic : 00
[05Eh 0094 002h] Reserved : 0000
[060h 0096 004h] Granularity : 00000000
[064h 0100 002h] Restrictions : 000F
[066h 0102 002h] QtgId : 0001
[068h 0104 004h] First Target : 00000001
Link:
[1]: https://lore.kernel.org/linux-cxl/20220616141950.23374-2-Jonathan.Cameron@huawei.com/
[2]: https://edk2.groups.io/g/devel/topic/rfc_edk2_patch_v3_0_1/109403423#
Yuquan Wang (1):
SbsaQemu: Support basic CXL enablement
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 23 +-
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 19 +
Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc | 69 +++
Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 401 +++++++++++++++++-
Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 2 +-
Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 34 +-
6 files changed, 537 insertions(+), 11 deletions(-)
create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc
--
2.34.1
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next reply other threads:[~2024-11-05 10:40 UTC|newest] Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-11-05 10:39 Yuquan Wang [this message] 2024-11-05 10:39 ` [edk2-devel] [RFC PATCH edk2-platforms v2 1/1] SbsaQemu: Support basic CXL enablement Yuquan Wang -- strict thread matches above, loose matches on Subject: below -- 2024-11-05 10:35 [edk2-devel] [RFC PATCH edk2-platforms v2 0/1] add basic support for CXL on sbsa-ref Yuquan Wang
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