From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id 89F48D80D75 for ; Tue, 12 Nov 2024 05:59:58 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=XQWR31WSxPHKlwn4THuxo32R+/7rIvlb3zzIf3cyKPA=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20240830; t=1731391198; v=1; x=1731650396; b=wv6ebIPmtdMkHOzN0CRGgRDP7dyv39WUQtgqAfu/LuY5w3bsYirmWEer0DmLcSrOs9VWL7oZ GOzJ41ZHsy31+CfhvCXHZjgbFCAhWo860uBh4MmbH8ELS3MxyotRuCUycWeIOHdQjw2BLhLYY2G vI23vqyjI2xPm+J0OuxtJyGr9Qq30UwO2oWUyZdFpFyPWn9ZIgxiOAMeHScaQWvnNZgqd6t9YZR 8EICnDzR6mwDDMBsBGdkcLSjudzDwWuf7pOQw8ya7UtyBVsqYB/5f8lU7wIt3wdYvtWBNg0amp3 9BQJH0UocLrKCdUIrxgtQ0wq8SqTrQdxF+F/llcQNh+IA== X-Received: by 127.0.0.2 with SMTP id A3o1YY7687511xVFspshTVX0; Mon, 11 Nov 2024 21:59:56 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mx.groups.io with SMTP id smtpd.web10.80278.1731391196367802123 for ; Mon, 11 Nov 2024 21:59:56 -0800 X-CSE-ConnectionGUID: lFmnWeQiSVy2CdzMnmv/RA== X-CSE-MsgGUID: tbrOwpkrQx644dTq+DddWw== X-IronPort-AV: E=McAfee;i="6700,10204,11253"; a="42589666" X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="42589666" X-Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Nov 2024 21:59:56 -0800 X-CSE-ConnectionGUID: 0q5qktX4TQqynS1Z+d1iyA== X-CSE-MsgGUID: AMdVD2h9S0uNhcDkUcz8xg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="118205125" X-Received: from shsse002.sh.intel.com ([10.239.132.247]) by fmviesa001.fm.intel.com with ESMTP; 11 Nov 2024 21:59:55 -0800 From: "Ning Feng via groups.io" To: devel@edk2.groups.io Cc: Ning Feng Subject: [edk2-devel] [PATCH] MedModulePkg/DxeIplPeim: Fix pagetable protection region in 5 level paging Date: Tue, 12 Nov 2024 00:59:44 -0500 Message-Id: <20241112055944.1820285-1-ning.feng@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Mon, 11 Nov 2024 21:59:56 -0800 Resent-From: ning.feng@intel.com Reply-To: devel@edk2.groups.io,ning.feng@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 0ANYWa3iSDLXOl5afyLFZII9x7686176AA= Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240830 header.b=wv6ebIPm; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=pass (policy=none) header.from=groups.io REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D4873 Currently the function does not cover the 5 level paging case. it will casued pagetable protection region set incorrectly. This patch do the enhancemant and with the patch protection region has been set correctly. Signed-off-by: Ning Feng --- .../Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 2 +- .../Core/DxeIplPeim/X64/VirtualMemory.c | 51 ++++++++++--------- .../Core/DxeIplPeim/X64/VirtualMemory.h | 15 +++--- .../UefiPayloadEntry/Ia32/DxeLoadFunc.c | 2 +- .../UefiPayloadEntry/X64/VirtualMemory.c | 45 ++++++++-------- .../UefiPayloadEntry/X64/VirtualMemory.h | 15 +++--- 6 files changed, 71 insertions(+), 59 deletions(-) diff --git a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c b/MdeModulePkg= /Core/DxeIplPeim/Ia32/DxeLoadFunc.c index 65e9bdc99e..60878b4c1a 100644 --- a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c +++ b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c @@ -166,7 +166,7 @@ Create4GPageTablesIa32Pae ( // Protect the page table by marking the memory used for page table to b= e=0D // read-only.=0D //=0D - EnablePageTableProtection ((UINTN)PageMap, FALSE);=0D + EnablePageTableProtection ((UINTN)PageMap, 3);=0D =0D return (UINTN)PageMap;=0D }=0D diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.c index df6196a41c..f02bdfe95d 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c @@ -485,14 +485,14 @@ Split1GPageTo2M ( =0D @param[in] PageTableBase Base address of page table (CR3).=0D @param[in] Address Start address of a page to be set as read-on= ly.=0D - @param[in] Level4Paging Level 4 paging flag.=0D + @param[in] LevelofPaging Level of paging.=0D =0D **/=0D VOID=0D SetPageTablePoolReadOnly (=0D IN UINTN PageTableBase,=0D IN EFI_PHYSICAL_ADDRESS Address,=0D - IN BOOLEAN Level4Paging=0D + IN UINT8 LevelofPaging=0D )=0D {=0D UINTN Index;=0D @@ -502,9 +502,9 @@ SetPageTablePoolReadOnly ( UINT64 *PageTable;=0D UINT64 *NewPageTable;=0D UINT64 PageAttr;=0D - UINT64 LevelSize[5];=0D - UINT64 LevelMask[5];=0D - UINTN LevelShift[5];=0D + UINT64 LevelSize[6];=0D + UINT64 LevelMask[6];=0D + UINTN LevelShift[6];=0D UINTN Level;=0D UINT64 PoolUnitSize;=0D =0D @@ -521,23 +521,26 @@ SetPageTablePoolReadOnly ( LevelShift[2] =3D PAGING_L2_ADDRESS_SHIFT;=0D LevelShift[3] =3D PAGING_L3_ADDRESS_SHIFT;=0D LevelShift[4] =3D PAGING_L4_ADDRESS_SHIFT;=0D + LevelShift[5] =3D PAGING_L5_ADDRESS_SHIFT;=0D =0D LevelMask[1] =3D PAGING_4K_ADDRESS_MASK_64;=0D LevelMask[2] =3D PAGING_2M_ADDRESS_MASK_64;=0D LevelMask[3] =3D PAGING_1G_ADDRESS_MASK_64;=0D - LevelMask[4] =3D PAGING_1G_ADDRESS_MASK_64;=0D + LevelMask[4] =3D PAGING_512G_ADDRESS_MASK_64;=0D + LevelMask[5] =3D PAGING_256T_ADDRESS_MASK_64;=0D =0D LevelSize[1] =3D SIZE_4KB;=0D LevelSize[2] =3D SIZE_2MB;=0D LevelSize[3] =3D SIZE_1GB;=0D LevelSize[4] =3D SIZE_512GB;=0D + LevelSize[5] =3D SIZE_256TB;=0D =0D AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &=0D PAGING_1G_ADDRESS_MASK_64;=0D PageTable =3D (UINT64 *)(UINTN)PageTableBase;=0D PoolUnitSize =3D PAGE_TABLE_POOL_UNIT_SIZE;=0D =0D - for (Level =3D (Level4Paging) ? 4 : 3; Level > 0; --Level) {=0D + for (Level =3D LevelofPaging; Level > 0; --Level) {=0D Index =3D ((UINTN)RShiftU64 (Address, LevelShift[Level]));=0D Index &=3D PAGING_PAE_INDEX_MASK;=0D =0D @@ -607,13 +610,13 @@ SetPageTablePoolReadOnly ( Prevent the memory pages used for page table from been overwritten.=0D =0D @param[in] PageTableBase Base address of page table (CR3).=0D - @param[in] Level4Paging Level 4 paging flag.=0D + @param[in] LevelofPaging Level of paging.=0D =0D **/=0D VOID=0D EnablePageTableProtection (=0D - IN UINTN PageTableBase,=0D - IN BOOLEAN Level4Paging=0D + IN UINTN PageTableBase,=0D + IN UINT8 LevelofPaging=0D )=0D {=0D PAGE_TABLE_POOL *HeadPool;=0D @@ -642,7 +645,7 @@ EnablePageTableProtection ( // protection to them one by one.=0D //=0D while (PoolSize > 0) {=0D - SetPageTablePoolReadOnly (PageTableBase, Address, Level4Paging);=0D + SetPageTablePoolReadOnly (PageTableBase, Address, LevelofPaging);=0D Address +=3D PAGE_TABLE_POOL_UNIT_SIZE;=0D PoolSize -=3D PAGE_TABLE_POOL_UNIT_SIZE;=0D }=0D @@ -696,7 +699,7 @@ CreateIdentityMappingPageTables ( UINTN TotalPagesNum;=0D UINTN BigPageAddress;=0D VOID *Hob;=0D - BOOLEAN Page5LevelEnabled;=0D + UINT8 LevelofPaging;=0D BOOLEAN Page1GSupport;=0D PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;=0D UINT64 AddressEncMask;=0D @@ -743,16 +746,16 @@ CreateIdentityMappingPageTables ( //=0D // If cpu has already run in 64bit long mode PEI, Page table Level in = DXE must align with previous level.=0D //=0D - Cr4.UintN =3D AsmReadCr4 ();=0D - Page5LevelEnabled =3D (Cr4.Bits.LA57 !=3D 0);=0D - if (Page5LevelEnabled) {=0D + Cr4.UintN =3D AsmReadCr4 ();=0D + LevelofPaging =3D (Cr4.Bits.LA57 =3D=3D 1) ? 5 : 4;=0D + if (LevelofPaging =3D=3D 5) {=0D ASSERT (PcdGetBool (PcdUse5LevelPageTable));=0D }=0D } else {=0D //=0D // If cpu runs in 32bit protected mode PEI, Page table Level in DXE is= decided by PCD and feature capability.=0D //=0D - Page5LevelEnabled =3D FALSE;=0D + LevelofPaging =3D 4;=0D if (PcdGetBool (PcdUse5LevelPageTable)) {=0D AsmCpuidEx (=0D CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,=0D @@ -763,12 +766,12 @@ CreateIdentityMappingPageTables ( NULL=0D );=0D if (EcxFlags.Bits.FiveLevelPage !=3D 0) {=0D - Page5LevelEnabled =3D TRUE;=0D + LevelofPaging =3D 5;=0D }=0D }=0D }=0D =0D - DEBUG ((DEBUG_INFO, "AddressBits=3D%u 5LevelPaging=3D%u 1GPage=3D%u\n", = PhysicalAddressBits, Page5LevelEnabled, Page1GSupport));=0D + DEBUG ((DEBUG_INFO, "AddressBits=3D%u LevelofPaging=3D%u 1GPage=3D%u\n",= PhysicalAddressBits, LevelofPaging, Page1GSupport));=0D =0D //=0D // IA-32e paging translates 48-bit linear addresses to 52-bit physical a= ddresses=0D @@ -776,7 +779,7 @@ CreateIdentityMappingPageTables ( // due to either unsupported by HW, or disabled by PCD.=0D //=0D ASSERT (PhysicalAddressBits <=3D 52);=0D - if (!Page5LevelEnabled && (PhysicalAddressBits > 48)) {=0D + if ((LevelofPaging !=3D 5) && (PhysicalAddressBits > 48)) {=0D PhysicalAddressBits =3D 48;=0D }=0D =0D @@ -811,7 +814,7 @@ CreateIdentityMappingPageTables ( //=0D // Substract the one page occupied by PML5 entries if 5-Level Paging is = disabled.=0D //=0D - if (!Page5LevelEnabled) {=0D + if (LevelofPaging !=3D 5) {=0D TotalPagesNum--;=0D }=0D =0D @@ -831,7 +834,7 @@ CreateIdentityMappingPageTables ( // By architecture only one PageMapLevel4 exists - so lets allocate stor= age for it.=0D //=0D PageMap =3D (VOID *)BigPageAddress;=0D - if (Page5LevelEnabled) {=0D + if (LevelofPaging =3D=3D 5) {=0D //=0D // By architecture only one PageMapLevel5 exists - so lets allocate st= orage for it.=0D //=0D @@ -853,7 +856,7 @@ CreateIdentityMappingPageTables ( PageMapLevel4Entry =3D (VOID *)BigPageAddress;=0D BigPageAddress +=3D SIZE_4KB;=0D =0D - if (Page5LevelEnabled) {=0D + if (LevelofPaging =3D=3D 5) {=0D //=0D // Make a PML5 Entry=0D //=0D @@ -947,7 +950,7 @@ CreateIdentityMappingPageTables ( ZeroMem (PageMapLevel4Entry, (512 - IndexOfPml4Entries) * sizeof (PAGE= _MAP_AND_DIRECTORY_POINTER));=0D }=0D =0D - if (Page5LevelEnabled) {=0D + if (LevelofPaging =3D=3D 5) {=0D Cr4.UintN =3D AsmReadCr4 ();=0D Cr4.Bits.LA57 =3D 1;=0D AsmWriteCr4 (Cr4.UintN);=0D @@ -961,7 +964,7 @@ CreateIdentityMappingPageTables ( // Protect the page table by marking the memory used for page table to b= e=0D // read-only.=0D //=0D - EnablePageTableProtection ((UINTN)PageMap, TRUE);=0D + EnablePageTableProtection ((UINTN)PageMap, LevelofPaging);=0D =0D //=0D // Set IA32_EFER.NXE if necessary.=0D diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.h index 616ebe42b0..ac5eb7282d 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h @@ -149,14 +149,17 @@ typedef union { =0D #define PAGING_PAE_INDEX_MASK 0x1FF=0D =0D -#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull=0D -#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull=0D -#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull=0D +#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull=0D +#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull=0D +#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull=0D +#define PAGING_512G_ADDRESS_MASK_64 0x000FF80000000000ull=0D +#define PAGING_256T_ADDRESS_MASK_64 0x000F800000000000ull=0D =0D #define PAGING_L1_ADDRESS_SHIFT 12=0D #define PAGING_L2_ADDRESS_SHIFT 21=0D #define PAGING_L3_ADDRESS_SHIFT 30=0D #define PAGING_L4_ADDRESS_SHIFT 39=0D +#define PAGING_L5_ADDRESS_SHIFT 48=0D =0D #define PAGING_PML4E_NUMBER 4=0D =0D @@ -293,13 +296,13 @@ IsNullDetectionEnabled ( Prevent the memory pages used for page table from been overwritten.=0D =0D @param[in] PageTableBase Base address of page table (CR3).=0D - @param[in] Level4Paging Level 4 paging flag.=0D + @param[in] LevelofPaging Level of paging.=0D =0D **/=0D VOID=0D EnablePageTableProtection (=0D - IN UINTN PageTableBase,=0D - IN BOOLEAN Level4Paging=0D + IN UINTN PageTableBase,=0D + IN UINT8 LevelofPaging=0D );=0D =0D /**=0D diff --git a/UefiPayloadPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c b/UefiPaylo= adPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c index cf9c03a9a8..6009232524 100644 --- a/UefiPayloadPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c +++ b/UefiPayloadPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c @@ -177,7 +177,7 @@ Create4GPageTablesIa32Pae ( // Protect the page table by marking the memory used for page table to b= e=0D // read-only.=0D //=0D - EnablePageTableProtection ((UINTN)PageMap, FALSE);=0D + EnablePageTableProtection ((UINTN)PageMap, 3);=0D =0D return (UINTN)PageMap;=0D }=0D diff --git a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c b/UefiPayl= oadPkg/UefiPayloadEntry/X64/VirtualMemory.c index 1899404b24..ad91ffbb4c 100644 --- a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c +++ b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c @@ -481,14 +481,14 @@ Split1GPageTo2M ( =0D @param[in] PageTableBase Base address of page table (CR3).=0D @param[in] Address Start address of a page to be set as read-on= ly.=0D - @param[in] Level4Paging Level 4 paging flag.=0D + @param[in] LevelofPaging Level of paging.=0D =0D **/=0D VOID=0D SetPageTablePoolReadOnly (=0D IN UINTN PageTableBase,=0D IN EFI_PHYSICAL_ADDRESS Address,=0D - IN BOOLEAN Level4Paging=0D + IN UINT8 LevelofPaging=0D )=0D {=0D UINTN Index;=0D @@ -498,9 +498,9 @@ SetPageTablePoolReadOnly ( UINT64 *PageTable;=0D UINT64 *NewPageTable;=0D UINT64 PageAttr;=0D - UINT64 LevelSize[5];=0D - UINT64 LevelMask[5];=0D - UINTN LevelShift[5];=0D + UINT64 LevelSize[6];=0D + UINT64 LevelMask[6];=0D + UINTN LevelShift[6];=0D UINTN Level;=0D UINT64 PoolUnitSize;=0D =0D @@ -517,23 +517,26 @@ SetPageTablePoolReadOnly ( LevelShift[2] =3D PAGING_L2_ADDRESS_SHIFT;=0D LevelShift[3] =3D PAGING_L3_ADDRESS_SHIFT;=0D LevelShift[4] =3D PAGING_L4_ADDRESS_SHIFT;=0D + LevelShift[5] =3D PAGING_L5_ADDRESS_SHIFT;=0D =0D LevelMask[1] =3D PAGING_4K_ADDRESS_MASK_64;=0D LevelMask[2] =3D PAGING_2M_ADDRESS_MASK_64;=0D LevelMask[3] =3D PAGING_1G_ADDRESS_MASK_64;=0D - LevelMask[4] =3D PAGING_1G_ADDRESS_MASK_64;=0D + LevelMask[4] =3D PAGING_512G_ADDRESS_MASK_64;=0D + LevelMask[5] =3D PAGING_256T_ADDRESS_MASK_64;=0D =0D LevelSize[1] =3D SIZE_4KB;=0D LevelSize[2] =3D SIZE_2MB;=0D LevelSize[3] =3D SIZE_1GB;=0D LevelSize[4] =3D SIZE_512GB;=0D + LevelSize[5] =3D SIZE_256TB;=0D =0D AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &=0D PAGING_1G_ADDRESS_MASK_64;=0D PageTable =3D (UINT64 *)(UINTN)PageTableBase;=0D PoolUnitSize =3D PAGE_TABLE_POOL_UNIT_SIZE;=0D =0D - for (Level =3D (Level4Paging) ? 4 : 3; Level > 0; --Level) {=0D + for (Level =3D LevelofPaging; Level > 0; --Level) {=0D Index =3D ((UINTN)RShiftU64 (Address, LevelShift[Level]));=0D Index &=3D PAGING_PAE_INDEX_MASK;=0D =0D @@ -603,13 +606,13 @@ SetPageTablePoolReadOnly ( Prevent the memory pages used for page table from been overwritten.=0D =0D @param[in] PageTableBase Base address of page table (CR3).=0D - @param[in] Level4Paging Level 4 paging flag.=0D + @param[in] LevelofPaging Level of paging.=0D =0D **/=0D VOID=0D EnablePageTableProtection (=0D - IN UINTN PageTableBase,=0D - IN BOOLEAN Level4Paging=0D + IN UINTN PageTableBase,=0D + IN UINT8 LevelofPaging=0D )=0D {=0D PAGE_TABLE_POOL *HeadPool;=0D @@ -638,7 +641,7 @@ EnablePageTableProtection ( // protection to them one by one.=0D //=0D while (PoolSize > 0) {=0D - SetPageTablePoolReadOnly (PageTableBase, Address, Level4Paging);=0D + SetPageTablePoolReadOnly (PageTableBase, Address, LevelofPaging);=0D Address +=3D PAGE_TABLE_POOL_UNIT_SIZE;=0D PoolSize -=3D PAGE_TABLE_POOL_UNIT_SIZE;=0D }=0D @@ -691,7 +694,7 @@ CreateIdentityMappingPageTables ( UINTN TotalPagesNum;=0D UINTN BigPageAddress;=0D VOID *Hob;=0D - BOOLEAN Enable5LevelPaging;=0D + UINT8 LevelofPaging;=0D BOOLEAN Page1GSupport;=0D PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;=0D UINT64 AddressEncMask;=0D @@ -740,10 +743,10 @@ CreateIdentityMappingPageTables ( // below logic inherits the 5-level paging setting from bootloader in IA= -32e mode=0D // and uses 4-level paging in legacy protected mode.=0D //=0D - Cr4.UintN =3D AsmReadCr4 ();=0D - Enable5LevelPaging =3D (BOOLEAN)(Cr4.Bits.LA57 =3D=3D 1);=0D + Cr4.UintN =3D AsmReadCr4 ();=0D + LevelofPaging =3D (Cr4.Bits.LA57 =3D=3D 1) ? 5 : 4;=0D =0D - DEBUG ((DEBUG_INFO, "PayloadEntry: AddressBits=3D%u 5LevelPaging=3D%u 1G= Page=3D%u\n", PhysicalAddressBits, Enable5LevelPaging, Page1GSupport));=0D + DEBUG ((DEBUG_INFO, "PayloadEntry: AddressBits=3D%u LevelofPaging=3D%u 1= GPage=3D%u\n", PhysicalAddressBits, LevelofPaging, Page1GSupport));=0D =0D //=0D // IA-32e paging translates 48-bit linear addresses to 52-bit physical a= ddresses=0D @@ -751,7 +754,7 @@ CreateIdentityMappingPageTables ( // due to either unsupported by HW, or disabled by PCD.=0D //=0D ASSERT (PhysicalAddressBits <=3D 52);=0D - if (!Enable5LevelPaging && (PhysicalAddressBits > 48)) {=0D + if ((LevelofPaging !=3D 5) && (PhysicalAddressBits > 48)) {=0D PhysicalAddressBits =3D 48;=0D }=0D =0D @@ -786,7 +789,7 @@ CreateIdentityMappingPageTables ( //=0D // Substract the one page occupied by PML5 entries if 5-Level Paging is = disabled.=0D //=0D - if (!Enable5LevelPaging) {=0D + if (LevelofPaging !=3D 5) {=0D TotalPagesNum--;=0D }=0D =0D @@ -806,7 +809,7 @@ CreateIdentityMappingPageTables ( // By architecture only one PageMapLevel4 exists - so lets allocate stor= age for it.=0D //=0D PageMap =3D (VOID *)BigPageAddress;=0D - if (Enable5LevelPaging) {=0D + if (LevelofPaging =3D=3D 5) {=0D //=0D // By architecture only one PageMapLevel5 exists - so lets allocate st= orage for it.=0D //=0D @@ -828,7 +831,7 @@ CreateIdentityMappingPageTables ( PageMapLevel4Entry =3D (VOID *)BigPageAddress;=0D BigPageAddress +=3D SIZE_4KB;=0D =0D - if (Enable5LevelPaging) {=0D + if (LevelofPaging =3D=3D 5) {=0D //=0D // Make a PML5 Entry=0D //=0D @@ -922,7 +925,7 @@ CreateIdentityMappingPageTables ( ZeroMem (PageMapLevel4Entry, (512 - IndexOfPml4Entries) * sizeof (PAGE= _MAP_AND_DIRECTORY_POINTER));=0D }=0D =0D - if (Enable5LevelPaging) {=0D + if (LevelofPaging =3D=3D 5) {=0D //=0D // For the PML5 entries we are not using fill in a null entry.=0D //=0D @@ -933,7 +936,7 @@ CreateIdentityMappingPageTables ( // Protect the page table by marking the memory used for page table to b= e=0D // read-only.=0D //=0D - EnablePageTableProtection ((UINTN)PageMap, TRUE);=0D + EnablePageTableProtection ((UINTN)PageMap, LevelofPaging);=0D =0D //=0D // Set IA32_EFER.NXE if necessary.=0D diff --git a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.h b/UefiPayl= oadPkg/UefiPayloadEntry/X64/VirtualMemory.h index 616ebe42b0..ac5eb7282d 100644 --- a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.h +++ b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.h @@ -149,14 +149,17 @@ typedef union { =0D #define PAGING_PAE_INDEX_MASK 0x1FF=0D =0D -#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull=0D -#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull=0D -#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull=0D +#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull=0D +#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull=0D +#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull=0D +#define PAGING_512G_ADDRESS_MASK_64 0x000FF80000000000ull=0D +#define PAGING_256T_ADDRESS_MASK_64 0x000F800000000000ull=0D =0D #define PAGING_L1_ADDRESS_SHIFT 12=0D #define PAGING_L2_ADDRESS_SHIFT 21=0D #define PAGING_L3_ADDRESS_SHIFT 30=0D #define PAGING_L4_ADDRESS_SHIFT 39=0D +#define PAGING_L5_ADDRESS_SHIFT 48=0D =0D #define PAGING_PML4E_NUMBER 4=0D =0D @@ -293,13 +296,13 @@ IsNullDetectionEnabled ( Prevent the memory pages used for page table from been overwritten.=0D =0D @param[in] PageTableBase Base address of page table (CR3).=0D - @param[in] Level4Paging Level 4 paging flag.=0D + @param[in] LevelofPaging Level of paging.=0D =0D **/=0D VOID=0D EnablePageTableProtection (=0D - IN UINTN PageTableBase,=0D - IN BOOLEAN Level4Paging=0D + IN UINTN PageTableBase,=0D + IN UINT8 LevelofPaging=0D );=0D =0D /**=0D --=20 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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