From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id 6BD3F740035 for ; Wed, 27 Nov 2024 09:13:05 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=C+/IysrbqN9CJbKK9OeLkEguS9vg51I7/MCPcegRrYI=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20240830; t=1732698785; v=1; x=1732957983; b=h4UM9YHE5YY6R8mXQ8UqsC3ii5sU8lS7R7kQhR9tGLm8wG1O6ZmH+ZCdWI7SHw/J+4VFiNWS 6gpbOmXAkctkgV8RhOoaSJBMKJM83MsXHqRDF6jpAnpp1JDD/XxZlN3bzo+3oRw/NhigjUgyJeD vU4TTsuW0A9rOSS6YwZ1iW2ZE1bUP7u+fiJzBwK9Y7Fa+5MozAqxxH4Rs15AOmoeoKGfxs77DVL vUbU2bSKOiINYQy1IdCIU0tosSeB1iAWGJ0aGxBIzCx4UuT+35vycWSPAQqQFlXR4zy0A4vEZD8 jbezqlObV+77+aZbNqpPzSOKe64SlWoGXY5SngN/HXHnA== X-Received: by 127.0.0.2 with SMTP id 5BWoYY7687511xiX5Cdfljq6; Wed, 27 Nov 2024 01:13:03 -0800 X-Received: from sgoci-sdnproxy-4.icoremail.net (sgoci-sdnproxy-4.icoremail.net [129.150.39.64]) by mx.groups.io with SMTP id smtpd.web11.68124.1732698782622759208 for ; Wed, 27 Nov 2024 01:13:03 -0800 X-Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-7 (Coremail) with SMTP id AQAAfwBXT6qa4kZnjJDjBw--.49374S2; Wed, 27 Nov 2024 17:12:58 +0800 (CST) X-Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAfwCn_nqR4kZnVcRcAA--.11074S4; Wed, 27 Nov 2024 17:12:52 +0800 (CST) From: "Yuquan Wang" To: AbdulLateef.Attar@amd.com, gaoliming@byosoft.com.cn, michael.d.kinney@intel.com, zhiguang.liu@intel.com Cc: Jonathan.Cameron@Huawei.com, marcin.juszkiewicz@linaro.org, chenbaozi@phytium.com.cn, devel@edk2.groups.io, linux-cxl@vger.kernel.org, Yuquan Wang Subject: [edk2-devel] [RFC EDK2 PATCH v5 1/1] MdePkg/IndustryStandard: add definitions for CXL CEDT Date: Wed, 27 Nov 2024 17:12:29 +0800 Message-Id: <20241127091229.112833-2-wangyuquan1236@phytium.com.cn> In-Reply-To: <20241127091229.112833-1-wangyuquan1236@phytium.com.cn> References: <20241127091229.112833-1-wangyuquan1236@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAfwCn_nqR4kZnVcRcAA--.11074S4 X-CM-SenderInfo: 5zdqw5pxtxt0arstlqxsk13x1xpou0fpof0/1tbiAQACAWdGJokDzwAAsA X-Coremail-Antispam: 1Uk129KBjvJXoW3GFWDWw18Kw4rZF18Xr4Utwb_yoW7tr4kpF n5AayYga98JFy3u3yfZa1F9r1fuFs7Gw1DGF9xZrya9FWUtwn7uFs8Ar1UXrykAr4UC347 WF42q3yru3W7C3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj DUYxn0WfASr-VFAU7a7-sFnT9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUU UUUUU Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Wed, 27 Nov 2024 01:13:03 -0800 Resent-From: wangyuquan1236@phytium.com.cn Reply-To: devel@edk2.groups.io,wangyuquan1236@phytium.com.cn List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: DrBl8xYwUMfSupLSrTFQOrbEx7686176AA= Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240830 header.b=h4UM9YHE; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io This adds #defines and struct typedefs for the various structure types in the CXL Early Discovery Table (CEDT). Signed-off-by: Yuquan Wang --- MdePkg/Include/IndustryStandard/Cxl20.h | 41 +++++++++++++++++ MdePkg/Include/IndustryStandard/Cxl30.h | 59 +++++++++++++++++++++++++ MdePkg/Include/IndustryStandard/Cxl31.h | 47 ++++++++++++++++++++ 3 files changed, 147 insertions(+) create mode 100644 MdePkg/Include/IndustryStandard/Cxl31.h diff --git a/MdePkg/Include/IndustryStandard/Cxl20.h b/MdePkg/Include/IndustryStandard/Cxl20.h index 574f78688180..ae8e4fab9e7c 100755 --- a/MdePkg/Include/IndustryStandard/Cxl20.h +++ b/MdePkg/Include/IndustryStandard/Cxl20.h @@ -14,6 +14,7 @@ #define CXL20_H_ #include +#include // // CXL DVSEC IDs @@ -102,6 +103,16 @@ #define CXL_MEM_DEVICE_MEDIA_STATUS_ERROR 0x2 #define CXL_MEM_DEVICE_MEDIA_STATUS_DISABLED 0x3 +// +// "CEDT" CXL Early Discovery Table +// Compute Express Link Specification Revision 2.0 - Chapter 9.14.1 +// +#define CXL_EARLY_DISCOVERY_TABLE_SIGNATURE SIGNATURE_32 ('C', 'E', 'D', 'T') + +#define CXL_EARLY_DISCOVERY_TABLE_REVISION_01 0x1 + +#define CEDT_TYPE_CHBS 0x0 + // // Ensure proper structure formats // @@ -458,6 +469,36 @@ typedef union { UINT64 Uint64; } CXL_MEMORY_DEVICE_STATUS_REGISTER; +// +// CEDT header +// Compute Express Link Specification Revision 2.0 - Chapter 9.14.1.1 +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +} CXL_EARLY_DISCOVERY_TABLE; + +// +// Node header definition shared by all CEDT structure types +// +typedef struct { + UINT8 Type; + UINT8 Reserved; + UINT16 Length; +} CEDT_STRUCTURE; + +// +// Definition for CXL Host Bridge Structure (CHBS) +// Compute Express Link Specification Revision 2.0 - Chapter 9.14.1.2 +// +typedef struct { + CEDT_STRUCTURE Header; + UINT32 Uid; + UINT32 CxlVersion; + UINT32 Reserved; + UINT64 Base; + UINT64 Length; +} CXL_HOST_BRIDGE_STRUCTURE; + #pragma pack() #endif diff --git a/MdePkg/Include/IndustryStandard/Cxl30.h b/MdePkg/Include/IndustryStandard/Cxl30.h index 7a9a6d69405d..27b20ab8198f 100644 --- a/MdePkg/Include/IndustryStandard/Cxl30.h +++ b/MdePkg/Include/IndustryStandard/Cxl30.h @@ -45,6 +45,14 @@ #define CXL_HDM_6_WAY_INTERLEAVING 0x9 #define CXL_HDM_12_WAY_INTERLEAVING 0xA +// +// "CEDT" CXL Early Discovery Table +// Compute Express Link Specification Revision 3.0 - Chapter 9.17.1 +// +#define CEDT_TYPE_CFMWS 0x1 +#define CEDT_TYPE_CXIMS 0x2 +#define CEDT_TYPE_RDPAS 0x3 + // // Ensure proper structure formats // @@ -311,6 +319,57 @@ typedef struct { CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_STATUS TimeoutAndIsolationStatus; } CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CAPABILITY_STRUCTURE; +// +// Definition for CXL Fixed Memory Window Structure (CFMWS) +// Compute Express Link Specification Revision 3.0 - Chapter 9.17.1.3 +// +// The number of entries in TargetList (Interleave Target List) shall +// match the Number of Interleave Ways (NIW). The current maximum is 16. +// +typedef struct { + CEDT_STRUCTURE Header; + UINT32 Reserved; + UINT64 BaseHpa; + UINT64 WindowSize; + UINT8 EncodedInterleaveWays; + UINT8 InterleaveArithmetic; + UINT16 Reserved1; + UINT32 Granularity; + UINT16 Restrictions; + UINT16 QtgId; + UINT32 TargetList[16]; +} CXL_FIXED_MEMORY_WINDOW_STRUCTURE; + +// +// Definition for CXL XOR Interleave Math Structure (CXIMS) +// Compute Express Link Specification Revision 3.0 - Chapter 9.17.1.4 +// +// The number of entries in XORMAPList depends on NIB. 4 is the current +// maximum for 16-way interleaving. +// +typedef struct { + CEDT_STRUCTURE Header; + UINT16 Reserved; + UINT8 HBIG; + UINT8 NIB; + UINT64 XORMAPList[4]; +} CXL_XOR_INTERLEAVE_MATH_STRUCTURE; + +// +// Definition for RCEC Downstream Port Association Structure (RDPAS) +// Compute Express Link Specification Revision 3.0 - Chapter 9.17.1.5 +// +// The errata released at CXL 3.2 fixed that RCEC BDF field overlaps +// Protocol Type field. +// +typedef struct { + CEDT_STRUCTURE Header; + UINT16 SegmentNumber; + UINT16 Bdf; + UINT64 BaseAddress; + UINT8 ProtocolType; +} RCEC_DOWNSTREAM_PORT_ASSOCIATION_STRUCTURE; + #pragma pack() #endif diff --git a/MdePkg/Include/IndustryStandard/Cxl31.h b/MdePkg/Include/IndustryStandard/Cxl31.h new file mode 100644 index 000000000000..768a9e9fafef --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Cxl31.h @@ -0,0 +1,47 @@ +/** @file + CXL 3.1 definitions + + This file contains the register definitions and firmware interface based + on the Compute Express Link (CXL) Specification Revision 3.1. + + Copyright (c) 2024, Phytium Technology Co Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Reference(s): + - Compute Express Link (CXL) Specification Revision 3.1. + (https://computeexpresslink.org/cxl-specification/) + +**/ + +#ifndef CXL31_H_ +#define CXL31_H_ + +#include + +// +// "CEDT" CXL Early Discovery Table +// Compute Express Link Specification Revision 3.1 - Chapter 9.18.1 +// +#define CXL_EARLY_DISCOVERY_TABLE_REVISION_02 0x2 + +#define CEDT_TYPE_CSDS 0x4 + +// +// Ensure proper structure formats +// +#pragma pack(1) + +// +// Definition for CXL System Description Structure (CSDS) +// Compute Express Link Specification Revision 3.1 - Chapter 9.18.6 +// +typedef struct { + CEDT_STRUCTURE Header; + UINT16 Capabilities; + UINT16 Reserved; +} CXL_DOWNSTREAM_PORT_ASSOCIATION_STRUCTURE; + +#pragma pack() + +#endif -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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