From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.101.70; helo=foss.arm.com; envelope-from=marc.zyngier@arm.com; receiver=edk2-devel@lists.01.org Received: from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by ml01.01.org (Postfix) with ESMTP id 84574223972AF for ; Tue, 6 Feb 2018 06:50:19 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C9F401435; Tue, 6 Feb 2018 06:56:01 -0800 (PST) Received: from [10.1.207.62] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 307DE3F53D; Tue, 6 Feb 2018 06:56:01 -0800 (PST) To: Ard Biesheuvel , edk2-devel@lists.01.org, leif.lindholm@linaro.org References: <20180206120416.17462-1-ard.biesheuvel@linaro.org> From: Marc Zyngier Organization: ARM Ltd Message-ID: <20bc6e59-61a2-3cfc-20b9-010b8e7eb8f8@arm.com> Date: Tue, 6 Feb 2018 14:55:58 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <20180206120416.17462-1-ard.biesheuvel@linaro.org> Subject: Re: [PATCH] ArmPkg/Gic: force GIC driver to run before CPU arch protocol driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Feb 2018 14:50:19 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit On 06/02/18 12:04, Ard Biesheuvel wrote: > Currently, the GIC driver has a static dependency on the CPU arch protocol > driver, so it can register its IRQ handler at init time. This means there > is a window between dispatch of the CPU driver and dispatch of the GIC > driver where any unexpected GIC state may trigger an interrupt which we > are not set up to handle yet. Note that this is even the case if we enter > UEFI with interrupts disabled at the CPU, given that any TPL manipulation > involving TPL_HIGH_LEVEL will unconditionally enable IRQs at the CPU side > regardless of whether they were enabled to begin with (but only as soon as > the CPU arch protocol is actually installed) > > So let's reorder the GIC driver with the CPU driver, and let it run its > initialization that puts the GIC into a known state before enabling > interrupts. Move its installation of its IRQ handler to a protocol notify > callback on the CPU arch protocol so that it runs as soon as it becomes > available. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > > This fixes an issue observed with GICv3 guests running under KVM. This fixes the problem I was seeing, so here's my: Tested-by: Marc Zyngier Thanks a lot Ard! M. -- Jazz is not dead. It just smells funny...