* [PATCH v2 0/3] Enable CCIX port as PCIe root host on N1SDP
@ 2021-11-23 12:26 Khasim Mohammed
2021-11-23 12:26 ` [PATCH v2 1/3] Silicon/ARM/NeoverseN1Soc: Update PciExpressLib to enable CCIX port Khasim Mohammed
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Khasim Mohammed @ 2021-11-23 12:26 UTC (permalink / raw)
To: devel; +Cc: nd, Khasim Syed Mohammed
The patch series enables CCIX port as PCIe root on N1SDP.
V2:
- Removed few PCDs entries that were not used.
- Migrated to latest version edk2-platform and validated the patches.
V1:
- The PciExpressLib is updated to validate the PCIe addresses
and introducing corresponding PCD entries.
- A custom PCI Segment library is adapted from SynQuacerPciSegmentLib
and ported for N1Sdp.
- The root complex node info in PciHostBridge library is updated to
include the CCIX port information.
The changes can be seen at:
https://github.com/khasim/edk2-platforms-n1sdp/tree/n1sdp-ccix-root
Khasim Syed Mohammed (3):
Silicon/ARM/NeoverseN1Soc: Update PciExpressLib to enable CCIX port
Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library
Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support
.../ConfigurationManagerDxe.inf | 3 +-
Platform/ARM/N1Sdp/N1SdpPlatform.dec | 3 -
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 3 +-
.../PciExpressLib.c | 127 +-
.../PciExpressLib.inf | 7 +-
.../PciHostBridgeLib/PciHostBridgeLib.c | 71 +-
.../PciHostBridgeLib/PciHostBridgeLib.inf | 11 +-
.../Library/PciSegmentLib/PciSegmentLib.c | 1425 +++++++++++++++++
.../Library/PciSegmentLib/PciSegmentLib.inf | 35 +
.../Library/PlatformLib/PlatformLib.inf | 1 +
.../Library/PlatformLib/PlatformLibMem.c | 4 +-
Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 5 +-
12 files changed, 1635 insertions(+), 60 deletions(-)
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf
--
2.17.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v2 1/3] Silicon/ARM/NeoverseN1Soc: Update PciExpressLib to enable CCIX port 2021-11-23 12:26 [PATCH v2 0/3] Enable CCIX port as PCIe root host on N1SDP Khasim Mohammed @ 2021-11-23 12:26 ` Khasim Mohammed 2021-11-30 17:10 ` [edk2-devel] " PierreGondois 2021-11-23 12:26 ` [PATCH v2 2/3] Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library Khasim Mohammed 2021-11-23 12:26 ` [PATCH v2 3/3] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support Khasim Mohammed 2 siblings, 1 reply; 8+ messages in thread From: Khasim Mohammed @ 2021-11-23 12:26 UTC (permalink / raw) To: devel; +Cc: nd, Khasim Syed Mohammed, Deepak Pandey Update the PciExpressLib to enable CCIX port as PCIe root host by validating the PCIe addresses and introducing corresponding PCD entries. Change-Id: I0d1167b86e53a3781f59c4d68a3b2e61add4317e Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com> Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com> --- .../PciExpressLib.c | 127 ++++++++++++------ .../PciExpressLib.inf | 7 +- Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 5 +- 3 files changed, 94 insertions(+), 45 deletions(-) diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c index bb0246b4a9..3abe0a2d6b 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c +++ b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c @@ -20,7 +20,7 @@ The description of the workarounds included for these limitations can be found in the comments below. - Copyright (c) 2020, ARM Limited. All rights reserved. + Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent @@ -36,15 +36,29 @@ #include <Library/PcdLib.h> #include <NeoverseN1Soc.h> +#define BUS_OFFSET 20 +#define DEV_OFFSET 15 +#define FUNC_OFFSET 12 +#define REG_OFFSET 4096 + /** - Assert the validity of a PCI address. A valid PCI address should contain 1's - only in the low 28 bits. + Assert the validity of a PCI address. A valid PCI address should contain 1's. @param A The address to validate. **/ #define ASSERT_INVALID_PCI_ADDRESS(A) \ - ASSERT (((A) & ~0xfffffff) == 0) + ASSERT (((A) & ~0xffffffff) == 0) + +#define EFI_PCIE_ADDRESS(bus, dev, func, reg) \ + (UINT64) ( \ + (((UINTN) bus) << BUS_OFFSET) | \ + (((UINTN) dev) << DEV_OFFSET) | \ + (((UINTN) func) << FUNC_OFFSET) | \ + (((UINTN) (reg)) < REG_OFFSET ? \ + ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32)))) + +#define GET_PCIE_BASE_ADDRESS(Address) (Address & 0xF8000000) /* Root port Entry, BDF Entries Count */ #define BDF_TABLE_ENTRY_SIZE 4 @@ -53,6 +67,7 @@ /* BDF table offsets for PCIe */ #define PCIE_BDF_TABLE_OFFSET 0 +#define CCIX_BDF_TABLE_OFFSET (16 * 1024) #define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F) #define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F) @@ -113,49 +128,64 @@ PciExpressRegisterForRuntimeAccess ( } /** - Check if the requested PCI address can be safely accessed. + Check if the requested PCI address is a valid BDF address. - SCP performs the initial bus scan, prepares a table of valid BDF addresses - and shares them through non-trusted SRAM. This function validates if the - requested PCI address belongs to a valid BDF by checking the table of valid - entries. If not, this function will return false. This is a workaround to - avoid bus fault that occurs when accessing unavailable PCI device due to - hardware bug. + SCP performs the initial bus scan and prepares a table of valid BDF addresses + and shares them through non-trusted SRAM. This function validates if the PCI + address from any PCI request falls within the table of valid entries. If not, + this function will return 0xFFFFFFFF. This is a workaround to avoid bus fault + that happens when accessing unavailable PCI device due to RTL bug. @param Address The address that encodes the PCI Bus, Device, Function and Register. - @return TRUE BDF can be accessed, valid. - @return FALSE BDF should not be accessed, invalid. + @return The base address of PCI Express. **/ STATIC -BOOLEAN +UINTN IsBdfValid ( - IN UINTN Address + IN UINTN Address ) { + UINT8 Bus; + UINT8 Device; + UINT8 Function; UINTN BdfCount; UINTN BdfValue; - UINTN BdfEntry; UINTN Count; UINTN TableBase; - UINTN ConfigBase; + UINTN PciAddress; + + Bus = GET_BUS_NUM (Address); + Device = GET_DEV_NUM (Address); + Function = GET_FUNC_NUM (Address); + + PciAddress = EFI_PCIE_ADDRESS (Bus, Device, Function, 0); + + if (GET_PCIE_BASE_ADDRESS (Address) == + FixedPcdGet64 (PcdPcieExpressBaseAddress)) { + TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFSET; + } else { + TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + CCIX_BDF_TABLE_OFFSET; + } - ConfigBase = Address & ~0xFFF; - TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFSET; BdfCount = MmioRead32 (TableBase + BDF_TABLE_ENTRY_SIZE); - BdfEntry = TableBase + BDF_TABLE_HEADER_SIZE; - - /* Skip the header & check remaining entry */ - for (Count = 0; Count < BdfCount; Count++, BdfEntry += BDF_TABLE_ENTRY_SIZE) { - BdfValue = MmioRead32 (BdfEntry); - if (BdfValue == ConfigBase) { - return TRUE; - } + + /* Start from the second entry */ + for (Count = BDF_TABLE_HEADER_COUNT; + Count < (BdfCount + BDF_TABLE_HEADER_COUNT); + Count++) { + BdfValue = MmioRead32 (TableBase + (Count * BDF_TABLE_ENTRY_SIZE)); + if (BdfValue == PciAddress) + break; } - return FALSE; + if (Count == (BdfCount + BDF_TABLE_HEADER_COUNT)) { + return mDummyConfigData; + } else { + return PciAddress; + } } /** @@ -186,20 +216,35 @@ GetPciExpressAddress ( IN UINTN Address ) { - UINT8 Bus, Device, Function; - UINTN ConfigAddress; - - Bus = GET_BUS_NUM (Address); - Device = GET_DEV_NUM (Address); + UINT8 Bus; + UINT8 Device; + UINT8 Function; + UINT16 Register; + UINTN ConfigAddress; + + // Get the EFI notation + Bus = GET_BUS_NUM (Address); + Device = GET_DEV_NUM (Address); Function = GET_FUNC_NUM (Address); - - if ((Bus == 0) && (Device == 0) && (Function == 0)) { - ConfigAddress = PcdGet32 (PcdPcieRootPortConfigBaseAddress) + Address; - } else { - ConfigAddress = PcdGet64 (PcdPciExpressBaseAddress) + Address; - if (!IsBdfValid(Address)) { - ConfigAddress = (UINTN)&mDummyConfigData; - } + Register = GET_REG_NUM (Address); + + ConfigAddress = (UINTN) + ((GET_PCIE_BASE_ADDRESS (Address) == + FixedPcdGet64 (PcdPcieExpressBaseAddress)) ? + (((Bus == 0) && (Device == 0) && (Function == 0)) ? + PcdGet32 (PcdPcieRootPortConfigBaseAddress + + EFI_PCIE_ADDRESS (Bus, Device, Function, Register)): + PcdGet64 (PcdPcieExpressBaseAddress + + EFI_PCIE_ADDRESS (Bus, Device, Function, Register))) : + (((Bus == 0) && (Device == 0) && (Function == 0)) ? + PcdGet32 (PcdCcixRootPortConfigBaseAddress + + EFI_PCIE_ADDRESS (Bus, Device, Function, Register)): + PcdGet32 (PcdCcixExpressBaseAddress + + EFI_PCIE_ADDRESS (Bus, Device, Function, Register)))); + + if (!((Bus == 0) && (Device == 0) && (Function == 0))) { + if (IsBdfValid (Address) == mDummyConfigData) + ConfigAddress = (UINTN) &mDummyConfigData; } return (VOID *)ConfigAddress; diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf index acb6fb6219..eac981e460 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf +++ b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf @@ -21,7 +21,7 @@ # 2. Root port ECAM space is not capable of 8bit/16bit writes. # This library includes workaround for these limitations as well. # -# Copyright (c) 2020, ARM Limited. All rights reserved. +# Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -43,6 +43,8 @@ Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec [FixedPcd] + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize @@ -53,4 +55,5 @@ PcdLib [Pcd] - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress ## CONSUMES + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec index eea2d58402..5ec3c32539 100644 --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec @@ -46,6 +46,7 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64|0x00000010 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x00000011 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00000012 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT64|0x00000013 # CCIX gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount|18|UINT32|0x00000016 @@ -53,8 +54,8 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin|0|UINT32|0x00000018 gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|UINT32|0x00000019 gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001A - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x01FFFF|UINT32|0x0000001B - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x020000|UINT32|0x0000001C + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x00FFFFFF|UINT32|0x0000001B + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x01000000|UINT32|0x0000001C gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32|0x00000001D gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x0000001E gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32|0x00000001F -- 2.17.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [edk2-devel] [PATCH v2 1/3] Silicon/ARM/NeoverseN1Soc: Update PciExpressLib to enable CCIX port 2021-11-23 12:26 ` [PATCH v2 1/3] Silicon/ARM/NeoverseN1Soc: Update PciExpressLib to enable CCIX port Khasim Mohammed @ 2021-11-30 17:10 ` PierreGondois 2021-12-06 10:34 ` Khasim Mohammed 0 siblings, 1 reply; 8+ messages in thread From: PierreGondois @ 2021-11-30 17:10 UTC (permalink / raw) To: devel, khasim.mohammed; +Cc: nd, Deepak Pandey, Sami.mujawar Hi Khasim, It seems that: -PciHostBridgeDxe requires the PciSegmentLib. -The MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf implementation requires the PciLib. -The MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf requires the PciExpressLib, wich is implemented in Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/ -Since the patch 2 of the serie is now implementing a PciSegmentLib, isn't it possible to move the PCI hacks from Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/ to this new library ? The Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/ library would then not be needed anymore and could be removed. A question about the mDummyConfigData value in Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c, shouldn't it be a const ? I still made some comments inline in this patch. Regards, Pierre On 11/23/21 1:26 PM, Khasim Mohammed via groups.io wrote: > Update the PciExpressLib to enable CCIX port as PCIe root host by > validating the PCIe addresses and introducing corresponding PCD > entries. > > Change-Id: I0d1167b86e53a3781f59c4d68a3b2e61add4317e > Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com> > Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com> > --- > .../PciExpressLib.c | 127 ++++++++++++------ > .../PciExpressLib.inf | 7 +- > Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 5 +- > 3 files changed, 94 insertions(+), 45 deletions(-) > > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c > index bb0246b4a9..3abe0a2d6b 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c > +++ b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c > @@ -20,7 +20,7 @@ > The description of the workarounds included for these limitations can > be found in the comments below. > > - Copyright (c) 2020, ARM Limited. All rights reserved. > + Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.<BR> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > @@ -36,15 +36,29 @@ > #include <Library/PcdLib.h> > #include <NeoverseN1Soc.h> > > +#define BUS_OFFSET 20 > +#define DEV_OFFSET 15 > +#define FUNC_OFFSET 12 > +#define REG_OFFSET 4096 > + > /** > - Assert the validity of a PCI address. A valid PCI address should contain 1's > - only in the low 28 bits. > + Assert the validity of a PCI address. A valid PCI address should contain 1's. > > @param A The address to validate. > > **/ > #define ASSERT_INVALID_PCI_ADDRESS(A) \ > - ASSERT (((A) & ~0xfffffff) == 0) > + ASSERT (((A) & ~0xffffffff) == 0) > + > +#define EFI_PCIE_ADDRESS(bus, dev, func, reg) \ > + (UINT64) ( \ > + (((UINTN) bus) << BUS_OFFSET) | \ > + (((UINTN) dev) << DEV_OFFSET) | \ > + (((UINTN) func) << FUNC_OFFSET) | \ > + (((UINTN) (reg)) < REG_OFFSET ? \ > + ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32)))) > + > +#define GET_PCIE_BASE_ADDRESS(Address) (Address & 0xF8000000) > > /* Root port Entry, BDF Entries Count */ > #define BDF_TABLE_ENTRY_SIZE 4 > @@ -53,6 +67,7 @@ > > /* BDF table offsets for PCIe */ > #define PCIE_BDF_TABLE_OFFSET 0 > +#define CCIX_BDF_TABLE_OFFSET (16 * 1024) > > #define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F) > #define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F) > @@ -113,49 +128,64 @@ PciExpressRegisterForRuntimeAccess ( > } > > /** > - Check if the requested PCI address can be safely accessed. > + Check if the requested PCI address is a valid BDF address. > > - SCP performs the initial bus scan, prepares a table of valid BDF addresses > - and shares them through non-trusted SRAM. This function validates if the > - requested PCI address belongs to a valid BDF by checking the table of valid > - entries. If not, this function will return false. This is a workaround to > - avoid bus fault that occurs when accessing unavailable PCI device due to > - hardware bug. > + SCP performs the initial bus scan and prepares a table of valid BDF addresses > + and shares them through non-trusted SRAM. This function validates if the PCI > + address from any PCI request falls within the table of valid entries. If not, > + this function will return 0xFFFFFFFF. This is a workaround to avoid bus fault > + that happens when accessing unavailable PCI device due to RTL bug. > > @param Address The address that encodes the PCI Bus, Device, Function and > Register. > > - @return TRUE BDF can be accessed, valid. > - @return FALSE BDF should not be accessed, invalid. > + @return The base address of PCI Express. > > **/ > STATIC > -BOOLEAN > +UINTN > IsBdfValid ( > - IN UINTN Address > + IN UINTN Address > ) > { > + UINT8 Bus; > + UINT8 Device; > + UINT8 Function; > UINTN BdfCount; > UINTN BdfValue; > - UINTN BdfEntry; > UINTN Count; > UINTN TableBase; > - UINTN ConfigBase; > + UINTN PciAddress; > + > + Bus = GET_BUS_NUM (Address); > + Device = GET_DEV_NUM (Address); > + Function = GET_FUNC_NUM (Address); > + > + PciAddress = EFI_PCIE_ADDRESS (Bus, Device, Function, 0); > + > + if (GET_PCIE_BASE_ADDRESS (Address) == > + FixedPcdGet64 (PcdPcieExpressBaseAddress)) { > + TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFSET; > + } else { > + TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + CCIX_BDF_TABLE_OFFSET; > + } > > - ConfigBase = Address & ~0xFFF; > - TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFSET; > BdfCount = MmioRead32 (TableBase + BDF_TABLE_ENTRY_SIZE); > - BdfEntry = TableBase + BDF_TABLE_HEADER_SIZE; > - > - /* Skip the header & check remaining entry */ > - for (Count = 0; Count < BdfCount; Count++, BdfEntry += BDF_TABLE_ENTRY_SIZE) { > - BdfValue = MmioRead32 (BdfEntry); > - if (BdfValue == ConfigBase) { > - return TRUE; > - } > + > + /* Start from the second entry */ > + for (Count = BDF_TABLE_HEADER_COUNT; > + Count < (BdfCount + BDF_TABLE_HEADER_COUNT); > + Count++) { > + BdfValue = MmioRead32 (TableBase + (Count * BDF_TABLE_ENTRY_SIZE)); > + if (BdfValue == PciAddress) > + break; > } > > - return FALSE; > + if (Count == (BdfCount + BDF_TABLE_HEADER_COUNT)) { > + return mDummyConfigData; > + } else { > + return PciAddress; > + } > } > > /** > @@ -186,20 +216,35 @@ GetPciExpressAddress ( > IN UINTN Address > ) > { > - UINT8 Bus, Device, Function; > - UINTN ConfigAddress; > - > - Bus = GET_BUS_NUM (Address); > - Device = GET_DEV_NUM (Address); > + UINT8 Bus; > + UINT8 Device; > + UINT8 Function; > + UINT16 Register; > + UINTN ConfigAddress; > + > + // Get the EFI notation > + Bus = GET_BUS_NUM (Address); > + Device = GET_DEV_NUM (Address); > Function = GET_FUNC_NUM (Address); > - > - if ((Bus == 0) && (Device == 0) && (Function == 0)) { > - ConfigAddress = PcdGet32 (PcdPcieRootPortConfigBaseAddress) + Address; > - } else { > - ConfigAddress = PcdGet64 (PcdPciExpressBaseAddress) + Address; > - if (!IsBdfValid(Address)) { > - ConfigAddress = (UINTN)&mDummyConfigData; > - } > + Register = GET_REG_NUM (Address); > + > + ConfigAddress = (UINTN) > + ((GET_PCIE_BASE_ADDRESS (Address) == > + FixedPcdGet64 (PcdPcieExpressBaseAddress)) ? > + (((Bus == 0) && (Device == 0) && (Function == 0)) ? > + PcdGet32 (PcdPcieRootPortConfigBaseAddress > + + EFI_PCIE_ADDRESS (Bus, Device, Function, Register)): > + PcdGet64 (PcdPcieExpressBaseAddress > + + EFI_PCIE_ADDRESS (Bus, Device, Function, Register))) : > + (((Bus == 0) && (Device == 0) && (Function == 0)) ? > + PcdGet32 (PcdCcixRootPortConfigBaseAddress > + + EFI_PCIE_ADDRESS (Bus, Device, Function, Register)): > + PcdGet32 (PcdCcixExpressBaseAddress > + + EFI_PCIE_ADDRESS (Bus, Device, Function, Register)))); Is it possible to split it in multiple statement ? Since the case of the root bridge is special and checked multiple times, we could store the result of "(Bus == 0) && (Device == 0) && (Function == 0)" I m not sure why this is valid, but shouldn't the brackets of: PcdGet64 (PcdPcieExpressBaseAddress + EFI_PCIE_ADDRESS (Bus, Device, Function, Register)) be like: PcdGet64 (PcdPcieExpressBaseAddress) + EFI_PCIE_ADDRESS (Bus, Device, Function, Register) (Same question for other PcdGet64() calls in the assignement) > + > + if (!((Bus == 0) && (Device == 0) && (Function == 0))) { > + if (IsBdfValid (Address) == mDummyConfigData) > + ConfigAddress = (UINTN) &mDummyConfigData; > } > > return (VOID *)ConfigAddress; > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf > index acb6fb6219..eac981e460 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf > +++ b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf > @@ -21,7 +21,7 @@ > # 2. Root port ECAM space is not capable of 8bit/16bit writes. > # This library includes workaround for these limitations as well. > # > -# Copyright (c) 2020, ARM Limited. All rights reserved. > +# Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.<BR> > # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -43,6 +43,8 @@ > Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > > [FixedPcd] > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize > > @@ -53,4 +55,5 @@ > PcdLib > > [Pcd] > - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress ## CONSUMES > + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress > diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > index eea2d58402..5ec3c32539 100644 > --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > @@ -46,6 +46,7 @@ > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64|0x00000010 > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x00000011 > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00000012 > + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT64|0x00000013 > > # CCIX > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount|18|UINT32|0x00000016 > @@ -53,8 +54,8 @@ > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin|0|UINT32|0x00000018 > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|UINT32|0x00000019 > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001A > - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x01FFFF|UINT32|0x0000001B > - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x020000|UINT32|0x0000001C > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x00FFFFFF|UINT32|0x0000001B > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x01000000|UINT32|0x0000001C > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32|0x00000001D > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x0000001E > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32|0x00000001F ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [edk2-devel] [PATCH v2 1/3] Silicon/ARM/NeoverseN1Soc: Update PciExpressLib to enable CCIX port 2021-11-30 17:10 ` [edk2-devel] " PierreGondois @ 2021-12-06 10:34 ` Khasim Mohammed 0 siblings, 0 replies; 8+ messages in thread From: Khasim Mohammed @ 2021-12-06 10:34 UTC (permalink / raw) To: PierreGondois, devel [-- Attachment #1: Type: text/plain, Size: 13062 bytes --] Hi Pierre, I have addressed all the suggested changes and posted v3 version of patches. On Tue, Nov 30, 2021 at 09:10 AM, PierreGondois wrote: > > Hi Khasim, > > It seems that: > -PciHostBridgeDxe requires the PciSegmentLib. > -The MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf > implementation requires the PciLib. > -The MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf requires > the PciExpressLib, wich is implemented in > Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/ > -Since the patch 2 of the serie is now implementing a PciSegmentLib, isn't > it possible to move the PCI hacks from > Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/ to this new > library ? The > Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/ library > would then not be needed anymore and could be removed. I tried to do this, but unfortunately wasn't successful. We are reusing the standard version of PciExpressLib.c and modifying the GetPci functionality to return the updated base address. If we remove the inf entry from custom implementation then it will leverage the default one and it will fail to get fixed PCIe address. There is similar patches posted for Morello SOC, https://edk2.groups.io/g/devel/message/84344?p=%2C%2C%2C20%2C0%2C0%2C0%3A%3Arecentpostdate%2Fsticky%2C%2Cchandni%2C20%2C2%2C0%2C87497024 https://edk2.groups.io/g/devel/message/84165?p=%2C%2C%2C20%2C0%2C0%2C0%3A%3Arecentpostdate%2Fsticky%2C%2Ckhasim%2C20%2C2%2C0%2C87257273 > > A question about the mDummyConfigData value in > Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c, > shouldn't it be a const ? Have fixed this in v3 version of patches. > > I still made some comments inline in this patch. > > Regards, > > Pierre > > > On 11/23/21 1:26 PM, Khasim Mohammed via groups.io wrote: > >> Update the PciExpressLib to enable CCIX port as PCIe root host by >> validating the PCIe addresses and introducing corresponding PCD >> entries. >> >> Change-Id: I0d1167b86e53a3781f59c4d68a3b2e61add4317e >> Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com> >> Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com> >> --- >> .../PciExpressLib.c | 127 ++++++++++++------ >> .../PciExpressLib.inf | 7 +- >> Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 5 +- >> 3 files changed, 94 insertions(+), 45 deletions(-) >> >> diff --git >> a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c >> b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c >> >> index bb0246b4a9..3abe0a2d6b 100644 >> --- >> a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c >> >> +++ >> b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c >> >> @@ -20,7 +20,7 @@ >> The description of the workarounds included for these limitations can >> be found in the comments below. >> >> - Copyright (c) 2020, ARM Limited. All rights reserved. >> + Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.<BR> >> >> SPDX-License-Identifier: BSD-2-Clause-Patent >> >> @@ -36,15 +36,29 @@ >> #include <Library/PcdLib.h> >> #include <NeoverseN1Soc.h> >> >> +#define BUS_OFFSET 20 >> +#define DEV_OFFSET 15 >> +#define FUNC_OFFSET 12 >> +#define REG_OFFSET 4096 >> + >> /** >> - Assert the validity of a PCI address. A valid PCI address should contain >> 1's >> - only in the low 28 bits. >> + Assert the validity of a PCI address. A valid PCI address should contain >> 1's. >> >> @param A The address to validate. >> >> **/ >> #define ASSERT_INVALID_PCI_ADDRESS(A) \ >> - ASSERT (((A) & ~0xfffffff) == 0) >> + ASSERT (((A) & ~0xffffffff) == 0) >> + >> +#define EFI_PCIE_ADDRESS(bus, dev, func, reg) \ >> + (UINT64) ( \ >> + (((UINTN) bus) << BUS_OFFSET) | \ >> + (((UINTN) dev) << DEV_OFFSET) | \ >> + (((UINTN) func) << FUNC_OFFSET) | \ >> + (((UINTN) (reg)) < REG_OFFSET ? \ >> + ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32)))) >> + >> +#define GET_PCIE_BASE_ADDRESS(Address) (Address & 0xF8000000) >> >> /* Root port Entry, BDF Entries Count */ >> #define BDF_TABLE_ENTRY_SIZE 4 >> @@ -53,6 +67,7 @@ >> >> /* BDF table offsets for PCIe */ >> #define PCIE_BDF_TABLE_OFFSET 0 >> +#define CCIX_BDF_TABLE_OFFSET (16 * 1024) >> >> #define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F) >> #define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F) >> @@ -113,49 +128,64 @@ PciExpressRegisterForRuntimeAccess ( >> } >> >> /** >> - Check if the requested PCI address can be safely accessed. >> + Check if the requested PCI address is a valid BDF address. >> >> - SCP performs the initial bus scan, prepares a table of valid BDF >> addresses >> - and shares them through non-trusted SRAM. This function validates if the >> >> - requested PCI address belongs to a valid BDF by checking the table of >> valid >> - entries. If not, this function will return false. This is a workaround >> to >> - avoid bus fault that occurs when accessing unavailable PCI device due to >> >> - hardware bug. >> + SCP performs the initial bus scan and prepares a table of valid BDF >> addresses >> + and shares them through non-trusted SRAM. This function validates if the >> PCI >> + address from any PCI request falls within the table of valid entries. If >> not, >> + this function will return 0xFFFFFFFF. This is a workaround to avoid bus >> fault >> + that happens when accessing unavailable PCI device due to RTL bug. >> >> @param Address The address that encodes the PCI Bus, Device, Function and >> Register. >> >> - @return TRUE BDF can be accessed, valid. >> - @return FALSE BDF should not be accessed, invalid. >> + @return The base address of PCI Express. >> >> **/ >> STATIC >> -BOOLEAN >> +UINTN >> IsBdfValid ( >> - IN UINTN Address >> + IN UINTN Address >> ) >> { >> + UINT8 Bus; >> + UINT8 Device; >> + UINT8 Function; >> UINTN BdfCount; >> UINTN BdfValue; >> - UINTN BdfEntry; >> UINTN Count; >> UINTN TableBase; >> - UINTN ConfigBase; >> + UINTN PciAddress; >> + >> + Bus = GET_BUS_NUM (Address); >> + Device = GET_DEV_NUM (Address); >> + Function = GET_FUNC_NUM (Address); >> + >> + PciAddress = EFI_PCIE_ADDRESS (Bus, Device, Function, 0); >> + >> + if (GET_PCIE_BASE_ADDRESS (Address) == >> + FixedPcdGet64 (PcdPcieExpressBaseAddress)) { >> + TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFSET; >> + } else { >> + TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + CCIX_BDF_TABLE_OFFSET; >> + } >> >> - ConfigBase = Address & ~0xFFF; >> - TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFSET; >> BdfCount = MmioRead32 (TableBase + BDF_TABLE_ENTRY_SIZE); >> - BdfEntry = TableBase + BDF_TABLE_HEADER_SIZE; >> - >> - /* Skip the header & check remaining entry */ >> - for (Count = 0; Count < BdfCount; Count++, BdfEntry += >> BDF_TABLE_ENTRY_SIZE) { >> - BdfValue = MmioRead32 (BdfEntry); >> - if (BdfValue == ConfigBase) { >> - return TRUE; >> - } >> + >> + /* Start from the second entry */ >> + for (Count = BDF_TABLE_HEADER_COUNT; >> + Count < (BdfCount + BDF_TABLE_HEADER_COUNT); >> + Count++) { >> + BdfValue = MmioRead32 (TableBase + (Count * BDF_TABLE_ENTRY_SIZE)); >> + if (BdfValue == PciAddress) >> + break; >> } >> >> - return FALSE; >> + if (Count == (BdfCount + BDF_TABLE_HEADER_COUNT)) { >> + return mDummyConfigData; >> + } else { >> + return PciAddress; >> + } >> } >> >> /** >> @@ -186,20 +216,35 @@ GetPciExpressAddress ( >> IN UINTN Address >> ) >> { >> - UINT8 Bus, Device, Function; >> - UINTN ConfigAddress; >> - >> - Bus = GET_BUS_NUM (Address); >> - Device = GET_DEV_NUM (Address); >> + UINT8 Bus; >> + UINT8 Device; >> + UINT8 Function; >> + UINT16 Register; >> + UINTN ConfigAddress; >> + >> + // Get the EFI notation >> + Bus = GET_BUS_NUM (Address); >> + Device = GET_DEV_NUM (Address); >> Function = GET_FUNC_NUM (Address); >> - >> - if ((Bus == 0) && (Device == 0) && (Function == 0)) { >> - ConfigAddress = PcdGet32 (PcdPcieRootPortConfigBaseAddress) + Address; >> - } else { >> - ConfigAddress = PcdGet64 (PcdPciExpressBaseAddress) + Address; >> - if (!IsBdfValid(Address)) { >> - ConfigAddress = (UINTN)&mDummyConfigData; >> - } >> + Register = GET_REG_NUM (Address); >> + >> + ConfigAddress = (UINTN) >> + ((GET_PCIE_BASE_ADDRESS (Address) == >> + FixedPcdGet64 (PcdPcieExpressBaseAddress)) ? >> + (((Bus == 0) && (Device == 0) && (Function == 0)) ? >> + PcdGet32 (PcdPcieRootPortConfigBaseAddress >> + + EFI_PCIE_ADDRESS (Bus, Device, Function, Register)): >> + PcdGet64 (PcdPcieExpressBaseAddress >> + + EFI_PCIE_ADDRESS (Bus, Device, Function, Register))) : >> + (((Bus == 0) && (Device == 0) && (Function == 0)) ? >> + PcdGet32 (PcdCcixRootPortConfigBaseAddress >> + + EFI_PCIE_ADDRESS (Bus, Device, Function, Register)): >> + PcdGet32 (PcdCcixExpressBaseAddress >> + + EFI_PCIE_ADDRESS (Bus, Device, Function, Register)))); > > Is it possible to split it in multiple statement ? Since the case of the > root bridge is special and checked multiple times, we could store the > result of "(Bus == 0) && (Device == 0) && (Function == 0)" Have spit this functionality in v3 version of patches. > > I m not sure why this is valid, but shouldn't the brackets of: > > PcdGet64 (PcdPcieExpressBaseAddress + EFI_PCIE_ADDRESS (Bus, Device, > Function, Register)) > > be like: > > PcdGet64 (PcdPcieExpressBaseAddress) + EFI_PCIE_ADDRESS (Bus, Device, > Function, Register) > > (Same question for other PcdGet64() calls in the assignement) Have fixed this. > > >> + >> + if (!((Bus == 0) && (Device == 0) && (Function == 0))) { >> + if (IsBdfValid (Address) == mDummyConfigData) >> + ConfigAddress = (UINTN) &mDummyConfigData; >> } >> >> return (VOID *)ConfigAddress; >> diff --git >> a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf >> b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf >> >> index acb6fb6219..eac981e460 100644 >> --- >> a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf >> >> +++ >> b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf >> >> @@ -21,7 +21,7 @@ >> # 2. Root port ECAM space is not capable of 8bit/16bit writes. >> # This library includes workaround for these limitations as well. >> # >> -# Copyright (c) 2020, ARM Limited. All rights reserved. >> +# Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.<BR> >> # >> # SPDX-License-Identifier: BSD-2-Clause-Patent >> # >> @@ -43,6 +43,8 @@ >> Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec >> >> [FixedPcd] >> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress >> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize >> >> @@ -53,4 +55,5 @@ >> PcdLib >> >> [Pcd] >> - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES >> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress ## CONSUMES >> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress >> diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec >> b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec >> index eea2d58402..5ec3c32539 100644 >> --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec >> +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec >> @@ -46,6 +46,7 @@ >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64|0x00000010 >> >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x00000011 >> >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00000012 >> >> + >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT64|0x00000013 >> >> >> # CCIX >> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount|18|UINT32|0x00000016 >> @@ -53,8 +54,8 @@ >> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin|0|UINT32|0x00000018 >> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|UINT32|0x00000019 >> >> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001A >> - >> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x01FFFF|UINT32|0x0000001B >> >> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x020000|UINT32|0x0000001C >> >> + >> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x00FFFFFF|UINT32|0x0000001B >> >> + >> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x01000000|UINT32|0x0000001C >> >> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32|0x00000001D >> >> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x0000001E >> >> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32|0x00000001F >> > > [-- Attachment #2: Type: text/html, Size: 13706 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 2/3] Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library 2021-11-23 12:26 [PATCH v2 0/3] Enable CCIX port as PCIe root host on N1SDP Khasim Mohammed 2021-11-23 12:26 ` [PATCH v2 1/3] Silicon/ARM/NeoverseN1Soc: Update PciExpressLib to enable CCIX port Khasim Mohammed @ 2021-11-23 12:26 ` Khasim Mohammed 2021-11-23 12:26 ` [PATCH v2 3/3] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support Khasim Mohammed 2 siblings, 0 replies; 8+ messages in thread From: Khasim Mohammed @ 2021-11-23 12:26 UTC (permalink / raw) To: devel; +Cc: nd, Khasim Syed Mohammed The BasePCISegment Library in MdePkg doesn't allow configuring multiple segments required for PCIe and CCIX root port enumeration. Therefore, a custom PCI Segment library is adapted from SynQuacerPciSegmentLib and ported for N1Sdp. Change-Id: I0a124b0ea2fb7a8ee652de2d66b977d848c509b4 Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com> --- .../Library/PciSegmentLib/PciSegmentLib.c | 1425 +++++++++++++++++ .../Library/PciSegmentLib/PciSegmentLib.inf | 35 + 2 files changed, 1460 insertions(+) create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c new file mode 100644 index 0000000000..dbf00e1f14 --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c @@ -0,0 +1,1425 @@ +/** @file + PCI Segment Library for N1SDP SoC with multiple RCs + + Having two distinct root complexes is not supported by the standard + set of PciLib/PciExpressLib/PciSegmentLib, this PciSegmentLib + reimplements the functionality to support multiple root ports on + different segment numbers. + + Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR> + Copyright (c) 2021, ARM Limited. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <Base.h> + +#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/PcdLib.h> +#include <Library/PciLib.h> +#include <Library/PciSegmentLib.h> +#include <NeoverseN1Soc.h> + +typedef enum { + PciCfgWidthUint8 = 0, + PciCfgWidthUint16, + PciCfgWidthUint32, + PciCfgWidthMax +} PCI_CFG_WIDTH; + +/** + Assert the validity of a PCI Segment address. + A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63 + + @param A The address to validate. + @param M Additional bits to assert to be zero. +**/ +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \ + ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0) + +/** + Function to return PCIe Physical Address for different RCs. + If address is invalid, then ASSERT(). + + @param Address Address passed from bus layer. + + @return Return PCIe base address. + +**/ +STATIC +UINT64 +PciSegmentLibGetConfigBase ( + IN UINT64 Address + ) +{ + switch ((UINT16)(Address >> 32)) { + case 0: + return FixedPcdGet32 (PcdPcieExpressBaseAddress); + case 1: + return FixedPcdGet32 (PcdCcixExpressBaseAddress); + default: + ASSERT (FALSE); + } + return 0; +} + +/** + Internal worker function to read a PCI configuration register. + + @param Address The address that encodes the PCI Bus, Device, Function + and Register. + @param Width The width of data to read + + @return The value read from the PCI configuration register. +**/ +STATIC +UINT32 +PciSegmentLibReadWorker ( + IN UINT64 Address, + IN PCI_CFG_WIDTH Width + ) +{ + UINT64 Base; + + Base = PciSegmentLibGetConfigBase (Address); + + switch (Width) { + case PciCfgWidthUint8: + return PciRead8 (Base + (UINT32)Address); + case PciCfgWidthUint16: + return PciRead16 (Base + (UINT32)Address); + case PciCfgWidthUint32: + return PciRead32 (Base + (UINT32)Address); + default: + ASSERT (FALSE); + } + return 0; +} + +/** + Internal worker function to write to a PCI configuration register. + + @param Address The address that encodes the PCI Bus, Device, Function + and Register. + @param Width The width of data to write + @param Data The value to write. + + @return The value written to the PCI configuration register. +**/ +STATIC +UINT32 +PciSegmentLibWriteWorker ( + IN UINT64 Address, + IN PCI_CFG_WIDTH Width, + IN UINT32 Data + ) +{ + UINT64 Base; + + Base = PciSegmentLibGetConfigBase (Address); + + switch (Width) { + case PciCfgWidthUint8: + PciWrite8 (Base + (UINT32)Address, Data); + break; + case PciCfgWidthUint16: + PciWrite16 (Base + (UINT32)Address, Data); + break; + case PciCfgWidthUint32: + PciWrite32 (Base + (UINT32)Address, Data); + break; + default: + ASSERT (FALSE); + } + + return Data; +} + +/** + Reads an 8-bit PCI configuration register. + + Reads and returns the 8-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are + serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, + Device, Function and Register. + + @return The 8-bit PCI configuration register specified by the Address. +**/ +UINT8 +EFIAPI +PciSegmentRead8 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); + + return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8); +} + +/** + Writes an 8-bit PCI configuration register. + + Writes the 8-bit Value in the PCI configuration register specified by the + Address. This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, + Device, Function, and Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. +**/ +UINT8 +EFIAPI +PciSegmentWrite8 ( + IN UINT64 Address, + IN UINT8 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); + + return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value); +} + +/** + Performs a bitwise OR of an 8-bit PCI configuration register with + an 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. + + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function, and Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. +**/ +UINT8 +EFIAPI +PciSegmentOr8 ( + IN UINT64 Address, + IN UINT8 OrData + ) +{ + return PciSegmentWrite8 (Address, + (UINT8) (PciSegmentRead8 (Address) | OrData)); +} + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with + an 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by + AndData, and writes the result to the 8-bit PCI configuration register + specified by Address. + + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations + are serialized. If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function, and Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written to the PCI configuration register. +**/ +UINT8 +EFIAPI +PciSegmentAnd8 ( + IN UINT64 Address, + IN UINT8 AndData + ) +{ + return PciSegmentWrite8 (Address, + (UINT8) (PciSegmentRead8 (Address) & AndData)); +} + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with + an 8-bit value, followed by a bitwise OR with another 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified + by AndData, performs a bitwise OR between the result of the AND operation + and the value specified by OrData, and writes the result to the 8-bit + PCI configuration register specified by Address. + + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentAndThenOr8 ( + IN UINT64 Address, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + return PciSegmentWrite8 (Address, + (UINT8) ((PciSegmentRead8 (Address) & AndData) + | OrData)); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in an 8-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address The PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldRead8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 8-bit register is returned. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit + and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param Value The new value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldWrite8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ) +{ + return PciSegmentWrite8 (Address, + BitFieldWrite8 (PciSegmentRead8 (Address), + StartBit, + EndBit, + Value)); +} + +/** + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and + writes the result back to the bit field in the 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and + EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldOr8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ) +{ + return PciSegmentWrite8 (Address, + BitFieldOr8 (PciSegmentRead8 (Address), + StartBit, + EndBit, + OrData)); +} + +/** + Reads a bit field in an 8-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 8-bit register. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and + EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldAnd8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ) +{ + return PciSegmentWrite8 (Address, + BitFieldAnd8 (PciSegmentRead8 (Address), + StartBit, + EndBit, + AndData)); +} + +/** + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit + and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit + and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldAndThenOr8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + return PciSegmentWrite8 (Address, + BitFieldAndThenOr8 (PciSegmentRead8 (Address), + StartBit, + EndBit, + AndData, + OrData)); +} + +/** + Reads a 16-bit PCI configuration register. + + Reads and returns the 16-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function, and Register. + + @return The 16-bit PCI configuration register specified by Address. + +**/ +UINT16 +EFIAPI +PciSegmentRead16 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); + + return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16); +} + +/** + Writes a 16-bit PCI configuration register. + + Writes the 16-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. + This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function, and Register. + @param Value The value to write. + + @return The Value written is returned. + +**/ +UINT16 +EFIAPI +PciSegmentWrite16 ( + IN UINT64 Address, + IN UINT16 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); + + return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value); +} + +/** + Performs a bitwise OR of a 16-bit PCI configuration register with + a 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function and Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentOr16 ( + IN UINT64 Address, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 (Address, + (UINT16) (PciSegmentRead16 (Address) | OrData)); +} + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with + a 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified + by AndData, and writes the result to the 16-bit PCI configuration register + specified by the Address. + + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function, and Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentAnd16 ( + IN UINT64 Address, + IN UINT16 AndData + ) +{ + return PciSegmentWrite16 (Address, + (UINT16) (PciSegmentRead16 (Address) & AndData)); +} + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit + value, followed a bitwise OR with another 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by + AndData, performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 16-bit PCI + configuration register specified by the Address. + + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentAndThenOr16 ( + IN UINT64 Address, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 (Address, + (UINT16) ((PciSegmentRead16 (Address) & AndData) + | OrData)); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 16-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address The PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldRead16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 16-bit register is returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and + EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param Value The new value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldWrite16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ) +{ + return PciSegmentWrite16 (Address, + BitFieldWrite16 (PciSegmentRead16 (Address), + StartBit, + EndBit, + Value)); +} + +/** + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified + by OrData, and writes the result to the 16-bit PCI configuration register + specified by the Address. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and + EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldOr16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 (Address, + BitFieldOr16 (PciSegmentRead16 (Address), + StartBit, + EndBit, + OrData)); +} + +/** + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, + and writes the result back to the bit field in the 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by the Address. + + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and + EndBit, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function, and Register. + @param StartBit The ordinal of the least significant bit in the bit field. + The ordinal of the least significant bit in a byte is + bit 0. + @param EndBit The ordinal of the most significant bit in the bit field. + The ordinal of the most significant bit in a byte is bit 7. + @param AndData The value to AND with the read value from the PCI + configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldAnd16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ) +{ + return PciSegmentWrite16 (Address, + BitFieldAnd16 (PciSegmentRead16 (Address), + StartBit, + EndBit, + AndData)); +} + +/** + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and + EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and + EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldAndThenOr16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 (Address, + BitFieldAndThenOr16 (PciSegmentRead16 (Address), + StartBit, + EndBit, + AndData, + OrData)); +} + +/** + Reads a 32-bit PCI configuration register. + + Reads and returns the 32-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, + Device, Function and Register. + + @return The 32-bit PCI configuration register specified by Address. + +**/ +UINT32 +EFIAPI +PciSegmentRead32 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); + + return PciSegmentLibReadWorker (Address, PciCfgWidthUint32); +} + +/** + Writes a 32-bit PCI configuration register. + + Writes the 32-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function, and Register. + @param Value The value to write. + + @return The parameter of Value. + +**/ +UINT32 +EFIAPI +PciSegmentWrite32 ( + IN UINT64 Address, + IN UINT32 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); + + return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value); +} + +/** + Performs a bitwise OR of a 32-bit PCI configuration register with a + 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified + by OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. + + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function, and Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentOr32 ( + IN UINT64 Address, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData); +} + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with + a 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified + by AndData, and writes the result to the 32-bit PCI configuration register + specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, + Device, Function and Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentAnd32 ( + IN UINT64 Address, + IN UINT32 AndData + ) +{ + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData); +} + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with + a 32-bit value, followed by a bitwise OR with another 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified + by AndData, performs a bitwise OR between the result of the AND operation + and the value specified by OrData, and writes the result to the 32-bit + PCI configuration register specified by Address. + + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentAndThenOr32 ( + IN UINT64 Address, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 (Address, + (PciSegmentRead32 (Address) & AndData) | OrData); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 32-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address The PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldRead32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 32-bit register is returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit + and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param Value The new value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldWrite32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ) +{ + return PciSegmentWrite32 (Address, + BitFieldWrite32 (PciSegmentRead32 (Address), + StartBit, + EndBit, + Value)); +} + +/** + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and + writes the result back to the bit field in the 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and + EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldOr32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 (Address, + BitFieldOr32 (PciSegmentRead32 (Address), + StartBit, + EndBit, + OrData)); +} + +/** + Reads a bit field in a 32-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 32-bit register. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified + by AndData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration register + is returned. This function must guarantee that all PCI read and write + operations are serialized. Extra left bits in AndData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and + EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldAnd32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ) +{ + return PciSegmentWrite32 (Address, + BitFieldAnd32 (PciSegmentRead32 (Address), + StartBit, + EndBit, + AndData)); +} + +/** + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit + and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit + and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldAndThenOr32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 ( + Address, + BitFieldAndThenOr32 (PciSegmentRead32 (Address), + StartBit, + EndBit, + AndData, + OrData)); +} + +/** + Reads a range of PCI configuration registers into a caller supplied buffer. + + Reads the range of PCI configuration registers specified by StartAddress and + Size into the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be read. Size is + returned. When possible 32-bit PCI configuration read cycles are used to read + from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit + and 16-bit PCI configuration read cycles may be used at the beginning and the + end of the range. + + If any reserved bits in StartAddress are set, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress The starting address that encodes the PCI Segment, Bus, + Device, Function and Register. + @param Size The size in bytes of the transfer. + @param Buffer The pointer to a buffer receiving the data read. + + @return Size + +**/ +UINTN +EFIAPI +PciSegmentReadBuffer ( + IN UINT64 StartAddress, + IN UINTN Size, + OUT VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); + ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); + + if (Size == 0) { + return Size; + } + + ASSERT (Buffer != NULL); + + // Save Size for return + ReturnValue = Size; + + if ((StartAddress & BIT0) != 0) { + // Read a byte if StartAddress is byte aligned + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress); + StartAddress += sizeof (UINT8); + Size -= sizeof (UINT8); + Buffer = (UINT8*)Buffer + 1; + } + + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) { + // Read a word if StartAddress is word aligned + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); + StartAddress += sizeof (UINT16); + Size -= sizeof (UINT16); + Buffer = (UINT16*)Buffer + 1; + } + + while (Size >= sizeof (UINT32)) { + // Read as many double words as possible + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress)); + StartAddress += sizeof (UINT32); + Size -= sizeof (UINT32); + Buffer = (UINT32*)Buffer + 1; + } + + if (Size >= sizeof (UINT16)) { + // Read the last remaining word if exist + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); + StartAddress += sizeof (UINT16); + Size -= sizeof (UINT16); + Buffer = (UINT16*)Buffer + 1; + } + + if (Size >= sizeof (UINT8)) { + // Read the last remaining byte if exist + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress); + } + + return ReturnValue; +} + + +/** + Copies the data in a caller supplied buffer to a specified range of PCI + configuration space. + + Writes the range of PCI configuration registers specified by StartAddress and + Size from the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be written. Size is + returned. When possible 32-bit PCI configuration write cycles are used to + write from StartAdress to StartAddress + Size. Due to alignment restrictions, + 8-bit and 16-bit PCI configuration write cycles may be used at the beginning + and the end of the range. + + If any reserved bits in StartAddress are set, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress The starting address that encodes the PCI Segment, Bus, + Device, Function and Register. + @param Size The size in bytes of the transfer. + @param Buffer The pointer to a buffer containing the data to write. + + @return The parameter of Size. + +**/ +UINTN +EFIAPI +PciSegmentWriteBuffer ( + IN UINT64 StartAddress, + IN UINTN Size, + IN VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); + ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); + + if (Size == 0) { + return 0; + } + + ASSERT (Buffer != NULL); + + // Save Size for return + ReturnValue = Size; + + if ((StartAddress & BIT0) != 0) { + // Write a byte if StartAddress is byte aligned + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer); + StartAddress += sizeof (UINT8); + Size -= sizeof (UINT8); + Buffer = (UINT8*)Buffer + 1; + } + + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) { + // Write a word if StartAddress is word aligned + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); + StartAddress += sizeof (UINT16); + Size -= sizeof (UINT16); + Buffer = (UINT16*)Buffer + 1; + } + + while (Size >= sizeof (UINT32)) { + // Write as many double words as possible + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer)); + StartAddress += sizeof (UINT32); + Size -= sizeof (UINT32); + Buffer = (UINT32*)Buffer + 1; + } + + if (Size >= sizeof (UINT16)) { + // Write the last remaining word if exist + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); + StartAddress += sizeof (UINT16); + Size -= sizeof (UINT16); + Buffer = (UINT16*)Buffer + 1; + } + + if (Size >= sizeof (UINT8)) { + // Write the last remaining byte if exist + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer); + } + + return ReturnValue; +} diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf new file mode 100644 index 0000000000..fdeb2eb5ad --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf @@ -0,0 +1,35 @@ +## @file +# PCI Segment Library for N1Sdp SoC with multiple RCs +# +# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2021, ARM Limited. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = PciSegmentLib + FILE_GUID = b5ecc9c3-6b30-4f72-8a06-889b4ea8427e + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PciSegmentLib + +[Sources] + PciSegmentLib.c + +[Packages] + MdePkg/MdePkg.dec + Platform/ARM/N1Sdp/N1SdpPlatform.dec + Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + PciLib + +[FixedPcd] + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress -- 2.17.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support 2021-11-23 12:26 [PATCH v2 0/3] Enable CCIX port as PCIe root host on N1SDP Khasim Mohammed 2021-11-23 12:26 ` [PATCH v2 1/3] Silicon/ARM/NeoverseN1Soc: Update PciExpressLib to enable CCIX port Khasim Mohammed 2021-11-23 12:26 ` [PATCH v2 2/3] Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library Khasim Mohammed @ 2021-11-23 12:26 ` Khasim Mohammed 2021-11-30 17:06 ` [edk2-devel] " PierreGondois 2 siblings, 1 reply; 8+ messages in thread From: Khasim Mohammed @ 2021-11-23 12:26 UTC (permalink / raw) To: devel; +Cc: nd, Khasim Syed Mohammed This patch enables CCIX root complex support by updating the root complex node info in PciHostBridge library and enabling PciSegment library for N1Sdp. Change-Id: I0510b1023aec16365b614d4eaf81858851d9fa28 Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com> --- .../ConfigurationManagerDxe.inf | 3 +- Platform/ARM/N1Sdp/N1SdpPlatform.dec | 3 - Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 3 +- .../PciHostBridgeLib/PciHostBridgeLib.c | 71 +++++++++++++++++-- .../PciHostBridgeLib/PciHostBridgeLib.inf | 11 ++- .../Library/PlatformLib/PlatformLib.inf | 1 + .../Library/PlatformLib/PlatformLibMem.c | 4 +- 7 files changed, 81 insertions(+), 15 deletions(-) diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf index 027a4202ff..67b0c3a0ea 100644 --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf @@ -76,8 +76,6 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate - gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress - gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base @@ -91,6 +89,7 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec b/Platform/ARM/N1Sdp/N1SdpPlatform.dec index 2ab6c20dcc..98d2d5ba81 100644 --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dec +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec @@ -34,9 +34,6 @@ gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001 gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002 - # PCIe - gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT32|0x00000007 - # External memory gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0|UINT64|0x00000029 diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc index 7488bdc036..75d7871452 100644 --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc @@ -75,7 +75,7 @@ [LibraryClasses.common.DXE_DRIVER] FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf PciHostBridgeLib|Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf - PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf + PciSegmentLib|Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf PciExpressLib|Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf @@ -127,7 +127,6 @@ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000 # PCIe - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x70000000 gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24 gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c index 9332939f63..c3a14a6c17 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -1,7 +1,7 @@ /** @file * PCI Host Bridge Library instance for ARM Neoverse N1 platform * -* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. +* Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR> * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -16,6 +16,8 @@ #include <Protocol/PciHostBridgeResourceAllocation.h> #include <Protocol/PciRootBridgeIo.h> +#define ROOT_COMPLEX_NUM 2 + GLOBAL_REMOVE_IF_UNREFERENCED STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { L"Mem", L"I/O", L"Bus" @@ -28,7 +30,7 @@ typedef struct { } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; #pragma pack () -STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = { +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[ROOT_COMPLEX_NUM] = { // PCIe { { @@ -51,10 +53,33 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = { 0 } } - } + }, + //CCIX + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)sizeof (ACPI_HID_DEVICE_PATH), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) + } + }, + EISA_PNP_ID(0x0A09), // CCIX + 0 + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, }; -STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = { +STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] = { { 0, // Segment 0, // Supports @@ -90,7 +115,43 @@ STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = { 0 }, (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] - } + }, + { + 1, // Segment + 0, // Supports + 0, // Attributes + TRUE, // DmaAbove4G + FALSE, // NoExtendedConfigSpace + FALSE, // ResourceAssigned + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + { + // Bus + FixedPcdGet32 (PcdCcixBusMin), + FixedPcdGet32 (PcdCcixBusMax) + }, { + // Io + FixedPcdGet64 (PcdCcixIoBase), + FixedPcdGet64 (PcdCcixIoBase) + FixedPcdGet64 (PcdCcixIoSize) - 1 + }, { + // Mem + FixedPcdGet32 (PcdCcixMmio32Base), + FixedPcdGet32 (PcdCcixMmio32Base) + FixedPcdGet32 (PcdCcixMmio32Size) - 1 + }, { + // MemAbove4G + FixedPcdGet64 (PcdCcixMmio64Base), + FixedPcdGet64 (PcdCcixMmio64Base) + FixedPcdGet64 (PcdCcixMmio64Size) - 1 + }, { + // PMem + MAX_UINT64, + 0 + }, { + // PMemAbove4G + MAX_UINT64, + 0 + }, + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1] + }, }; /** diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf index 3ff1c592f2..3356c3ad35 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf @@ -1,7 +1,7 @@ ## @file # PCI Host Bridge Library instance for ARM Neoverse N1 platform. # -# Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. +# Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -42,6 +42,15 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size + [Protocols] gEfiCpuIo2ProtocolGuid diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf index 8e2154aadf..96e590cdd8 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf @@ -43,6 +43,7 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c index 1c4a445c5e..339fa07b32 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c @@ -115,8 +115,8 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; // PCIe ECAM Configuration Space - VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciExpressBaseAddress); - VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciExpressBaseAddress); + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPcieExpressBaseAddress); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPcieExpressBaseAddress); VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdPcieBusMax) - FixedPcdGet32 (PcdPcieBusMin) + 1) * SIZE_1MB; -- 2.17.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [edk2-devel] [PATCH v2 3/3] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support 2021-11-23 12:26 ` [PATCH v2 3/3] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support Khasim Mohammed @ 2021-11-30 17:06 ` PierreGondois 2021-12-06 10:27 ` Khasim Mohammed 0 siblings, 1 reply; 8+ messages in thread From: PierreGondois @ 2021-11-30 17:06 UTC (permalink / raw) To: devel, khasim.mohammed; +Cc: nd, Sami.mujawar Hi Khasim, On 11/23/21 1:26 PM, Khasim Mohammed via groups.io wrote: > This patch enables CCIX root complex support by updating > the root complex node info in PciHostBridge library > and enabling PciSegment library for N1Sdp. > > Change-Id: I0510b1023aec16365b614d4eaf81858851d9fa28 > Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com> > --- > .../ConfigurationManagerDxe.inf | 3 +- > Platform/ARM/N1Sdp/N1SdpPlatform.dec | 3 - > Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 3 +- > .../PciHostBridgeLib/PciHostBridgeLib.c | 71 +++++++++++++++++-- > .../PciHostBridgeLib/PciHostBridgeLib.inf | 11 ++- > .../Library/PlatformLib/PlatformLib.inf | 1 + > .../Library/PlatformLib/PlatformLibMem.c | 4 +- > 7 files changed, 81 insertions(+), 15 deletions(-) > > diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf > index 027a4202ff..67b0c3a0ea 100644 > --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf > +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf > @@ -76,8 +76,6 @@ > gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase > gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate > > - gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress > - > gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace > gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base > > @@ -91,6 +89,7 @@ > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin > + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize > diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec b/Platform/ARM/N1Sdp/N1SdpPlatform.dec > index 2ab6c20dcc..98d2d5ba81 100644 > --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dec > +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec > @@ -34,9 +34,6 @@ > gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001 > gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002 > > - # PCIe > - gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT32|0x00000007 > - I think the "# Remote Chip PCIe" definitions also need to be removed. Unrelated to this, but it seems there are some hard-coded PCI values at https://github.com/tianocore/edk2-platforms/blob/master/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c#L1050 that are also defined as Pcds. Would it be possible to replace the hard coded values ? > # External memory > gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0|UINT64|0x00000029 > > diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc > index 7488bdc036..75d7871452 100644 > --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc > +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc > @@ -75,7 +75,7 @@ > [LibraryClasses.common.DXE_DRIVER] > FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf > PciHostBridgeLib|Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf > - PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf > + PciSegmentLib|Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf > PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf > PciExpressLib|Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf > > @@ -127,7 +127,6 @@ > gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000 > > # PCIe > - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x70000000 > gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24 > gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE > > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c > index 9332939f63..c3a14a6c17 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c > @@ -1,7 +1,7 @@ > /** @file > * PCI Host Bridge Library instance for ARM Neoverse N1 platform > * > -* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. > +* Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR> > * > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > @@ -16,6 +16,8 @@ > #include <Protocol/PciHostBridgeResourceAllocation.h> > #include <Protocol/PciRootBridgeIo.h> > > +#define ROOT_COMPLEX_NUM 2 > + > GLOBAL_REMOVE_IF_UNREFERENCED > STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { > L"Mem", L"I/O", L"Bus" > @@ -28,7 +30,7 @@ typedef struct { > } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; > #pragma pack () > > -STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = { > +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[ROOT_COMPLEX_NUM] = { > // PCIe > { > { > @@ -51,10 +53,33 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = { > 0 > } > } > - } > + }, > + //CCIX > + { > + { > + { > + ACPI_DEVICE_PATH, > + ACPI_DP, > + { > + (UINT8)sizeof (ACPI_HID_DEVICE_PATH), > + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) > + } > + }, > + EISA_PNP_ID(0x0A09), // CCIX > + 0 > + }, > + { > + END_DEVICE_PATH_TYPE, > + END_ENTIRE_DEVICE_PATH_SUBTYPE, > + { > + END_DEVICE_PATH_LENGTH, > + 0 > + } > + } > + }, > }; > > -STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = { > +STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] = { > { > 0, // Segment > 0, // Supports > @@ -90,7 +115,43 @@ STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = { > 0 > }, > (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] > - } > + }, > + { > + 1, // Segment > + 0, // Supports > + 0, // Attributes > + TRUE, // DmaAbove4G > + FALSE, // NoExtendedConfigSpace > + FALSE, // ResourceAssigned > + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes > + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, > + { > + // Bus > + FixedPcdGet32 (PcdCcixBusMin), > + FixedPcdGet32 (PcdCcixBusMax) > + }, { > + // Io > + FixedPcdGet64 (PcdCcixIoBase), > + FixedPcdGet64 (PcdCcixIoBase) + FixedPcdGet64 (PcdCcixIoSize) - 1 > + }, { > + // MemSilicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > + FixedPcdGet32 (PcdCcixMmio32Base), > + FixedPcdGet32 (PcdCcixMmio32Base) + FixedPcdGet32 (PcdCcixMmio32Size) - 1 > + }, { > + // MemAbove4G > + FixedPcdGet64 (PcdCcixMmio64Base), > + FixedPcdGet64 (PcdCcixMmio64Base) + FixedPcdGet64 (PcdCcixMmio64Size) - 1 > + }, { > + // PMem > + MAX_UINT64, > + 0 > + }, { > + // PMemAbove4G > + MAX_UINT64, > + 0 > + }, > + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1] > + }, > }; > > /** > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf > index 3ff1c592f2..3356c3ad35 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf > @@ -1,7 +1,7 @@ > ## @file > # PCI Host Bridge Library instance for ARM Neoverse N1 platform. > # > -# Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. > +# Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR> > # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -42,6 +42,15 @@ > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size > > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size > + > [Protocols] > gEfiCpuIo2ProtocolGuid > > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > index 8e2154aadf..96e590cdd8 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > @@ -43,6 +43,7 @@ > gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin > + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > index 1c4a445c5e..339fa07b32 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > @@ -115,8 +115,8 @@ ArmPlatformGetVirtualMemoryMap ( > VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > > // PCIe ECAM Configuration Space > - VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciExpressBaseAddress); > - VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciExpressBaseAddress); > + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPcieExpressBaseAddress); > + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPcieExpressBaseAddress); > VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdPcieBusMax) - > FixedPcdGet32 (PcdPcieBusMin) + 1) * > SIZE_1MB; ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [edk2-devel] [PATCH v2 3/3] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support 2021-11-30 17:06 ` [edk2-devel] " PierreGondois @ 2021-12-06 10:27 ` Khasim Mohammed 0 siblings, 0 replies; 8+ messages in thread From: Khasim Mohammed @ 2021-12-06 10:27 UTC (permalink / raw) To: PierreGondois, devel [-- Attachment #1: Type: text/plain, Size: 10569 bytes --] On Tue, Nov 30, 2021 at 09:06 AM, PierreGondois wrote: Hi Pierre, > > Hi Khasim, > > On 11/23/21 1:26 PM, Khasim Mohammed via groups.io wrote: > >> This patch enables CCIX root complex support by updating >> the root complex node info in PciHostBridge library >> and enabling PciSegment library for N1Sdp. >> >> Change-Id: I0510b1023aec16365b614d4eaf81858851d9fa28 >> Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com> >> --- >> .../ConfigurationManagerDxe.inf | 3 +- >> Platform/ARM/N1Sdp/N1SdpPlatform.dec | 3 - >> Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 3 +- >> .../PciHostBridgeLib/PciHostBridgeLib.c | 71 +++++++++++++++++-- >> .../PciHostBridgeLib/PciHostBridgeLib.inf | 11 ++- >> .../Library/PlatformLib/PlatformLib.inf | 1 + >> .../Library/PlatformLib/PlatformLibMem.c | 4 +- >> 7 files changed, 81 insertions(+), 15 deletions(-) >> >> diff --git >> a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf >> b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf >> >> index 027a4202ff..67b0c3a0ea 100644 >> --- >> a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf >> >> +++ >> b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf >> >> @@ -76,8 +76,6 @@ >> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase >> gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate >> >> - gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress >> - >> gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace >> gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base >> >> @@ -91,6 +89,7 @@ >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin >> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize >> diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec >> b/Platform/ARM/N1Sdp/N1SdpPlatform.dec >> index 2ab6c20dcc..98d2d5ba81 100644 >> --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dec >> +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec >> @@ -34,9 +34,6 @@ >> gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001 >> gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002 >> >> - # PCIe >> - >> gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT32|0x00000007 >> >> - > > I think the "# Remote Chip PCIe" definitions also need to be removed. I removed these in v3 posted just now. > > Unrelated to this, but it seems there are some hard-coded PCI values at > > https://github.com/tianocore/edk2-platforms/blob/master/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c#L1050 > > > that are also defined as Pcds. Would it be possible to replace the hard > coded values ? Have removed the hardcoded entries and changed with PCDs. > > >> # External memory >> gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0|UINT64|0x00000029 >> >> diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc >> b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc >> index 7488bdc036..75d7871452 100644 >> --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc >> +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc >> @@ -75,7 +75,7 @@ >> [LibraryClasses.common.DXE_DRIVER] >> FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf >> PciHostBridgeLib|Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf >> >> - >> PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf >> >> + >> PciSegmentLib|Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf >> >> PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf >> PciExpressLib|Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf >> >> >> @@ -127,7 +127,6 @@ >> gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000 >> >> # PCIe >> - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x70000000 >> gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24 >> gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE >> >> diff --git >> a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c >> b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c >> index 9332939f63..c3a14a6c17 100644 >> --- >> a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c >> +++ >> b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c >> @@ -1,7 +1,7 @@ >> /** @file >> * PCI Host Bridge Library instance for ARM Neoverse N1 platform >> * >> -* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. >> +* Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR> >> * >> * SPDX-License-Identifier: BSD-2-Clause-Patent >> * >> @@ -16,6 +16,8 @@ >> #include <Protocol/PciHostBridgeResourceAllocation.h> >> #include <Protocol/PciRootBridgeIo.h> >> >> +#define ROOT_COMPLEX_NUM 2 >> + >> GLOBAL_REMOVE_IF_UNREFERENCED >> STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { >> >> L"Mem", L"I/O", L"Bus" >> @@ -28,7 +30,7 @@ typedef struct { >> } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; >> #pragma pack () >> >> -STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = { >> +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH >> mEfiPciRootBridgeDevicePath[ROOT_COMPLEX_NUM] = { >> // PCIe >> { >> { >> @@ -51,10 +53,33 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH >> mEfiPciRootBridgeDevicePath[] = { >> 0 >> } >> } >> - } >> + }, >> + //CCIX >> + { >> + { >> + { >> + ACPI_DEVICE_PATH, >> + ACPI_DP, >> + { >> + (UINT8)sizeof (ACPI_HID_DEVICE_PATH), >> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) >> + } >> + }, >> + EISA_PNP_ID(0x0A09), // CCIX >> + 0 >> + }, >> + { >> + END_DEVICE_PATH_TYPE, >> + END_ENTIRE_DEVICE_PATH_SUBTYPE, >> + { >> + END_DEVICE_PATH_LENGTH, >> + 0 >> + } >> + } >> + }, >> }; >> >> -STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = { >> +STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] = { >> { >> 0, // Segment >> 0, // Supports >> @@ -90,7 +115,43 @@ STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = { >> 0 >> }, >> (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] >> - } >> + }, >> + { >> + 1, // Segment >> + 0, // Supports >> + 0, // Attributes >> + TRUE, // DmaAbove4G >> + FALSE, // NoExtendedConfigSpace >> + FALSE, // ResourceAssigned >> + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes >> + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, >> + { >> + // Bus >> + FixedPcdGet32 (PcdCcixBusMin), >> + FixedPcdGet32 (PcdCcixBusMax) >> + }, { >> + // Io >> + FixedPcdGet64 (PcdCcixIoBase), >> + FixedPcdGet64 (PcdCcixIoBase) + FixedPcdGet64 (PcdCcixIoSize) - 1 >> + }, { >> + // MemSilicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec >> + FixedPcdGet32 (PcdCcixMmio32Base), >> + FixedPcdGet32 (PcdCcixMmio32Base) + FixedPcdGet32 (PcdCcixMmio32Size) - >> 1 >> + }, { >> + // MemAbove4G >> + FixedPcdGet64 (PcdCcixMmio64Base), >> + FixedPcdGet64 (PcdCcixMmio64Base) + FixedPcdGet64 (PcdCcixMmio64Size) - >> 1 >> + }, { >> + // PMem >> + MAX_UINT64, >> + 0 >> + }, { >> + // PMemAbove4G >> + MAX_UINT64, >> + 0 >> + }, >> + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1] >> + }, >> }; >> >> /** >> diff --git >> a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf >> b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf >> index 3ff1c592f2..3356c3ad35 100644 >> --- >> a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf >> +++ >> b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf >> @@ -1,7 +1,7 @@ >> ## @file >> # PCI Host Bridge Library instance for ARM Neoverse N1 platform. >> # >> -# Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. >> +# Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR> >> # >> # SPDX-License-Identifier: BSD-2-Clause-Patent >> # >> @@ -42,6 +42,15 @@ >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size >> >> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin >> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax >> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase >> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize >> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base >> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size >> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base >> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size >> + >> [Protocols] >> gEfiCpuIo2ProtocolGuid >> >> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf >> b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf >> index 8e2154aadf..96e590cdd8 100644 >> --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf >> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf >> @@ -43,6 +43,7 @@ >> gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin >> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base >> diff --git >> a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c >> b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c >> index 1c4a445c5e..339fa07b32 100644 >> --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c >> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c >> @@ -115,8 +115,8 @@ ArmPlatformGetVirtualMemoryMap ( >> VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; >> >> >> // PCIe ECAM Configuration Space >> - VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 >> (PcdPciExpressBaseAddress); >> - VirtualMemoryTable[Index].VirtualBase = PcdGet64 >> (PcdPciExpressBaseAddress); >> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 >> (PcdPcieExpressBaseAddress); >> + VirtualMemoryTable[Index].VirtualBase = PcdGet64 >> (PcdPcieExpressBaseAddress); >> VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdPcieBusMax) - >> FixedPcdGet32 (PcdPcieBusMin) + 1) * >> SIZE_1MB; > > [-- Attachment #2: Type: text/html, Size: 11010 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-12-06 10:34 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-11-23 12:26 [PATCH v2 0/3] Enable CCIX port as PCIe root host on N1SDP Khasim Mohammed 2021-11-23 12:26 ` [PATCH v2 1/3] Silicon/ARM/NeoverseN1Soc: Update PciExpressLib to enable CCIX port Khasim Mohammed 2021-11-30 17:10 ` [edk2-devel] " PierreGondois 2021-12-06 10:34 ` Khasim Mohammed 2021-11-23 12:26 ` [PATCH v2 2/3] Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library Khasim Mohammed 2021-11-23 12:26 ` [PATCH v2 3/3] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support Khasim Mohammed 2021-11-30 17:06 ` [edk2-devel] " PierreGondois 2021-12-06 10:27 ` Khasim Mohammed
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