1) when implementing PciHostBridgeLib, are we supposed to put host addresses (address the CPU uses after translation) in the Mem/MemAbove4G apertures or PCI/device addresses? (address the device uses before translation)

PCI_ROOT_BRIDGE_APERTURE is defined here: edk2/MdeModulePkg/Include/Library/PciHostBridgeLib.h at master · tianocore/edk2 (github.com)

Base = Device Address

Translation = Device Address - Host Address.

Also worth noting that in an ACPI memory resource descriptor (DWordMemory, QWordMemory, ...), AddressTranslation (_TRA) is actually the opposite of above = Host Address - Device Address.

2) Does the 'Mem' aperture have to be a 32 bit address/limit from host perspective?

From PCI device perspective. Host could have it mapped above 4 GB, and this is where you need translation.

3) Does translation have to be 0 for Mem/MemAbove4G apertures in the PCI_ROOT_BRIDGE struct? Most example platforms do that, but I'm not sure if that's a requirement for PciHostBridgeLib or just convention.

It depends on how your platform maps PCI apertures in the CPU address space.

If an identity mapping is used (Host Address == Device Address) - ideally, then Translation is 0.