From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id 9B0FDD80091 for ; Tue, 30 Jul 2024 02:35:28 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=JwmyAlJFUAfD8dgV+DczMiRNeN07vOgfSEgFkaXivy4=; c=relaxed/simple; d=groups.io; h=Subject:To:From:User-Agent:MIME-Version:Date:References:In-Reply-To:Message-ID:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type; s=20240206; t=1722306928; v=1; b=vj3zhZHOYh9UjjaQcKt7aEgzcKDDUUxSZwEepZog5U9mx18QVWgZ29dJ970MK48OQvK2MpsM PVE/s68n/U7j8HsQcRntidan2cclQQKgOe/QJ98eE554P9TIeiyYLfo4XsDkrPsciqN0QbJZSzg 34u/I5XP+mB6ZFBhEtmePcav04BVIgiZ80WLnVRWk/d45kxH0LAxKkjbdHPgr+gR8pwCyesdsWe y81TFDeJBEmpgo05h2D5Lo4eFoKktl/R8G1vPvit1SMi4H83Aq1H6CWRzFFlN3l7Z677N2H0S0S XZF0PVLcs/tnGGjtJaD7Y/lt65XXnNWEG7m+Xu7Y7J8pA== X-Received: by 127.0.0.2 with SMTP id AtphYY7687511xw0f0Bu2VTn; Mon, 29 Jul 2024 19:35:26 -0700 Subject: Re: [edk2-devel] [Question] How do you set PCIe host bridge address space granularity for a PCI host bridge defined with PciHostBridgeLib? To: "Arminder Singh" , devel@edk2.groups.io From: "Alexander D" X-Originating-Location: Galati, RO (5.13.178.255) X-Originating-Platform: Windows Chrome 127 User-Agent: GROUPS.IO Web Poster MIME-Version: 1.0 Date: Mon, 29 Jul 2024 19:35:21 -0700 References: <4791.1722298751229097446@groups.io> In-Reply-To: <4791.1722298751229097446@groups.io> Message-ID: <22372.1722306921287461697@groups.io> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,aenv067@gmail.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: MQLINmPfuO4gih0R6CfLoZHqx7686176AA= Content-Type: multipart/alternative; boundary="vK3iGtYUwchHHv2A4MAv" X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=vj3zhZHO; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=gmail.com (policy=none) --vK3iGtYUwchHHv2A4MAv Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable >=20 > 1) when implementing PciHostBridgeLib, are we supposed to put host > addresses (address the CPU uses after translation) in the Mem/MemAbove4G > apertures or PCI/device addresses? (address the device uses before > translation) PCI_ROOT_BRIDGE_APERTURE is defined here: edk2/MdeModulePkg/Include/ Librar= y/PciHostBridgeLib.h at master =C2=B7 tianocore/edk2 (github.com) ( https:/= /github.com/tianocore/edk2/blob/master/MdeModulePkg/Include/Library/PciHost= BridgeLib.h#L13 ) Base =3D Device Address Translation =3D Device Address - Host Address. Also worth noting that in an ACPI memory resource descriptor (DWordMemory, = QWordMemory, ...), AddressTranslation (_TRA) is actually the opposite of ab= ove =3D Host Address - Device Address. >=20 > 2) Does the 'Mem' aperture have to be a 32 bit address/limit from host > perspective? >From PCI device perspective. Host could have it mapped above 4 GB, and this= is where you need translation. >=20 > 3) Does translation have to be 0 for Mem/MemAbove4G apertures in the > PCI_ROOT_BRIDGE struct? Most example platforms do that, but I'm not sure > if that's a requirement for PciHostBridgeLib or just convention. It depends on how your platform maps PCI apertures in the CPU address space= . If an identity mapping is used (Host Address =3D=3D Device Address) - ideal= ly, then Translation is 0. -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#120073): https://edk2.groups.io/g/devel/message/120073 Mute This Topic: https://groups.io/mt/107528139/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- --vK3iGtYUwchHHv2A4MAv Content-Type: text/html; charset="utf-8" Content-Transfer-Encoding: quoted-printable
1) when implementing = PciHostBridgeLib, are we supposed to put host addresses (address the CPU us= es after translation) in the Mem/MemAbove4G apertures or PCI/device address= es? (address the device uses before translation)
 
PCI_ROOT_BRIDGE_APERTURE is defined here:  edk2/MdeModulePkg/Include/Library/PciHostBridgeLib.h at master · tianocore/edk2 (github.com)<= /a>
 
Base =3D Device Address
Translation =3D Device Address - Host Address.
 
Also worth noting that in an ACPI memory resource descriptor (DWordMem= ory, QWordMemory, ...), AddressTranslation (_TRA) is actually the opposite = of above =3D Host Address - Device Address.
 
2) Does the 'Mem' ape= rture have to be a 32 bit address/limit from host perspective?
 
From PCI device perspective. Host could have it mapped above 4 GB, and= this is where you need translation.
 
3) Does translation h= ave to be 0 for Mem/MemAbove4G apertures in the PCI_ROOT_BRIDGE struct? Mos= t example platforms do that, but I'm not sure if that's a requirement for P= ciHostBridgeLib or just convention.
 
It depends on how your platform maps PCI apertures in the CPU address = space.
If an identity mapping is used (Host Address =3D=3D Device Address) - = ideally, then Translation is 0.
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