From mboxrd@z Thu Jan 1 00:00:00 1970 Subject: Re: [edk2-devel] [PATCH v1 3/5] UefiCpuPkg: Initial implementation of AMD's SmmCpuFeaturesLib To: Abdul Lateef Attar ,devel@edk2.groups.io From: "Chang, Abner" X-Originating-Location: TW (185.221.70.44) X-Originating-Platform: Windows Chrome 107 User-Agent: GROUPS.IO Web Poster MIME-Version: 1.0 Date: Wed, 07 Dec 2022 20:06:08 -0800 References: <6d3a8cd3b4c1080edfaa1e6cadeec3855e49b828.1670332633.git.abdattar@amd.com> In-Reply-To: <6d3a8cd3b4c1080edfaa1e6cadeec3855e49b828.1670332633.git.abdattar@amd.com> Message-ID: <22797.1670472368345917693@groups.io> Content-Type: multipart/alternative; boundary="44MKK8uShvN9u9MDDDiR" --44MKK8uShvN9u9MDDDiR Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Hi Abdul, Because SmmCpuFeatureLib is expected to only be used by X86 vendors, we can= just have SmmCpuFeaturesLib under the root of module directory and rename = it to AmdSmmCpuFeaturesLib.c Thanks Abner On Tue, Dec 6, 2022 at 09:23 PM, Abdul Lateef Attar wrote: >=20 > From: Abdul Lateef Attar >=20 > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4182 >=20 > Adds initial defination for AMD's SmmCpuFeaturesLib > library implementation. > All function's body either empty or just returns > value. Its initial skeleton of library implementation. >=20 > Cc: Paul Grimes > Cc: Garrett Kirkendall > Cc: Abner Chang > Cc: Eric Dong > Cc: Ray Ni > Cc: Rahul Kumar > Signed-off-by: Abdul Lateef Attar > --- > UefiCpuPkg/UefiCpuPkg.dsc | 9 + > .../AmdSmmCpuFeaturesLib.inf | 37 ++ > .../SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c | 357 ++++++++++++++++++ > 3 files changed, 403 insertions(+) > create mode 100644 > UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > create mode 100644 > UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c >=20 > diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc > index 67b0ce46e455..8aeaf992af9b 100644 > --- a/UefiCpuPkg/UefiCpuPkg.dsc > +++ b/UefiCpuPkg/UefiCpuPkg.dsc > @@ -2,6 +2,7 @@ > # UefiCpuPkg Package > # > # Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.
> +# Copyright (C) 2022 Advanced Micro Devices, Inc. All rights > reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -160,6 +161,7 @@ [Components.IA32, Components.X64] > UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.inf > UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.inf > UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.in= f >=20 > + UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf > UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf > UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf > @@ -176,6 +178,13 @@ [Components.IA32, Components.X64] > > SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibS= tm.inf >=20 > } > + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { > + > + FILE_GUID =3D B7242C74-BD21-49EE-84B4-07162E8C080D > + > + > SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesL= ib.inf >=20 > + > SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpu= PlatformHookLibNull.inf >=20 > + } > UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf > UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf > UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf > diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.in= f > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > new file mode 100644 > index 000000000000..08ac0262022f > --- /dev/null > +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > @@ -0,0 +1,37 @@ > +## @file > +# The CPU specific programming for PiSmmCpuDxeSmm module. > +# > +# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
> +# Copyright (C) 2022 Advanced Micro Devices, Inc. All rights > reserved.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D SmmCpuFeaturesLib > + MODULE_UNI_FILE =3D SmmCpuFeaturesLib.uni > + FILE_GUID =3D 5849E964-78EC-428E-8CBD-848A7E359134 > + MODULE_TYPE =3D DXE_SMM_DRIVER > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D SmmCpuFeaturesLib > + CONSTRUCTOR =3D SmmCpuFeaturesLibConstructor > + > +[Sources] > + SmmCpuFeaturesLib.c > + SmmCpuFeaturesLibCommon.c > + Amd/SmmCpuFeaturesLib.c > + > +[Packages] > + MdePkg/MdePkg.dec > + UefiCpuPkg/UefiCpuPkg.dec > + > +[LibraryClasses] > + BaseLib > + PcdLib > + MemoryAllocationLib > + DebugLib > + > +[FeaturePcd] > + gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable ## CONSUMES > + gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable ## CONSUMES > diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c > new file mode 100644 > index 000000000000..dc3fed0302d2 > --- /dev/null > +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c > @@ -0,0 +1,357 @@ > +/** @file > +Implementation specific to the SmmCpuFeatureLib library instance > +for AMD based platforms. > + > +Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
> +Copyright (c) Microsoft Corporation.
> +Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > + > +/** > + Read an SMM Save State register on the target processor. If this > function > + returns EFI_UNSUPPORTED, then the caller is responsible for reading the > + SMM Save Sate register. > + > + @param[in] CpuIndex The index of the CPU to read the SMM Save State. Th= e >=20 > + value must be between 0 and the NumberOfCpus field in > + the System Management System Table (SMST). > + @param[in] Register The SMM Save State register to read. > + @param[in] Width The number of bytes to read from the CPU save state. > + @param[out] Buffer Upon return, this holds the CPU register value read > + from the save state. > + > + @retval EFI_SUCCESS The register was read from Save State. > + @retval EFI_INVALID_PARAMTER Buffer is NULL. > + @retval EFI_UNSUPPORTED This function does not support reading Register= . >=20 > + > +**/ > +EFI_STATUS > +EFIAPI > +SmmCpuFeaturesReadSaveStateRegister ( > + IN UINTN CpuIndex, > + IN EFI_SMM_SAVE_STATE_REGISTER Register, > + IN UINTN Width, > + OUT VOID *Buffer > + ) > +{ > + return EFI_SUCCESS; > +} > + > +/** > + Writes an SMM Save State register on the target processor. If this > function > + returns EFI_UNSUPPORTED, then the caller is responsible for writing the > + SMM Save Sate register. > + > + @param[in] CpuIndex The index of the CPU to write the SMM Save State. > The > + value must be between 0 and the NumberOfCpus field in > + the System Management System Table (SMST). > + @param[in] Register The SMM Save State register to write. > + @param[in] Width The number of bytes to write to the CPU save state. > + @param[in] Buffer Upon entry, this holds the new CPU register value. > + > + @retval EFI_SUCCESS The register was written to Save State. > + @retval EFI_INVALID_PARAMTER Buffer is NULL. > + @retval EFI_UNSUPPORTED This function does not support writing Register= . >=20 > +**/ > +EFI_STATUS > +EFIAPI > +SmmCpuFeaturesWriteSaveStateRegister ( > + IN UINTN CpuIndex, > + IN EFI_SMM_SAVE_STATE_REGISTER Register, > + IN UINTN Width, > + IN CONST VOID *Buffer > + ) > +{ > + return EFI_SUCCESS; > +} > + > +/** > + Performs library initialization. > + > + This initialization function contains common functionality shared betwe= n > all > + library instance constructors. > + > +**/ > +VOID > +CpuFeaturesLibInitialization ( > + VOID > + ) > +{ > +} > + > +/** > + Called during the very first SMI into System Management Mode to > initialize > + CPU features, including SMBASE, for the currently executing CPU. Since > this > + is the first SMI, the SMRAM Save State Map is at the default address of > + AMD_SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently > executing > + CPU is specified by CpuIndex and CpuIndex can be used to access > information > + about the currently executing CPU in the ProcessorInfo array and the > + HotPlugCpuData data structure. > + > + @param[in] CpuIndex The index of the CPU to initialize. The value > + must be between 0 and the NumberOfCpus field in > + the System Management System Table (SMST). > + @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that > + was elected as monarch during System Management > + Mode initialization. > + FALSE if the CpuIndex is not the index of the CPU > + that was elected as monarch during System > + Management Mode initialization. > + @param[in] ProcessorInfo Pointer to an array of > EFI_PROCESSOR_INFORMATION > + structures. ProcessorInfo[CpuIndex] contains the > + information for the currently executing CPU. > + @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure > that > + contains the ApidId and SmBase arrays. > +**/ > +VOID > +EFIAPI > +SmmCpuFeaturesInitializeProcessor ( > + IN UINTN CpuIndex, > + IN BOOLEAN IsMonarch, > + IN EFI_PROCESSOR_INFORMATION *ProcessorInfo, > + IN CPU_HOT_PLUG_DATA *CpuHotPlugData > + ) > +{ > +} > + > +/** > + This function updates the SMRAM save state on the currently executing > CPU > + to resume execution at a specific address after an RSM instruction. Thi= s >=20 > + function must evaluate the SMRAM save state to determine the execution > mode > + the RSM instruction resumes and update the resume execution address wit= h >=20 > + either NewInstructionPointer32 or NewInstructionPoint. The auto HALT > restart > + flag in the SMRAM save state must always be cleared. This function > returns > + the value of the instruction pointer from the SMRAM save state that was > + replaced. If this function returns 0, then the SMRAM save state was not > + modified. > + > + This function is called during the very first SMI on each CPU after > + SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution > mode > + to signal that the SMBASE of each CPU has been updated before the > default > + SMBASE address is used for the first SMI to the next CPU. > + > + @param[in] CpuIndex The index of the CPU to hook. The value > + must be between 0 and the NumberOfCpus > + field in the System Management System Table > + (SMST). > + @param[in] CpuState Pointer to SMRAM Save State Map for the > + currently executing CPU. > + @param[in] NewInstructionPointer32 Instruction pointer to use if > resuming to > + 32-bit execution mode from 64-bit SMM. > + @param[in] NewInstructionPointer Instruction pointer to use if resuming > to > + same execution mode as SMM. > + > + @retval 0 This function did modify the SMRAM save state. > + @retval > 0 The original instruction pointer value from the SMRAM save > state > + before it was replaced. > +**/ > +UINT64 > +EFIAPI > +SmmCpuFeaturesHookReturnFromSmm ( > + IN UINTN CpuIndex, > + IN SMRAM_SAVE_STATE_MAP *CpuState, > + IN UINT64 NewInstructionPointer32, > + IN UINT64 NewInstructionPointer > + ) > +{ > + return 0; > +} > + > +/** > + Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is > + returned, then a custom SMI handler is not provided by this library, > + and the default SMI handler must be used. > + > + @retval 0 Use the default SMI handler. > + @retval > 0 Use the SMI handler installed by > SmmCpuFeaturesInstallSmiHandler() > + The caller is required to allocate enough SMRAM for each CPU to > + support the size of the custom SMI handler. > +**/ > +UINTN > +EFIAPI > +SmmCpuFeaturesGetSmiHandlerSize ( > + VOID > + ) > +{ > + return 0; > +} > + > +/** > + Install a custom SMI handler for the CPU specified by CpuIndex. This > function > + is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is > greater > + than zero and is called by the CPU that was elected as monarch during > System > + Management Mode initialization. > + > + @param[in] CpuIndex The index of the CPU to install the custom SMI > handler. > + The value must be between 0 and the NumberOfCpus field > + in the System Management System Table (SMST). > + @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex. > + @param[in] SmiStack The stack to use when an SMI is processed by the > + the CPU specified by CpuIndex. > + @param[in] StackSize The size, in bytes, if the stack used when an SMI > is > + processed by the CPU specified by CpuIndex. > + @param[in] GdtBase The base address of the GDT to use when an SMI is > + processed by the CPU specified by CpuIndex. > + @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is > + processed by the CPU specified by CpuIndex. > + @param[in] IdtBase The base address of the IDT to use when an SMI is > + processed by the CPU specified by CpuIndex. > + @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is > + processed by the CPU specified by CpuIndex. > + @param[in] Cr3 The base address of the page tables to use when an SMI > + is processed by the CPU specified by CpuIndex. > +**/ > +VOID > +EFIAPI > +SmmCpuFeaturesInstallSmiHandler ( > + IN UINTN CpuIndex, > + IN UINT32 SmBase, > + IN VOID *SmiStack, > + IN UINTN StackSize, > + IN UINTN GdtBase, > + IN UINTN GdtSize, > + IN UINTN IdtBase, > + IN UINTN IdtSize, > + IN UINT32 Cr3 > + ) > +{ > +} > + > +/** > + Determines if MTRR registers must be configured to set SMRAM > cache-ability > + when executing in System Management Mode. > + > + @retval TRUE MTRR registers must be configured to set SMRAM > cache-ability. > + @retval FALSE MTRR registers do not need to be configured to set SMRAM > + cache-ability. > +**/ > +BOOLEAN > +EFIAPI > +SmmCpuFeaturesNeedConfigureMtrrs ( > + VOID > + ) > +{ > + return FALSE; > +} > + > +/** > + Disable SMRR register if SMRR is supported and > SmmCpuFeaturesNeedConfigureMtrrs() > + returns TRUE. > +**/ > +VOID > +EFIAPI > +SmmCpuFeaturesDisableSmrr ( > + VOID > + ) > +{ > +} > + > +/** > + Enable SMRR register if SMRR is supported and > SmmCpuFeaturesNeedConfigureMtrrs() > + returns TRUE. > +**/ > +VOID > +EFIAPI > +SmmCpuFeaturesReenableSmrr ( > + VOID > + ) > +{ > +} > + > +/** > + Processor specific hook point each time a CPU enters System Management > Mode. > + > + @param[in] CpuIndex The index of the CPU that has entered SMM. The valu= e >=20 > + must be between 0 and the NumberOfCpus field in the > + System Management System Table (SMST). > +**/ > +VOID > +EFIAPI > +SmmCpuFeaturesRendezvousEntry ( > + IN UINTN CpuIndex > + ) > +{ > +} > + > +/** > + Returns the current value of the SMM register for the specified CPU. > + If the SMM register is not supported, then 0 is returned. > + > + @param[in] CpuIndex The index of the CPU to read the SMM register. The > + value must be between 0 and the NumberOfCpus field in > + the System Management System Table (SMST). > + @param[in] RegName Identifies the SMM register to read. > + > + @return The value of the SMM register specified by RegName from the CPU > + specified by CpuIndex. > +**/ > +UINT64 > +EFIAPI > +SmmCpuFeaturesGetSmmRegister ( > + IN UINTN CpuIndex, > + IN SMM_REG_NAME RegName > + ) > +{ > + return 0; > +} > + > +/** > + Sets the value of an SMM register on a specified CPU. > + If the SMM register is not supported, then no action is performed. > + > + @param[in] CpuIndex The index of the CPU to write the SMM register. The > + value must be between 0 and the NumberOfCpus field in > + the System Management System Table (SMST). > + @param[in] RegName Identifies the SMM register to write. > + registers are read-only. > + @param[in] Value The value to write to the SMM register. > +**/ > +VOID > +EFIAPI > +SmmCpuFeaturesSetSmmRegister ( > + IN UINTN CpuIndex, > + IN SMM_REG_NAME RegName, > + IN UINT64 Value > + ) > +{ > +} > + > +/** > + Check to see if an SMM register is supported by a specified CPU. > + > + @param[in] CpuIndex The index of the CPU to check for SMM register > support. > + The value must be between 0 and the NumberOfCpus field > + in the System Management System Table (SMST). > + @param[in] RegName Identifies the SMM register to check for support. > + > + @retval TRUE The SMM register specified by RegName is supported by the > CPU > + specified by CpuIndex. > + @retval FALSE The SMM register specified by RegName is not supported by > the > + CPU specified by CpuIndex. > +**/ > +BOOLEAN > +EFIAPI > +SmmCpuFeaturesIsSmmRegisterSupported ( > + IN UINTN CpuIndex, > + IN SMM_REG_NAME RegName > + ) > +{ > + return FALSE; > +} > + > +/** > + This function is hook point called after the > gEfiSmmReadyToLockProtocolGuid > + notification is completely processed. > +**/ > +VOID > +EFIAPI > +SmmCpuFeaturesCompleteSmmReadyToLock ( > + VOID > + ) > +{ > +} > -- > 2.25.1 --44MKK8uShvN9u9MDDDiR Content-Type: text/html; charset="utf-8" Content-Transfer-Encoding: quoted-printable Hi Abdul,
Because SmmCpuFeatureLib is expected to only be used by X86 = vendors, we can just have SmmCpuFeaturesLib under the root of module direct= ory and rename it to AmdSmmCpuFeaturesLib.c
Thanks
Abner
On Tue, Dec 6, 2022 at 09:23 PM, Abdul Lateef Attar wrote:
From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>

BZ: https://bugzilla.tianocore.org/show_bu= g.cgi?id=3D4182

Adds initial defination for AMD's SmmCpuFeat= uresLib
library implementation.
All function's body either empty = or just returns
value. Its initial skeleton of library implementation.=

Cc: Paul Grimes <paul.grimes@amd.com>
Cc: Garrett Ki= rkendall <garrett.kirkendall@amd.com>
Cc: Abner Chang <abner.= chang@amd.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: R= ay Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.= com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.co= m>
---
UefiCpuPkg/UefiCpuPkg.dsc | 9 +
.../AmdSmmCpuFeatu= resLib.inf | 37 ++
.../SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c | 357= ++++++++++++++++++
3 files changed, 403 insertions(+)
create mod= e 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeatures= Lib.c

diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCp= uPkg.dsc
index 67b0ce46e455..8aeaf992af9b 100644
--- a/UefiCpuPkg= /UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -2,6 +2,7 @@# UefiCpuPkg Package
#
# Copyright (c) 2007 - 2022, Intel Cor= poration. All rights reserved.<BR>
+# Copyright (C) 2022 Advance= d Micro Devices, Inc. All rights reserved.<BR>
#
# SPDX-Lic= ense-Identifier: BSD-2-Clause-Patent
#
@@ -160,6 +161,7 @@ [Compo= nents.IA32, Components.X64]
UefiCpuPkg/Library/RegisterCpuFeaturesLib/= PeiRegisterCpuFeaturesLib.inf
UefiCpuPkg/Library/RegisterCpuFeaturesLi= b/DxeRegisterCpuFeaturesLib.inf
UefiCpuPkg/Library/SmmCpuPlatformHookL= ibNull/SmmCpuPlatformHookLibNull.inf
+ UefiCpuPkg/Library/SmmCpuFeatur= esLib/AmdSmmCpuFeaturesLib.inf
UefiCpuPkg/Library/SmmCpuFeaturesLib/Sm= mCpuFeaturesLib.inf
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeature= sLibStm.inf
UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeatur= esLib.inf
@@ -176,6 +178,13 @@ [Components.IA32, Components.X64]
= <LibraryClasses>
SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeat= uresLib/SmmCpuFeaturesLibStm.inf
}
+ UefiCpuPkg/PiSmmCpuDxeSmm/Pi= SmmCpuDxeSmm.inf {
+ <Defines>
+ FILE_GUID =3D B7242C74-BD2= 1-49EE-84B4-07162E8C080D
+ <LibraryClasses>
+ SmmCpuFeature= sLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
+ S= mmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPla= tformHookLibNull.inf
+ }
UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S= 3Resume2Pei.inf
UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf
U= efiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf
diff --g= it a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf b/UefiCp= uPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
new file mode = 100644
index 000000000000..08ac0262022f
--- /dev/null
+++ b/= UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
@@ -0,0 = +1,37 @@
+## @file
+# The CPU specific programming for PiSmmCpuDx= eSmm module.
+#
+# Copyright (c) 2009 - 2016, Intel Corporation. = All rights reserved.<BR>
+# Copyright (C) 2022 Advanced Micro De= vices, Inc. All rights reserved.<BR>
+# SPDX-License-Identifier:= BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VER= SION =3D 0x00010005
+ BASE_NAME =3D SmmCpuFeaturesLib
+ MODULE_UN= I_FILE =3D SmmCpuFeaturesLib.uni
+ FILE_GUID =3D 5849E964-78EC-428E-8C= BD-848A7E359134
+ MODULE_TYPE =3D DXE_SMM_DRIVER
+ VERSION_STRING= =3D 1.0
+ LIBRARY_CLASS =3D SmmCpuFeaturesLib
+ CONSTRUCTOR =3D = SmmCpuFeaturesLibConstructor
+
+[Sources]
+ SmmCpuFeaturesLi= b.c
+ SmmCpuFeaturesLibCommon.c
+ Amd/SmmCpuFeaturesLib.c
+<= br />+[Packages]
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec<= br />+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ MemoryAll= ocationLib
+ DebugLib
+
+[FeaturePcd]
+ gUefiCpuPkgToke= nSpaceGuid.PcdSmrrEnable ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdSm= mFeatureControlEnable ## CONSUMES
diff --git a/UefiCpuPkg/Library/SmmC= puFeaturesLib/Amd/SmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLi= b/Amd/SmmCpuFeaturesLib.c
new file mode 100644
index 000000000000= ..dc3fed0302d2
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeatu= resLib/Amd/SmmCpuFeaturesLib.c
@@ -0,0 +1,357 @@
+/** @file
= +Implementation specific to the SmmCpuFeatureLib library instance
+for= AMD based platforms.
+
+Copyright (c) 2010 - 2019, Intel Corpora= tion. All rights reserved.<BR>
+Copyright (c) Microsoft Corporat= ion.<BR>
+Copyright (C) 2022 Advanced Micro Devices, Inc. All ri= ghts reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent=
+
+**/
+
+#include <Library/SmmCpuFeaturesLib.h>=
+#include <Uefi/UefiBaseType.h>
+
+/**
+ Read an= SMM Save State register on the target processor. If this function
+ r= eturns EFI_UNSUPPORTED, then the caller is responsible for reading the
+ SMM Save Sate register.
+
+ @param[in] CpuIndex The index of t= he CPU to read the SMM Save State. The
+ value must be between 0 and t= he NumberOfCpus field in
+ the System Management System Table (SMST).<= br />+ @param[in] Register The SMM Save State register to read.
+ @par= am[in] Width The number of bytes to read from the CPU save state.
+ @p= aram[out] Buffer Upon return, this holds the CPU register value read
+= from the save state.
+
+ @retval EFI_SUCCESS The register was re= ad from Save State.
+ @retval EFI_INVALID_PARAMTER Buffer is NULL.
+ @retval EFI_UNSUPPORTED This function does not support reading Register= .
+
+**/
+EFI_STATUS
+EFIAPI
+SmmCpuFeaturesReadSa= veStateRegister (
+ IN UINTN CpuIndex,
+ IN EFI_SMM_SAVE_STATE_RE= GISTER Register,
+ IN UINTN Width,
+ OUT VOID *Buffer
+ )+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Writes an = SMM Save State register on the target processor. If this function
+ re= turns EFI_UNSUPPORTED, then the caller is responsible for writing the
= + SMM Save Sate register.
+
+ @param[in] CpuIndex The index of th= e CPU to write the SMM Save State. The
+ value must be between 0 and t= he NumberOfCpus field in
+ the System Management System Table (SMST).<= br />+ @param[in] Register The SMM Save State register to write.
+ @pa= ram[in] Width The number of bytes to write to the CPU save state.
+ @p= aram[in] Buffer Upon entry, this holds the new CPU register value.
++ @retval EFI_SUCCESS The register was written to Save State.
+ @r= etval EFI_INVALID_PARAMTER Buffer is NULL.
+ @retval EFI_UNSUPPORTED T= his function does not support writing Register.
+**/
+EFI_STATUS<= br />+EFIAPI
+SmmCpuFeaturesWriteSaveStateRegister (
+ IN UINTN C= puIndex,
+ IN EFI_SMM_SAVE_STATE_REGISTER Register,
+ IN UINTN Wi= dth,
+ IN CONST VOID *Buffer
+ )
+{
+ return EFI_SUCCES= S;
+}
+
+/**
+ Performs library initialization.
+<= br />+ This initialization function contains common functionality shared be= twen all
+ library instance constructors.
+
+**/
+VOID<= br />+CpuFeaturesLibInitialization (
+ VOID
+ )
+{
+}+
+/**
+ Called during the very first SMI into System Managem= ent Mode to initialize
+ CPU features, including SMBASE, for the curre= ntly executing CPU. Since this
+ is the first SMI, the SMRAM Save Stat= e Map is at the default address of
+ AMD_SMM_DEFAULT_SMBASE + SMRAM_SA= VE_STATE_MAP_OFFSET. The currently executing
+ CPU is specified by Cpu= Index and CpuIndex can be used to access information
+ about the curre= ntly executing CPU in the ProcessorInfo array and the
+ HotPlugCpuData= data structure.
+
+ @param[in] CpuIndex The index of the CPU to = initialize. The value
+ must be between 0 and the NumberOfCpus field i= n
+ the System Management System Table (SMST).
+ @param[in] IsMon= arch TRUE if the CpuIndex is the index of the CPU that
+ was elected a= s monarch during System Management
+ Mode initialization.
+ FALSE= if the CpuIndex is not the index of the CPU
+ that was elected as mon= arch during System
+ Management Mode initialization.
+ @param[in]= ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION
+ stru= ctures. ProcessorInfo[CpuIndex] contains the
+ information for the cur= rently executing CPU.
+ @param[in] CpuHotPlugData Pointer to the CPU_H= OT_PLUG_DATA structure that
+ contains the ApidId and SmBase arrays.+**/
+VOID
+EFIAPI
+SmmCpuFeaturesInitializeProcessor (<= br />+ IN UINTN CpuIndex,
+ IN BOOLEAN IsMonarch,
+ IN EFI_PROCES= SOR_INFORMATION *ProcessorInfo,
+ IN CPU_HOT_PLUG_DATA *CpuHotPlugData=
+ )
+{
+}
+
+/**
+ This function updates the= SMRAM save state on the currently executing CPU
+ to resume execution= at a specific address after an RSM instruction. This
+ function must = evaluate the SMRAM save state to determine the execution mode
+ the RS= M instruction resumes and update the resume execution address with
+ e= ither NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart=
+ flag in the SMRAM save state must always be cleared. This function = returns
+ the value of the instruction pointer from the SMRAM save sta= te that was
+ replaced. If this function returns 0, then the SMRAM sav= e state was not
+ modified.
+
+ This function is called duri= ng the very first SMI on each CPU after
+ SmmCpuFeaturesInitializeProc= essor() to set a flag in normal execution mode
+ to signal that the SM= BASE of each CPU has been updated before the default
+ SMBASE address = is used for the first SMI to the next CPU.
+
+ @param[in] CpuInde= x The index of the CPU to hook. The value
+ must be between 0 and the = NumberOfCpus
+ field in the System Management System Table
+ (SMS= T).
+ @param[in] CpuState Pointer to SMRAM Save State Map for the
+ currently executing CPU.
+ @param[in] NewInstructionPointer32 Instr= uction pointer to use if resuming to
+ 32-bit execution mode from 64-b= it SMM.
+ @param[in] NewInstructionPointer Instruction pointer to use = if resuming to
+ same execution mode as SMM.
+
+ @retval 0 T= his function did modify the SMRAM save state.
+ @retval > 0 The ori= ginal instruction pointer value from the SMRAM save state
+ before it = was replaced.
+**/
+UINT64
+EFIAPI
+SmmCpuFeaturesHookR= eturnFromSmm (
+ IN UINTN CpuIndex,
+ IN SMRAM_SAVE_STATE_MAP *Cp= uState,
+ IN UINT64 NewInstructionPointer32,
+ IN UINT64 NewInstr= uctionPointer
+ )
+{
+ return 0;
+}
+
+/**+ Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is+ returned, then a custom SMI handler is not provided by this library,<= br />+ and the default SMI handler must be used.
+
+ @retval 0 Us= e the default SMI handler.
+ @retval > 0 Use the SMI handler instal= led by SmmCpuFeaturesInstallSmiHandler()
+ The caller is required to a= llocate enough SMRAM for each CPU to
+ support the size of the custom = SMI handler.
+**/
+UINTN
+EFIAPI
+SmmCpuFeaturesGetSmiH= andlerSize (
+ VOID
+ )
+{
+ return 0;
+}
++/**
+ Install a custom SMI handler for the CPU specified by CpuIn= dex. This function
+ is only called if SmmCpuFeaturesGetSmiHandlerSize= () returns a size is greater
+ than zero and is called by the CPU that= was elected as monarch during System
+ Management Mode initialization= .
+
+ @param[in] CpuIndex The index of the CPU to install the cus= tom SMI handler.
+ The value must be between 0 and the NumberOfCpus fi= eld
+ in the System Management System Table (SMST).
+ @param[in] = SmBase The SMBASE address for the CPU specified by CpuIndex.
+ @param[= in] SmiStack The stack to use when an SMI is processed by the
+ the CP= U specified by CpuIndex.
+ @param[in] StackSize The size, in bytes, if= the stack used when an SMI is
+ processed by the CPU specified by Cpu= Index.
+ @param[in] GdtBase The base address of the GDT to use when an= SMI is
+ processed by the CPU specified by CpuIndex.
+ @param[in= ] GdtSize The size, in bytes, of the GDT used when an SMI is
+ process= ed by the CPU specified by CpuIndex.
+ @param[in] IdtBase The base add= ress of the IDT to use when an SMI is
+ processed by the CPU specified= by CpuIndex.
+ @param[in] IdtSize The size, in bytes, of the IDT used= when an SMI is
+ processed by the CPU specified by CpuIndex.
+ @= param[in] Cr3 The base address of the page tables to use when an SMI
+= is processed by the CPU specified by CpuIndex.
+**/
+VOID
+= EFIAPI
+SmmCpuFeaturesInstallSmiHandler (
+ IN UINTN CpuIndex,+ IN UINT32 SmBase,
+ IN VOID *SmiStack,
+ IN UINTN StackSize,=
+ IN UINTN GdtBase,
+ IN UINTN GdtSize,
+ IN UINTN IdtBase,=
+ IN UINTN IdtSize,
+ IN UINT32 Cr3
+ )
+{
+}
+
+/**
+ Determines if MTRR registers must be configured to set= SMRAM cache-ability
+ when executing in System Management Mode.
= +
+ @retval TRUE MTRR registers must be configured to set SMRAM cache-= ability.
+ @retval FALSE MTRR registers do not need to be configured t= o set SMRAM
+ cache-ability.
+**/
+BOOLEAN
+EFIAPI
+SmmCpuFeaturesNeedConfigureMtrrs (
+ VOID
+ )
+{
+ re= turn FALSE;
+}
+
+/**
+ Disable SMRR register if SMRR i= s supported and SmmCpuFeaturesNeedConfigureMtrrs()
+ returns TRUE.
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesDisableSmrr (
+ VOI= D
+ )
+{
+}
+
+/**
+ Enable SMRR register if = SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
+ returns TRU= E.
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesReenableSmrr (
+ VOID
+ )
+{
+}
+
+/**
+ Processor specifi= c hook point each time a CPU enters System Management Mode.
+
+ @= param[in] CpuIndex The index of the CPU that has entered SMM. The value
+ must be between 0 and the NumberOfCpus field in the
+ System Manag= ement System Table (SMST).
+**/
+VOID
+EFIAPI
+SmmCpuFe= aturesRendezvousEntry (
+ IN UINTN CpuIndex
+ )
+{
+}+
+/**
+ Returns the current value of the SMM register for th= e specified CPU.
+ If the SMM register is not supported, then 0 is ret= urned.
+
+ @param[in] CpuIndex The index of the CPU to read the S= MM register. The
+ value must be between 0 and the NumberOfCpus field = in
+ the System Management System Table (SMST).
+ @param[in] RegN= ame Identifies the SMM register to read.
+
+ @return The value of= the SMM register specified by RegName from the CPU
+ specified by Cpu= Index.
+**/
+UINT64
+EFIAPI
+SmmCpuFeaturesGetSmmRegist= er (
+ IN UINTN CpuIndex,
+ IN SMM_REG_NAME RegName
+ )
+{
+ return 0;
+}
+
+/**
+ Sets the value of an S= MM register on a specified CPU.
+ If the SMM register is not supported= , then no action is performed.
+
+ @param[in] CpuIndex The index = of the CPU to write the SMM register. The
+ value must be between 0 an= d the NumberOfCpus field in
+ the System Management System Table (SMST= ).
+ @param[in] RegName Identifies the SMM register to write.
+ r= egisters are read-only.
+ @param[in] Value The value to write to the S= MM register.
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesSetSmmRe= gister (
+ IN UINTN CpuIndex,
+ IN SMM_REG_NAME RegName,
+ I= N UINT64 Value
+ )
+{
+}
+
+/**
+ Check to se= e if an SMM register is supported by a specified CPU.
+
+ @param[= in] CpuIndex The index of the CPU to check for SMM register support.
+= The value must be between 0 and the NumberOfCpus field
+ in the Syste= m Management System Table (SMST).
+ @param[in] RegName Identifies the = SMM register to check for support.
+
+ @retval TRUE The SMM regis= ter specified by RegName is supported by the CPU
+ specified by CpuInd= ex.
+ @retval FALSE The SMM register specified by RegName is not suppo= rted by the
+ CPU specified by CpuIndex.
+**/
+BOOLEAN
= +EFIAPI
+SmmCpuFeaturesIsSmmRegisterSupported (
+ IN UINTN CpuInd= ex,
+ IN SMM_REG_NAME RegName
+ )
+{
+ return FALSE;+}
+
+/**
+ This function is hook point called after the = gEfiSmmReadyToLockProtocolGuid
+ notification is completely processed.=
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesCompleteSmmReadyToLo= ck (
+ VOID
+ )
+{
+}
--
2.25.1
--44MKK8uShvN9u9MDDDiR--