From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B1700820A2 for ; Wed, 8 Feb 2017 02:38:57 -0800 (PST) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP; 08 Feb 2017 02:38:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,346,1477983600"; d="dat'59?scan'59,208,59";a="62569835" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga005.fm.intel.com with ESMTP; 08 Feb 2017 02:38:57 -0800 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 8 Feb 2017 02:38:56 -0800 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.20]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.177]) with mapi id 14.03.0248.002; Wed, 8 Feb 2017 18:38:54 +0800 From: "Guo, Mang" To: "edk2-devel@lists.01.org" CC: "Lu, ShifeiX A" , "Wei, David" Thread-Topic: [Patch][edk2-platforms/devel-MinnowBoard3] Change MRC parameter Thread-Index: AdKB94r7WllvChb/T6WKJtsHTbjhFg== Date: Wed, 8 Feb 2017 10:38:53 +0000 Message-ID: <22D2C85ED001C54AA20BFE3B0E4751D1524D7161@SHSMSX103.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: <22D2C85ED001C54AA20BFE3B0E4751D1524D7161@SHSMSX103.ccr.corp.intel.com> x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.21 Subject: [Patch][edk2-platforms/devel-MinnowBoard3] Change MRC parameter X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 08 Feb 2017 10:38:57 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable These code cause HDMI cable of some vendor couldn't work. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang --- .../LeafHill/BoardInitPreMem/BoardInitMiscs.c | 17 +----- .../LeafHill/BoardInitPreMem/BoardInitPreMem.inf | 1 - .../MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c | 17 +----- .../BoardInitPreMem/BoardInitPreMem.inf | 1 - .../BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h | 5 +- .../MemoryInit/BXT/Include/MrcEfiDefinitions.h | 5 +- .../Mmrc/ProjectIndependent/Include/MmrcData.h | 67 ++----------------= ---- 7 files changed, 13 insertions(+), 100 deletions(-) diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/Boa= rdInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/= BoardInitMiscs.c index fe8ece0..5af2fae 100644 --- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitM= iscs.c +++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitM= iscs.c @@ -14,7 +14,6 @@ **/ =20 #include "BoardInitMiscs.h" -#include "MmrcData.h" =20 UPDATE_FSPM_UPD_FUNC mLhUpdateFspmUpdPtr =3D LhUpdateFspmUpd; DRAM_CREATE_POLICY_DEFAULTS_FUNC mLhDramCreatePolicyDefaultsPtr =3D LhDr= amCreatePolicyDefaults; @@ -30,9 +29,6 @@ LhUpdateFspmUpd ( EFI_PLATFORM_INFO_HOB *PlatformInfo =3D NULL; DRAM_POLICY_PPI *DramPolicy; EFI_STATUS Status; - MRC_NV_DATA_FRAME *MrcNvData; - MRC_PARAMS_SAVE_RESTORE *MrcParamsHob; - BOOT_VARIABLE_NV_DATA *BootVariableNvDataHob; =20 Status =3D (*PeiServices)->LocatePpi ( PeiServices, @@ -68,20 +64,11 @@ LhUpdateFspmUpd ( FspUpdRgn->FspmConfig.InterleavedMode =3D DramPolicy= ->InterleavedMode; FspUpdRgn->FspmConfig.MinRefRate2xEnable =3D DramPolicy= ->MinRefRate2xEnabled; FspUpdRgn->FspmConfig.DualRankSupportEnable =3D DramPolicy= ->DualRankSupportEnabled; + FspUpdRgn->FspmArchUpd.NvsBufferPtr =3D (VOID *)(U= INT32)DramPolicy->MrcTrainingDataPtr; + FspUpdRgn->FspmConfig.MrcBootDataPtr =3D (VOID *)(U= INT32)DramPolicy->MrcBootDataPtr; =20 CopyMem (&(FspUpdRgn->FspmConfig.Ch0_RankEnable), &DramPolicy->ChDrp, = sizeof (DramPolicy->ChDrp)); CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), &DramPolicy->ChSw= izzle, sizeof (DramPolicy->ChSwizzle)); - - if (((VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr !=3D 0) && - ((VOID *)(UINT32)DramPolicy->MrcBootDataPtr !=3D 0)) { - MrcNvData =3D (MRC_NV_DATA_FRAME *) AllocateZeroPool (sizeof (MRC_NV= _DATA_FRAME)); - MrcParamsHob =3D (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcT= rainingDataPtr); - BootVariableNvDataHob =3D (BOOT_VARIABLE_NV_DATA*)((UINT32)DramPolic= y->MrcBootDataPtr); - CopyMem(&(MrcNvData->MrcParamsSaveRestore), MrcParamsHob, sizeof (MR= C_PARAMS_SAVE_RESTORE)); - CopyMem(&(MrcNvData->BootVariableNvData), BootVariableNvDataHob, siz= eof (BOOT_VARIABLE_NV_DATA)); - FspUpdRgn->FspmArchUpd.NvsBufferPtr =3D (VOID *)(UINT32)MrcNvData; - } - } // // override RankEnable settings for Minnow diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/Boa= rdInitPreMem.inf b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreM= em/BoardInitPreMem.inf index c526bc2..c170839 100644 --- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitP= reMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitP= reMem.inf @@ -39,7 +39,6 @@ IntelFsp2Pkg/IntelFsp2Pkg.dec BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/IntelFsp2Wrappe= rPkg.dec IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec - Silicon\BroxtonSoC\BroxtonSiPkg\NorthCluster\MemoryInit\MemoryInit.dec =20 [Pcd] gPlatformModuleTokenSpaceGuid.PcdBoardId diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem= /BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardIni= tPreMem/BoardInitMiscs.c index 9e535ca..ece8a88 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardI= nitMiscs.c +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardI= nitMiscs.c @@ -14,7 +14,6 @@ **/ =20 #include "BoardInitMiscs.h" -#include "MmrcData.h" =20 UPDATE_FSPM_UPD_FUNC mMb3UpdateFspmUpdPtr =3D Mb3UpdateFspmUpd; DRAM_CREATE_POLICY_DEFAULTS_FUNC mMb3DramCreatePolicyDefaultsPtr =3D Mb3= DramCreatePolicyDefaults; @@ -30,9 +29,6 @@ Mb3UpdateFspmUpd ( EFI_PLATFORM_INFO_HOB *PlatformInfo =3D NULL; DRAM_POLICY_PPI *DramPolicy; EFI_STATUS Status; - MRC_NV_DATA_FRAME *MrcNvData; - MRC_PARAMS_SAVE_RESTORE *MrcParamsHob; - BOOT_VARIABLE_NV_DATA *BootVariableNvDataHob; =20 Status =3D (*PeiServices)->LocatePpi ( PeiServices, @@ -68,20 +64,11 @@ Mb3UpdateFspmUpd ( FspUpdRgn->FspmConfig.InterleavedMode =3D DramPolicy= ->InterleavedMode; FspUpdRgn->FspmConfig.MinRefRate2xEnable =3D DramPolicy= ->MinRefRate2xEnabled; FspUpdRgn->FspmConfig.DualRankSupportEnable =3D DramPolicy= ->DualRankSupportEnabled; + FspUpdRgn->FspmArchUpd.NvsBufferPtr =3D (VOID *)(U= INT32)DramPolicy->MrcTrainingDataPtr; + FspUpdRgn->FspmConfig.MrcBootDataPtr =3D (VOID *)(U= INT32)DramPolicy->MrcBootDataPtr; =20 CopyMem (&(FspUpdRgn->FspmConfig.Ch0_RankEnable), &DramPolicy->ChDrp, = sizeof(DramPolicy->ChDrp)); CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), &DramPolicy->ChSw= izzle, sizeof (DramPolicy->ChSwizzle)); - - if (((VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr !=3D 0) && - ((VOID *)(UINT32)DramPolicy->MrcBootDataPtr !=3D 0)) { - MrcNvData =3D (MRC_NV_DATA_FRAME *) AllocateZeroPool (sizeof (MRC_NV= _DATA_FRAME)); - MrcParamsHob =3D (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcT= rainingDataPtr); - BootVariableNvDataHob =3D (BOOT_VARIABLE_NV_DATA*)((UINT32)DramPolic= y->MrcBootDataPtr); - CopyMem(&(MrcNvData->MrcParamsSaveRestore), MrcParamsHob, sizeof (MR= C_PARAMS_SAVE_RESTORE)); - CopyMem(&(MrcNvData->BootVariableNvData), BootVariableNvDataHob, siz= eof (BOOT_VARIABLE_NV_DATA)); - FspUpdRgn->FspmArchUpd.NvsBufferPtr =3D (VOID *)(UINT32)MrcNvData; - } - } // // override RankEnable settings for Minnow diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem= /BoardInitPreMem.inf b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/Board= InitPreMem/BoardInitPreMem.inf index 9135fb8..f64ab8f 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardI= nitPreMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardI= nitPreMem.inf @@ -39,7 +39,6 @@ IntelFsp2Pkg/IntelFsp2Pkg.dec BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/IntelFsp2Wrappe= rPkg.dec IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec - Silicon\BroxtonSoC\BroxtonSiPkg\NorthCluster\MemoryInit\MemoryInit.dec =20 [Pcd] gPlatformModuleTokenSpaceGuid.PcdBoardId diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h b/= Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h index 6d610a5..7eb0e92 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h @@ -1,9 +1,8 @@ - /** @file Dram Policy PPI is used for specifying platform related Intel silicon information and policy setting. =20 - Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -57,12 +56,10 @@ typedef struct { UINT8 RmtMode; UINT8 RmtCheckRun; UINT16 RmtMarginCheckScaleHighThreshold; - UINT8 Reserved1; UINT32 MsgLevelMask; UINT8 SpdAddress[DRAM_POLICY_NUMBER_SPD_ADDRESSES]; UINT8 ChSwizzle[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY= _NUMBER_BITS]; DRP_DRAM_POLICY ChDrp[DRAM_POLICY_NUMBER_CHANNELS]; - UINT8 Reserved2; UINT8 DebugMsgLevel; UINT8 reserved[13]; } DRAM_POLICY_PPI; diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/In= clude/MrcEfiDefinitions.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Me= moryInit/BXT/Include/MrcEfiDefinitions.h index 1bf9d0f..b19d6a0 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/M= rcEfiDefinitions.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/M= rcEfiDefinitions.h @@ -1,5 +1,5 @@ /** @file - Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+ - Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved. =20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -64,12 +64,10 @@ typedef struct { UINT8 RmtMode; UINT8 RmtCheckRun; UINT16 RmtMarginCheckScaleHighThreshold; - UINT8 Reserved1; UINT32 MsgLevelMask; UINT8 SpdAddress[DRAM_POLICY_NUMBER_SPD_ADDRESSES]; UINT8 ChSwizzle[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY= _NUMBER_BITS]; DRP_DRAM_POLICY ChDrp[DRAM_POLICY_NUMBER_CHANNELS]; - UINT8 Reserved2; UINT8 DebugMsgLevel; UINT8 reserved[13]; } DRAM_POLICY_PPI; @@ -81,6 +79,7 @@ typedef struct { typedef enum { Bxt =3D 0x00, Bxt1, + BxtX, BxtP, BxtSeriesMax =3D 0xFF } BXT_SERIES; diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/P= rojectIndependent/Include/MmrcData.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Nort= hCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h index 5f65ba7..0d64528 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectI= ndependent/Include/MmrcData.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectI= ndependent/Include/MmrcData.h @@ -28,9 +28,10 @@ #define UINTX UINT32 #endif typedef UINT32 MMRC_STATUS; -/// -/// MRC version description. -/// + +// +// MRC version description. +// typedef union { struct{ UINT8 Major; ///< Major version number @@ -51,60 +52,6 @@ typedef union { UINT8 Data8[4]; } MrcVersion; =20 -typedef union { - UINT8 Data; - struct { - // - // Rank Select Interleaving Enable. See Address Mapping section for f= ull description. - // 0 - Rank Select Interleaving disabled - // 1 - Rank Select Interleaving enabled - // - // Bits[0:0] - // - UINT8 RankSelectInterleavingEnable : 1; - // - // Bank Address Hashing Enable. See Address Mapping section for full = description. - // 0 - Bank Address Hashing disabled - // 1 - Bank Address Hashing enabled - // - // Bits[1:1] - // - UINT8 BankAddressHashingEnable : 1; - // - // CH1 CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. Thi= s is used - // on board designs where the CH1 CLK is not routed and left floating = or stubbed out. - // 0 =3D CH1 CLK is enabled - // 1 =3D CH1 CLK is disabled - // - // Bits[2:2] - // - UINT8 Ch1ClkDisable : 1; - // - // Reserved - // - // Bits[3] - // - UINT8 Reserved : 1; - // - // Specifies the address mapping to be used. - // 00b - 1KB, - // 01b - 2KB, - // 10b - 4KB, - // 11b - Reserved - // - // Bits[5:4] - // - UINT8 AddressMapping : 2; - // - // Reserved - // - // Bits[7:6] - // - UINT8 Reserved0 : 2; - } Bits; -} CHANNEL_OPTION; - - #ifndef ABSOLUTE #define ABSOLUTE 1 #define RELATIVE 2 @@ -157,9 +104,6 @@ typedef enum { #define BIT31 0x80000000 #endif =20 - -#pragma pack(1) - typedef enum { Pfct =3D 0, PfctT, @@ -188,6 +132,7 @@ typedef struct { /** Final training values stored on a per blueprint level. Needs to be per b= lueprint in case of a system with more than 1 level of memory per channel. + **/ typedef struct { UINT16 Values[MAX_BLUEPRINTS][MAX_NUM_ALGOS][MAX_RANKS][MAX_STROBES]; @@ -267,7 +212,6 @@ typedef struct { UINT8 OdtHigh; UINT16 LP4_MR0VALUE; UINT16 LP4_MR4VALUE; - CHANNEL_OPTION ChOption; } CHANNEL; =20 typedef struct { @@ -298,6 +242,7 @@ typedef struct { BOOT_VARIABLE_NV_DATA BootVariableNvData; } MRC_NV_DATA_FRAME; =20 +#pragma pack() #pragma pack(pop) #endif =20 --=20 2.10.1.windows.1