From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 47467820F7 for ; Wed, 15 Feb 2017 19:36:57 -0800 (PST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Feb 2017 19:36:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,167,1484035200"; d="dat'59?scan'59,208,59";a="821908376" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by FMSMGA003.fm.intel.com with ESMTP; 15 Feb 2017 19:36:56 -0800 Received: from fmsmsx115.amr.corp.intel.com (10.18.116.19) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 15 Feb 2017 19:36:56 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx115.amr.corp.intel.com (10.18.116.19) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 15 Feb 2017 19:36:55 -0800 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.20]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.132]) with mapi id 14.03.0248.002; Thu, 16 Feb 2017 11:36:53 +0800 From: "Guo, Mang" To: "edk2-devel@lists.01.org" CC: "Wei, David" , "Lu, ShifeiX A" Thread-Topic: [Patch][edk2-platforms/devel-MinnowBoard3] Fix MRC restore issue Thread-Index: AdKIBenNWYTz0Lg7SpGvb5XllFid+Q== Date: Thu, 16 Feb 2017 03:36:52 +0000 Message-ID: <22D2C85ED001C54AA20BFE3B0E4751D1524D8759@SHSMSX103.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: <22D2C85ED001C54AA20BFE3B0E4751D1524D8759@SHSMSX103.ccr.corp.intel.com> x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.21 Subject: [Patch][edk2-platforms/devel-MinnowBoard3] Fix MRC restore issue X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Feb 2017 03:36:57 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MCR parameter restored in the second time of boot, so the boot time is less= than the first time of boot. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang --- .../LeafHill/BoardInitPreMem/BoardInitMiscs.c | 17 +++++++++++++-- .../LeafHill/BoardInitPreMem/BoardInitPreMem.inf | 1 + .../MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c | 17 +++++++++++++-- .../BoardInitPreMem/BoardInitPreMem.inf | 1 + .../BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h | 2 ++ .../MemoryInit/BXT/Include/MrcEfiDefinitions.h | 3 ++- .../Mmrc/ProjectIndependent/Include/MmrcData.h | 24 ++++++++++++++++++= +++- 7 files changed, 59 insertions(+), 6 deletions(-) diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/Boa= rdInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/= BoardInitMiscs.c index 5af2fae..fe8ece0 100644 --- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitM= iscs.c +++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitM= iscs.c @@ -14,6 +14,7 @@ **/ =20 #include "BoardInitMiscs.h" +#include "MmrcData.h" =20 UPDATE_FSPM_UPD_FUNC mLhUpdateFspmUpdPtr =3D LhUpdateFspmUpd; DRAM_CREATE_POLICY_DEFAULTS_FUNC mLhDramCreatePolicyDefaultsPtr =3D LhDr= amCreatePolicyDefaults; @@ -29,6 +30,9 @@ LhUpdateFspmUpd ( EFI_PLATFORM_INFO_HOB *PlatformInfo =3D NULL; DRAM_POLICY_PPI *DramPolicy; EFI_STATUS Status; + MRC_NV_DATA_FRAME *MrcNvData; + MRC_PARAMS_SAVE_RESTORE *MrcParamsHob; + BOOT_VARIABLE_NV_DATA *BootVariableNvDataHob; =20 Status =3D (*PeiServices)->LocatePpi ( PeiServices, @@ -64,11 +68,20 @@ LhUpdateFspmUpd ( FspUpdRgn->FspmConfig.InterleavedMode =3D DramPolicy= ->InterleavedMode; FspUpdRgn->FspmConfig.MinRefRate2xEnable =3D DramPolicy= ->MinRefRate2xEnabled; FspUpdRgn->FspmConfig.DualRankSupportEnable =3D DramPolicy= ->DualRankSupportEnabled; - FspUpdRgn->FspmArchUpd.NvsBufferPtr =3D (VOID *)(U= INT32)DramPolicy->MrcTrainingDataPtr; - FspUpdRgn->FspmConfig.MrcBootDataPtr =3D (VOID *)(U= INT32)DramPolicy->MrcBootDataPtr; =20 CopyMem (&(FspUpdRgn->FspmConfig.Ch0_RankEnable), &DramPolicy->ChDrp, = sizeof (DramPolicy->ChDrp)); CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), &DramPolicy->ChSw= izzle, sizeof (DramPolicy->ChSwizzle)); + + if (((VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr !=3D 0) && + ((VOID *)(UINT32)DramPolicy->MrcBootDataPtr !=3D 0)) { + MrcNvData =3D (MRC_NV_DATA_FRAME *) AllocateZeroPool (sizeof (MRC_NV= _DATA_FRAME)); + MrcParamsHob =3D (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcT= rainingDataPtr); + BootVariableNvDataHob =3D (BOOT_VARIABLE_NV_DATA*)((UINT32)DramPolic= y->MrcBootDataPtr); + CopyMem(&(MrcNvData->MrcParamsSaveRestore), MrcParamsHob, sizeof (MR= C_PARAMS_SAVE_RESTORE)); + CopyMem(&(MrcNvData->BootVariableNvData), BootVariableNvDataHob, siz= eof (BOOT_VARIABLE_NV_DATA)); + FspUpdRgn->FspmArchUpd.NvsBufferPtr =3D (VOID *)(UINT32)MrcNvData; + } + } // // override RankEnable settings for Minnow diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/Boa= rdInitPreMem.inf b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreM= em/BoardInitPreMem.inf index c170839..c526bc2 100644 --- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitP= reMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitP= reMem.inf @@ -39,6 +39,7 @@ IntelFsp2Pkg/IntelFsp2Pkg.dec BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/IntelFsp2Wrappe= rPkg.dec IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + Silicon\BroxtonSoC\BroxtonSiPkg\NorthCluster\MemoryInit\MemoryInit.dec =20 [Pcd] gPlatformModuleTokenSpaceGuid.PcdBoardId diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem= /BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardIni= tPreMem/BoardInitMiscs.c index ece8a88..9e535ca 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardI= nitMiscs.c +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardI= nitMiscs.c @@ -14,6 +14,7 @@ **/ =20 #include "BoardInitMiscs.h" +#include "MmrcData.h" =20 UPDATE_FSPM_UPD_FUNC mMb3UpdateFspmUpdPtr =3D Mb3UpdateFspmUpd; DRAM_CREATE_POLICY_DEFAULTS_FUNC mMb3DramCreatePolicyDefaultsPtr =3D Mb3= DramCreatePolicyDefaults; @@ -29,6 +30,9 @@ Mb3UpdateFspmUpd ( EFI_PLATFORM_INFO_HOB *PlatformInfo =3D NULL; DRAM_POLICY_PPI *DramPolicy; EFI_STATUS Status; + MRC_NV_DATA_FRAME *MrcNvData; + MRC_PARAMS_SAVE_RESTORE *MrcParamsHob; + BOOT_VARIABLE_NV_DATA *BootVariableNvDataHob; =20 Status =3D (*PeiServices)->LocatePpi ( PeiServices, @@ -64,11 +68,20 @@ Mb3UpdateFspmUpd ( FspUpdRgn->FspmConfig.InterleavedMode =3D DramPolicy= ->InterleavedMode; FspUpdRgn->FspmConfig.MinRefRate2xEnable =3D DramPolicy= ->MinRefRate2xEnabled; FspUpdRgn->FspmConfig.DualRankSupportEnable =3D DramPolicy= ->DualRankSupportEnabled; - FspUpdRgn->FspmArchUpd.NvsBufferPtr =3D (VOID *)(U= INT32)DramPolicy->MrcTrainingDataPtr; - FspUpdRgn->FspmConfig.MrcBootDataPtr =3D (VOID *)(U= INT32)DramPolicy->MrcBootDataPtr; =20 CopyMem (&(FspUpdRgn->FspmConfig.Ch0_RankEnable), &DramPolicy->ChDrp, = sizeof(DramPolicy->ChDrp)); CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), &DramPolicy->ChSw= izzle, sizeof (DramPolicy->ChSwizzle)); + + if (((VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr !=3D 0) && + ((VOID *)(UINT32)DramPolicy->MrcBootDataPtr !=3D 0)) { + MrcNvData =3D (MRC_NV_DATA_FRAME *) AllocateZeroPool (sizeof (MRC_NV= _DATA_FRAME)); + MrcParamsHob =3D (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcT= rainingDataPtr); + BootVariableNvDataHob =3D (BOOT_VARIABLE_NV_DATA*)((UINT32)DramPolic= y->MrcBootDataPtr); + CopyMem(&(MrcNvData->MrcParamsSaveRestore), MrcParamsHob, sizeof (MR= C_PARAMS_SAVE_RESTORE)); + CopyMem(&(MrcNvData->BootVariableNvData), BootVariableNvDataHob, siz= eof (BOOT_VARIABLE_NV_DATA)); + FspUpdRgn->FspmArchUpd.NvsBufferPtr =3D (VOID *)(UINT32)MrcNvData; + } + } // // override RankEnable settings for Minnow diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem= /BoardInitPreMem.inf b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/Board= InitPreMem/BoardInitPreMem.inf index f64ab8f..9135fb8 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardI= nitPreMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardI= nitPreMem.inf @@ -39,6 +39,7 @@ IntelFsp2Pkg/IntelFsp2Pkg.dec BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/IntelFsp2Wrappe= rPkg.dec IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + Silicon\BroxtonSoC\BroxtonSiPkg\NorthCluster\MemoryInit\MemoryInit.dec =20 [Pcd] gPlatformModuleTokenSpaceGuid.PcdBoardId diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h b/= Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h index 7eb0e92..a2da161 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h @@ -56,10 +56,12 @@ typedef struct { UINT8 RmtMode; UINT8 RmtCheckRun; UINT16 RmtMarginCheckScaleHighThreshold; + UINT8 Reserved1; UINT32 MsgLevelMask; UINT8 SpdAddress[DRAM_POLICY_NUMBER_SPD_ADDRESSES]; UINT8 ChSwizzle[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY= _NUMBER_BITS]; DRP_DRAM_POLICY ChDrp[DRAM_POLICY_NUMBER_CHANNELS]; + UINT8 Reserved2; UINT8 DebugMsgLevel; UINT8 reserved[13]; } DRAM_POLICY_PPI; diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/In= clude/MrcEfiDefinitions.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Me= moryInit/BXT/Include/MrcEfiDefinitions.h index b19d6a0..5d36a6d 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/M= rcEfiDefinitions.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/M= rcEfiDefinitions.h @@ -64,10 +64,12 @@ typedef struct { UINT8 RmtMode; UINT8 RmtCheckRun; UINT16 RmtMarginCheckScaleHighThreshold; + UINT8 Reserved1; UINT32 MsgLevelMask; UINT8 SpdAddress[DRAM_POLICY_NUMBER_SPD_ADDRESSES]; UINT8 ChSwizzle[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY= _NUMBER_BITS]; DRP_DRAM_POLICY ChDrp[DRAM_POLICY_NUMBER_CHANNELS]; + UINT8 Reserved2; UINT8 DebugMsgLevel; UINT8 reserved[13]; } DRAM_POLICY_PPI; @@ -79,7 +81,6 @@ typedef struct { typedef enum { Bxt =3D 0x00, Bxt1, - BxtX, BxtP, BxtSeriesMax =3D 0xFF } BXT_SERIES; diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/P= rojectIndependent/Include/MmrcData.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Nort= hCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h index 0d64528..eb0f973 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectI= ndependent/Include/MmrcData.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectI= ndependent/Include/MmrcData.h @@ -52,6 +52,25 @@ typedef union { UINT8 Data8[4]; } MrcVersion; =20 +typedef union { + UINT8 Data; + struct { + + UINT8 RankSelectInterleavingEnable : 1; + + UINT8 BankAddressHashingEnable : 1; + + UINT8 Ch1ClkDisable : 1; + + UINT8 Reserved : 1; + + UINT8 AddressMapping : 2; + + UINT8 Reserved0 : 2; + } Bits; +} CHANNEL_OPTION; + + #ifndef ABSOLUTE #define ABSOLUTE 1 #define RELATIVE 2 @@ -104,6 +123,9 @@ typedef enum { #define BIT31 0x80000000 #endif =20 + +#pragma pack(1) + typedef enum { Pfct =3D 0, PfctT, @@ -212,6 +234,7 @@ typedef struct { UINT8 OdtHigh; UINT16 LP4_MR0VALUE; UINT16 LP4_MR4VALUE; + CHANNEL_OPTION ChOption; } CHANNEL; =20 typedef struct { @@ -242,7 +265,6 @@ typedef struct { BOOT_VARIABLE_NV_DATA BootVariableNvData; } MRC_NV_DATA_FRAME; =20 -#pragma pack() #pragma pack(pop) #endif =20 --=20 2.10.1.windows.1