From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7CDF62095A6D4 for ; Mon, 3 Jul 2017 01:29:41 -0700 (PDT) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Jul 2017 01:31:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,302,1496127600"; d="dat'59?scan'59,208,59";a="281502779" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga004.fm.intel.com with ESMTP; 03 Jul 2017 01:31:16 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 3 Jul 2017 01:31:15 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.116]) by SHSMSX104.ccr.corp.intel.com ([10.239.4.70]) with mapi id 14.03.0319.002; Mon, 3 Jul 2017 16:31:11 +0800 From: "Guo, Mang" To: "edk2-devel@lists.01.org" CC: "Wei, David" , "Lu, ShifeiX A" Thread-Topic: [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Add GPIO Protocol Thread-Index: AdLz1rl/FcenslTASs6wmnYBPlFDvw== Date: Mon, 3 Jul 2017 08:31:11 +0000 Message-ID: <22D2C85ED001C54AA20BFE3B0E4751D15251E878@SHSMSX103.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: <22D2C85ED001C54AA20BFE3B0E4751D15251E878@SHSMSX103.ccr.corp.intel.com> x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.22 Subject: [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Add GPIO Protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 03 Jul 2017 08:29:41 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable This protocol is used to get GPIO info and configure GPIO. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang --- .../Common/Include/Protocol/GpioProtocol.h | 192 ++++++++++++ .../PlatformSettings/PlatformGpio/GpioPadTable.h | 296 +++++++++++++++++= + .../PlatformSettings/PlatformGpio/PlatformGpio.c | 340 +++++++++++++++++= ++++ .../PlatformSettings/PlatformGpio/PlatformGpio.h | 152 +++++++++ .../PlatformSettings/PlatformGpio/PlatformGpio.inf | 52 ++++ .../BroxtonPlatformPkg/PlatformDsc/Components.dsc | 1 + Platform/BroxtonPlatformPkg/PlatformPkg.dec | 4 +- Platform/BroxtonPlatformPkg/PlatformPkg.fdf | 1 + 8 files changed, 1037 insertions(+), 1 deletion(-) create mode 100644 Platform/BroxtonPlatformPkg/Common/Include/Protocol/Gpi= oProtocol.h create mode 100644 Platform/BroxtonPlatformPkg/Common/PlatformSettings/Pla= tformGpio/GpioPadTable.h create mode 100644 Platform/BroxtonPlatformPkg/Common/PlatformSettings/Pla= tformGpio/PlatformGpio.c create mode 100644 Platform/BroxtonPlatformPkg/Common/PlatformSettings/Pla= tformGpio/PlatformGpio.h create mode 100644 Platform/BroxtonPlatformPkg/Common/PlatformSettings/Pla= tformGpio/PlatformGpio.inf diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Protocol/GpioProtoc= ol.h b/Platform/BroxtonPlatformPkg/Common/Include/Protocol/GpioProtocol.h new file mode 100644 index 0000000..bb60c27 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Include/Protocol/GpioProtocol.h @@ -0,0 +1,192 @@ +/** @file + This protocol is used to configure GPIO. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + +**/ + +/// +/// GPIO Protocol GUID. +/// +#define EDKII_GPIO_PROTOCOL_GUID \ + { \ + 0x239a4037, 0x5231, 0x44d6, {0xa2, 0xab, 0x51, 0x74, 0xcd, 0x81, 0xff,= 0x85 } \ + } + +typedef struct _EDKII_GPIO_PROTOCOL EDKII_GPIO_PROTOCOL; + + + +typedef enum { + GpInOut =3D 0, + GpIn =3D 1, ///< GPI, input only in PAD_VALUE + GpOut =3D 2 ///< GPO, output only in PAD_VALUE +} GPIO_DIRECTION; + +typedef enum { + Low =3D 0, + High =3D 1 +} GPIO_LEVEL; + +typedef enum { + Fn0 =3D 0, ///< Function 0, GPIO mode + Fn1 =3D 1, ///< Function 1 + Fn2 =3D 2, ///< Function 2 + Fn3 =3D 3, ///< Function 3 + Fn4 =3D 4, ///< Function 4 + Fn5 =3D 5 ///< Function 5 +} PAD_MODE; + +/** + Get Max GPIO count. + + @param[in] This A pointer to the EDKII_GPIO_PROTOCOL = instance. + @param[out] MaxCount Max GPIO count + + @retval EFI_SUCCESS The operation succeeded. +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_GET_MAX_COUNT)( + IN EDKII_GPIO_PROTOCOL *This, + OUT UINT32 *MaxCount + ); + + +/** + Get Pad Mode. + + @param[in] This A pointer to the EDKII_GPIO_PROTOCOL = instance. + @param[in] PinNum Target GPIO. + @param[out] PadMode 0: Function 0 (GPIO mode), + 1: Function 1, 2: Function 2, 3: Func= tion 3, 4: Function 4, 5: Function 5 + + @retval EFI_SUCCESS The operation succeeded. + @retval EFI_UNSUPPORTED This function is not supported. +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_GET_MODE) ( + IN EDKII_GPIO_PROTOCOL *This, + IN UINT32 PinNum, + OUT PAD_MODE *PadMode + ); + + +/** + Set Pad Mode to Fn0/Fn1/Fn2/Fn3/Fn4/Fn5. + + @param[in] This A pointer to the EDKII_GPIO_PROTOCOL = instance. + @param[in] GPIO_NAME Target GPIO. + @param[out] PMode GPIO mode to set. + + @retval EFI_SUCCESS The operation succeeded. + @retval EFI_UNSUPPORTED This function is not supported. +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_SET_MODE) ( + IN EDKII_GPIO_PROTOCOL *This, + IN UINT32 PinNum, + IN PAD_MODE PadMode + ); + + +/** + Check GPIO direction. + + @param[in] This A pointer to the EDKII_GPIO_PROTOCOL = instance. + @param[in] PinNum Target GPIO. + @param[out] GpioDirection + + @retval EFI_SUCCESS The operation succeeded. + @retval EFI_UNSUPPORTED This function is not supported. +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_GET_GPIO_DIRECTION)( + IN EDKII_GPIO_PROTOCOL *This, + IN UINT32 PinNum, + OUT GPIO_DIRECTION *GpioDirection + ); + + +/** + Set GPIO direction to GPI/GPO/GPIO. + + @param[in] This A pointer to the EDKII_GPIO_PROTOCOL = instance. + @param[in] PinNum Target GPIO. + @Param[in] GpioDirection + + @retval EFI_SUCCESS The operation succeeded. + @retval EFI_UNSUPPORTED This function is not supported. +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_SET_GPIO_DIRECTION)( + IN EDKII_GPIO_PROTOCOL *This, + IN UINT32 PinNum, + IN GPIO_DIRECTION GpioDirection + ); + + +/** + Check GPIO direction, if it is GPI, get input value. + + @param[in] This A pointer to the EDKII_GPIO_PROTOCOL = instance. + @param[in] PinNum Target GPIO. + @param[out] InputVal GPIO Input value + 0: InputLow, 1: InputHigh + + @retval EFI_SUCCESS The operation succeeded. + @retval EFI_UNSUPPORTED This function is not supported. +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_GPIO_GET_GPI_LEVEL)( + IN EDKII_GPIO_PROTOCOL *This, + IN UINT32 PinNum, + OUT GPIO_LEVEL *GpiLevel + ); + + +/** + Check GPIO direction, if it is GPO, Set output value. + + @param[in] This A pointer to the EDKII_GPIO_PROTOCOL = instance. + @param[in] PinNum Target GPIO. + @param[in] GpoState GPO output value + 0: Low, 1: High + + @retval EFI_SUCCESS The operation succeeded. + @retval EFI_UNSUPPORTED This function is not supported. +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_GPIO_SET_GPO_LEVEL)( + IN EDKII_GPIO_PROTOCOL *This, + IN UINT32 PinNum, + IN GPIO_LEVEL GpoLevel + ); + + +struct _EDKII_GPIO_PROTOCOL { + EDKII_GET_MAX_COUNT GetMaxCount; + EDKII_GET_MODE GetMode; + EDKII_SET_MODE SetMode; + EDKII_GET_GPIO_DIRECTION GetGpioDirection; ///< Get GPIO dir= ection + EDKII_SET_GPIO_DIRECTION SetGpioDirection; ///< Set GPIO dir= ection + EDKII_GPIO_GET_GPI_LEVEL GetGpiLevel; ///< Get GPI leve= l + EDKII_GPIO_SET_GPO_LEVEL SetGpoLevel; ///< Set GPO leve= l +}; + +extern EFI_GUID gEdkiiGpioProtocolGuid; + diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformGp= io/GpioPadTable.h b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/Pla= tformGpio/GpioPadTable.h new file mode 100644 index 0000000..11e3722 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformGpio/Gpio= PadTable.h @@ -0,0 +1,296 @@ +/** @file + GPIO pad and offset definition. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + +**/ + +#ifndef _BXTP_GPIOTABLE_H_ +#define _BXTP_GPIOTABLE_H_ + + +typedef struct { + CHAR16* pad_name; + UINT32 CommAndOffset; + +} GPIO_PAD_TABLE; + +// +// GPIO pad and offset definition as GPIO HAS +// North community GPIO pad definition +// +STATIC CONST GPIO_PAD_TABLE mGpioPadTable[] =3D { + +// +// GPIO pad and offset definition as GPIO HAS +// North community GPIO pad definition +// +{L"GPIO_0", N_GPIO_0}, //GPIO_0 +{L"GPIO_1", N_GPIO_1}, //GPIO_1 +{L"GPIO_2", N_GPIO_2}, //GPIO_2 +{L"GPIO_3", N_GPIO_3}, //GPIO_3 +{L"GPIO_4", N_GPIO_4}, //GPIO_4 +{L"GPIO_5", N_GPIO_5}, //GPIO_5 +{L"GPIO_6", N_GPIO_6}, //GPIO_6 +{L"GPIO_7", N_GPIO_7}, //GPIO_7 +{L"GPIO_8", N_GPIO_8}, //GPIO_8 +{L"GPIO_9", N_GPIO_9}, //GPIO_9 +{L"GPIO_10", N_GPIO_10}, //GPIO_10 +{L"GPIO_11", N_GPIO_11}, //GPIO_11 +{L"GPIO_12", N_GPIO_12}, //GPIO_12 +{L"GPIO_13", N_GPIO_13}, //GPIO_13 +{L"GPIO_14", N_GPIO_14}, //GPIO_14 +{L"GPIO_15", N_GPIO_15}, //GPIO_15 +{L"GPIO_16", N_GPIO_16}, //GPIO_16 +{L"GPIO_17", N_GPIO_17}, //GPIO_17 +{L"GPIO_18", N_GPIO_18}, //GPIO_18 +{L"GPIO_19", N_GPIO_19}, //GPIO_19 +{L"GPIO_20", N_GPIO_20}, //GPIO_20 +{L"GPIO_21", N_GPIO_21}, //GPIO_21 +{L"GPIO_22", N_GPIO_22}, //GPIO_22 +{L"GPIO_23", N_GPIO_23}, //GPIO_23 +{L"GPIO_24", N_GPIO_24}, //GPIO_24 +{L"GPIO_25", N_GPIO_25}, //GPIO_25 +{L"GPIO_26", N_GPIO_26}, //GPIO_26 +{L"GPIO_27", N_GPIO_27}, //GPIO_27 +{L"GPIO_28", N_GPIO_28}, //GPIO_28 +{L"GPIO_29", N_GPIO_29}, //GPIO_29 +{L"GPIO_30", N_GPIO_30}, //GPIO_30 +{L"GPIO_31", N_GPIO_31}, //GPIO_31 +{L"GPIO_32", N_GPIO_32}, //GPIO_32 +{L"GPIO_33", N_GPIO_33}, //GPIO_33 +{L"GPIO_34", N_GPIO_34}, //PWM0 +{L"GPIO_35", N_GPIO_35}, //PWM1 +{L"GPIO_36", N_GPIO_36}, //PWM2 +{L"GPIO_37", N_GPIO_37}, //PWM3 +{L"GPIO_38", N_GPIO_38}, //LPSS_UART0_RXD +{L"GPIO_39", N_GPIO_39}, //LPSS_UART0_TXD +{L"GPIO_40", N_GPIO_40}, //LPSS_UART0_RTS_B +{L"GPIO_41", N_GPIO_41}, //LPSS_UART0_CTS_B +{L"GPIO_42", N_GPIO_42}, //LPSS_UART1_RXD +{L"GPIO_43", N_GPIO_43}, //LPSS_UART1_TXD +{L"GPIO_44", N_GPIO_44}, //LPSS_UART1_RTS_B +{L"GPIO_45", N_GPIO_45}, //LPSS_UART1_CTS_B +{L"GPIO_46", N_GPIO_46}, //LPSS_UART2_RXD +{L"GPIO_47", N_GPIO_47}, //LPSS_UART2_TXD +{L"GPIO_48", N_GPIO_48}, //LPSS_UART2_RTS_B +{L"GPIO_49", N_GPIO_49}, //LPSS_UART2_CTS_B +{L"GPIO_62", N_GPIO_62}, //GP_CAMERASB00 +{L"GPIO_63", N_GPIO_63}, //GP_CAMERASB01 +{L"GPIO_64", N_GPIO_64}, //GP_CAMERASB02 +{L"GPIO_65", N_GPIO_65}, //GP_CAMERASB03 +{L"GPIO_66", N_GPIO_66}, //GP_CAMERASB04 +{L"GPIO_67", N_GPIO_67}, //GP_CAMERASB05 +{L"GPIO_68", N_GPIO_68}, //GP_CAMERASB06 +{L"GPIO_69", N_GPIO_69}, //GP_CAMERASB07 +{L"GPIO_70", N_GPIO_70}, //GP_CAMERASB08 +{L"GPIO_71", N_GPIO_71}, //GP_CAMERASB09 +{L"GPIO_72", N_GPIO_72}, //GP_CAMERASB10 +{L"GPIO_73", N_GPIO_73}, //GP_CAMERASB11 +{L"TCK", N_TCK}, //TCK +{L"TRST_B", N_TRST_B}, //TRST_B +{L"TMS", N_TMS}, //TMS +{L"TDI", N_TDI}, //TDI +{L"CX_PMODE", N_CX_PMODE}, //CX_PMODE +{L"CX_PREQ_B", N_CX_PREQ_B}, //CX_PREQ_B +{L"JTAGX", N_JTAGX}, //JTAGX +{L"CXPRDY_B", N_CX_PRDY_B}, //CXPRDY_B +{L"TDO", N_TDO}, //TDO +{L"GPIO_216", N_CNV_BRI_DT}, //CNV_BRI_DT +{L"GPIO_217", N_CNV_BRI_RSP}, //CNV_BRI_RSP +{L"GPIO_218", N_CNV_RGI_DT}, //CNV_RGI_DT +{L"GPIO_219", N_CNV_RGI_RSP}, //CNV_RGI_RSP +{L"SVID0_ALERT_B", N_SVID0_ALERT_B}, //SVID0_ALERT_B +{L"SVID0_DATA", N_SVID0_DATA}, //SVID0_DATA +{L"SVID0_CLK", N_SVID0_CLK}, //SVID0_CLK + +// +// Northwest community GPIO pad definition +// +{L"GPIO_187", NW_GPIO_187}, //HV_DDI0_DDC_SDA +{L"GPIO_188", NW_GPIO_188}, //HV_DDI0_DDC_SCL +{L"GPIO_189", NW_GPIO_189}, //HV_DDI1_DDC_SDA +{L"GPIO_190", NW_GPIO_190}, //HV_DDI1_DDC_SCL +{L"GPIO_191", NW_GPIO_191}, //DBI_SDA +{L"GPIO_192", NW_GPIO_192}, //DBI_SCL +{L"GPIO_193", NW_GPIO_193}, //PANEL0_VDDEN +{L"GPIO_194", NW_GPIO_194}, //PANEL0_BKLTEN +{L"GPIO_195", NW_GPIO_195}, //PANEL0_BKLTCTL +{L"GPIO_196", NW_GPIO_196}, //PANEL1_VDDEN +{L"GPIO_197", NW_GPIO_197}, //PANEL1_BKLTEN +{L"GPIO_198", NW_GPIO_198}, //PANEL1_BKLTCTL +{L"GPIO_199", NW_GPIO_199}, //DBI_CSX +{L"GPIO_200", NW_GPIO_200}, //DBI_RESX +{L"GPIO_201", NW_GPIO_201}, //GP_INTD_DSI_TE1 +{L"GPIO_202", NW_GPIO_202}, //GP_INTD_DSI_TE2 +{L"GPIO_203", NW_GPIO_203}, //USB_OC0_B +{L"GPIO_204", NW_GPIO_204}, //USB_OC1_B +{L"PMC_SPI_FS0", NW_PMC_SPI_FS0}, //PMC_SPI_FS0 +{L"PMC_SPI_FS1", NW_PMC_SPI_FS1}, //PMC_SPI_FS1 +{L"PMC_SPI_FS2", NW_PMC_SPI_FS2}, //PMC_SPI_FS2 +{L"PMC_SPI_RXD", NW_PMC_SPI_RXD}, //PMC_SPI_RXD +{L"PMC_SPI_TXD", NW_PMC_SPI_TXD}, //PMC_SPI_TXD +{L"PMC_SPI_CLK", NW_PMC_SPI_CLK}, //PMC_SPI_CLK +{L"PMIC_PWRGOOD", NW_PMIC_PWRGOOD}, //PMIC_PWRGOOD +{L"PMIC_RESET_B", NW_PMIC_RESET_B}, //PMIC_RESET_B +{L"GPIO_213", NW_GPIO_213}, //PMIC_SDWN_B +{L"GPIO_214", NW_GPIO_214}, //PMIC_BCUDISW2 +{L"GPIO_215", NW_GPIO_215}, //PMIC_BCUDISCRIT +{L"PMIC_THERMTRIP_B", NW_PMIC_THERMTRIP_B}, //PMIC_THERMTRIP_B +{L"PMIC_STDBY", NW_PMIC_STDBY}, //PMIC_STDBY +{L"PROCHOT_B", NW_PROCHOT_B}, //PROCHOT_B +{L"PMIC_I2C_SCL", NW_PMIC_I2C_SCL}, //PMIC_I2C_SCL +{L"PMIC_I2C_SDA", NW_PMIC_I2C_SDA}, //PMIC_I2C_SDA +{L"GPIO_74", NW_GPIO_74}, //AVS_I2S1_MCLK +{L"GPIO_75", NW_GPIO_75}, //AVS_I2S1_BCLK +{L"GPIO_76", NW_GPIO_76}, //AVS_I2S1_WS_SYNC +{L"GPIO_77", NW_GPIO_77}, //AVS_I2S1_SDI +{L"GPIO_78", NW_GPIO_78}, //AVS_I2S1_SDO +{L"GPIO_79", NW_GPIO_79}, //AVS_M_CLK_A1 +{L"GPIO_80", NW_GPIO_80}, //AVS_M_CLK_B1 +{L"GPIO_81", NW_GPIO_81}, //AVS_M_DATA_1 +{L"GPIO_82", NW_GPIO_82}, //AVS_M_CLK_AB2 +{L"GPIO_83", NW_GPIO_83}, //AVS_M_DATA_2 +{L"GPIO_84", NW_GPIO_84}, //AVS_I2S2_MCLK +{L"GPIO_85", NW_GPIO_85}, //AVS_I2S2_BCLK +{L"GPIO_86", NW_GPIO_86}, //AVS_I2S2_WS_SYNC +{L"GPIO_87", NW_GPIO_87}, //AVS_I2S2_SDI +{L"GPIO_88", NW_GPIO_88}, //AVS_I2S2_SDO +{L"GPIO_89", NW_GPIO_89}, //AVS_I2S3_BCLK +{L"GPIO_90", NW_GPIO_90}, //AVS_I2S3_WS_SYNC +{L"GPIO_91", NW_GPIO_91}, //AVS_I2S3_SDI +{L"GPIO_92", NW_GPIO_92}, //AVS_I2S3_SDO +{L"GPIO_97", NW_GPIO_97}, //FST_SPI_CS0_B +{L"GPIO_98", NW_GPIO_98}, //FST_SPI_CS1_B +{L"GPIO_99", NW_GPIO_99}, //FST_SPI_MOSI_IO0 +{L"GPIO_100", NW_GPIO_100}, //FST_SPI_MISO_IO1 +{L"GPIO_101", NW_GPIO_101}, //FST_SPI_IO2 +{L"GPIO_102", NW_GPIO_102}, //FST_SPI_IO3 +{L"GPIO_103", NW_GPIO_103}, //FST_SPI_CLK +{L"FST_SPI_CLK_FB", NW_FST_SPI_CLK_FB}, //FST_SPI_CLK_FB +{L"GPIO_104", NW_GPIO_104}, //GP_SSP_0_CLK +{L"GPIO_105", NW_GPIO_105}, //GP_SSP_0_FS0 +{L"GPIO_106", NW_GPIO_106}, //GP_SSP_0_FS1 +{L"GPIO_109", NW_GPIO_109}, //GP_SSP_0_RXD +{L"GPIO_110", NW_GPIO_110}, //GP_SSP_0_TXD +{L"GPIO_111", NW_GPIO_111}, //GP_SSP_1_CLK +{L"GPIO_112", NW_GPIO_112}, //GP_SSP_1_FS0 +{L"GPIO_113", NW_GPIO_113}, //GP_SSP_1_FS1 +{L"GPIO_116", NW_GPIO_116}, //GP_SSP_1_RXD +{L"GPIO_117", NW_GPIO_117}, //GP_SSP_1_TXD +{L"GPIO_118", NW_GPIO_118}, //GP_SSP_2_CLK +{L"GPIO_119", NW_GPIO_119}, //GP_SSP_2_FS0 +{L"GPIO_120", NW_GPIO_120}, //GP_SSP_2_FS1 +{L"GPIO_121", NW_GPIO_121}, //GP_SSP_2_FS2 +{L"GPIO_122", NW_GPIO_122}, //GP_SSP_2_RXD +{L"GPIO_123", NW_GPIO_123}, //GP_SSP_2_TXD + +// +// West community GPIO pad definition +// +{L"GPIO_124", W_GPIO_124}, //LPSS_I2S0_SDA +{L"GPIO_125", W_GPIO_125}, //LPSS_I2S0_SCL +{L"GPIO_126", W_GPIO_126}, //LPSS_I2S1_SDA +{L"GPIO_127", W_GPIO_127}, //LPSS_I2S1_SCL +{L"GPIO_128", W_GPIO_128}, //LPSS_I2S2_SDA +{L"GPIO_129", W_GPIO_129}, //LPSS_I2S2_SCL +{L"GPIO_130", W_GPIO_130}, //LPSS_I2S3_SDA +{L"GPIO_131", W_GPIO_131}, //LPSS_I2S3_SCL +{L"GPIO_132", W_GPIO_132}, //LPSS_I2S4_SDA +{L"GPIO_133", W_GPIO_133}, //LPSS_I2S4_SCL +{L"GPIO_134", W_GPIO_134}, //LPSS_I2S5_SDA +{L"GPIO_135", W_GPIO_135}, //LPSS_I2S5_SCL +{L"GPIO_136", W_GPIO_136}, //LPSS_I2S6_SDA +{L"GPIO_137", W_GPIO_137}, //LPSS_I2S6_SCL +{L"GPIO_138", W_GPIO_138}, //LPSS_I2S7_SDA +{L"GPIO_139", W_GPIO_139}, //LPSS_I2S7_SCL +{L"GPIO_146", W_GPIO_146}, //ISH_GPIO_0 +{L"GPIO_147", W_GPIO_147}, //ISH_GPIO_1 +{L"GPIO_148", W_GPIO_148}, //ISH_GPIO_2 +{L"GPIO_149", W_GPIO_149}, //ISH_GPIO_3 +{L"GPIO_150", W_GPIO_150}, //ISH_GPIO_4 +{L"GPIO_151", W_GPIO_151}, //ISH_GPIO_5 +{L"GPIO_152", W_GPIO_152}, //ISH_GPIO_6 +{L"GPIO_153", W_GPIO_153}, //ISH_GPIO_7 +{L"GPIO_154", W_GPIO_154}, //ISH_GPIO_8 +{L"GPIO_155", W_GPIO_155}, //ISH_GPIO_9 +{L"GPIO_209", W_GPIO_209}, //PCIE_CLKREQ0_B +{L"GPIO_210", W_GPIO_210}, //PCIE_CLKREQ1_B +{L"GPIO_211", W_GPIO_211}, //PCIE_CLKREQ2_B +{L"GPIO_212", W_GPIO_212}, //PCIE_CLKREQ3_B +{L"OSC_C{LK_OUT0", W_OSC_CLK_OUT_0}, //OSC_CLK_OUT0 +{L"OSC_C{LK_OUT1", W_OSC_CLK_OUT_1}, //OSC_CLK_OUT1 +{L"OSC_C{LK_OUT2", W_OSC_CLK_OUT_2}, //OSC_CLK_OUT2 +{L"OSC_C{LK_OUT3", W_OSC_CLK_OUT_3}, //OSC_CLK_OUT3 +{L"OSC_C{LK_OUT4", W_OSC_CLK_OUT_4}, //OSC_CLK_OUT4 +{L"PMU_AC_PRESENT", W_PMU_AC_PRESENT}, //PMU_AC_PRESENT +{L"PMU_BAT{LOW_B", W_PMU_BATLOW_B}, //PMU_BATLOW_B +{L"PMU_PLTRST_B", W_PMU_PLTRST_B}, //PMU_PLTRST_B +{L"PMU_PWRBTN_B", W_PMU_PWRBTN_B}, //PMU_PWRBTN_B +{L"PMU_RESETBUTTON_B", W_PMU_RESETBUTTON_B}, //PMU_RESETBUTTON_B +{L"PMU_SLP_S0_B", W_PMU_SLP_S0_B}, //PMU_SLP_S0_B +{L"PMU_SLP_S3_B", W_PMU_SLP_S3_B}, //PMU_SLP_S3_B +{L"PMU_SLP_S4_B", W_PMU_SLP_S4_B}, //PMU_SLP_S4_B +{L"PMU_SUSCLK", W_PMU_SUSCLK}, //PMU_SUSCLK +{L"PMU_WAKE_B", W_PMU_WAKE_B}, //PMU_WAKE_B +{L"SUS_STAT_B", W_SUS_STAT_B}, //SUS_STAT_B +{L"SUSPWRDNACK", W_SUSPWRDNACK}, //SUSPWRDNACK + +// +// Southwest community GPIO pad definition +// +{L"GPIO_205", SW_GPIO_205}, //PCIE_WAKE0_B +{L"GPIO_206", SW_GPIO_206}, //PCIE_WAKE1_B +{L"GPIO_207", SW_GPIO_207}, //PCIE_WAKE2_B +{L"GPIO_208", SW_GPIO_208}, //PCIE_WAKE3_B +{L"GPIO_156", SW_GPIO_156}, //EMMC0_CLK +{L"GPIO_157", SW_GPIO_157}, //EMMC0_D0 +{L"GPIO_158", SW_GPIO_158}, //EMMC0_D1 +{L"GPIO_159", SW_GPIO_159}, //EMMC0_D2 +{L"GPIO_160", SW_GPIO_160}, //EMMC0_D3 +{L"GPIO_161", SW_GPIO_161}, //EMMC0_D4 +{L"GPIO_162", SW_GPIO_162}, //EMMC0_D5 +{L"GPIO_163", SW_GPIO_163}, //EMMC0_D6 +{L"GPIO_164", SW_GPIO_164}, //EMMC0_D7 +{L"GPIO_165", SW_GPIO_165}, //EMMC0_CMD0 +{L"GPIO_166", SW_GPIO_166}, //SDIO_CLK +{L"GPIO_167", SW_GPIO_167}, //SDIO_D0 +{L"GPIO_168", SW_GPIO_168}, //SDIO_D1 +{L"GPIO_169", SW_GPIO_169}, //SDIO_D2 +{L"GPIO_170", SW_GPIO_170}, //SDIO_D3 +{L"GPIO_171", SW_GPIO_171}, //SDIO_CMD +{L"GPIO_172", SW_GPIO_172}, //SDCARD_CLK +{L"GPIO_179", SW_GPIO_179}, //SDCARD_CMD +{L"GPIO_173", SW_GPIO_173}, //SDCARD_CLK_FB +{L"GPIO_174", SW_GPIO_174}, //SDCARD_D0 +{L"GPIO_175", SW_GPIO_175}, //SDCARD_D1 +{L"GPIO_176", SW_GPIO_176}, //SDCARD_D2 +{L"GPIO_177", SW_GPIO_177}, //SDCARD_D3 +{L"GPIO_178", SW_GPIO_178}, //SDCARD_CD_B +{L"GPIO_186", SW_GPIO_186}, //SDCARD_LVL_WP +{L"GPIO_182", SW_GPIO_182}, //EMMC0_STROBE +{L"GPIO_183", SW_GPIO_183}, //SDIO_PWR_DOWN_B +{L"SMB_ALERTB", SW_SMB_ALERTB}, //SMB_ALERTB +{L"SMB_CLK", SW_SMB_CLK}, //SMB_CLK +{L"SMB_DATA", SW_SMB_DATA}, //SMB_DATA +{L"LPC_ILB_SERIRQ", SW_LPC_ILB_SERIRQ}, //LPC_ILB_SERIRQ +{L"LPC_CLKOUT0", SW_LPC_CLKOUT0}, //LPC_CLKOUT0 +{L"LPC_CLKOUT1", SW_LPC_CLKOUT1}, //LPC_CLKOUT1 +{L"LPC_AD0", SW_LPC_AD0}, //LPC_AD0 +{L"LPC_AD1", SW_LPC_AD1}, //LPC_AD1 +{L"LPC_AD2", SW_LPC_AD2}, //LPC_AD2 +{L"LPC_AD3", SW_LPC_AD3}, //LPC_AD3 +{L"LPC_CLKRUN", SW_LPC_CLKRUN}, //LPC_CLKRUN +{L"LPC_FRAMEB", SW_LPC_FRAMEB} //LPC_FRAMEB +}; + +#endif + diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformGp= io/PlatformGpio.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/Pla= tformGpio/PlatformGpio.c new file mode 100644 index 0000000..02fbf15 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformGpio/Plat= formGpio.c @@ -0,0 +1,340 @@ +/** @file + Implementation for GPIO protocol. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include "PlatformGpio.h" +#include "GpioPadTable.h" + +EFI_HANDLE mHandle =3D NULL; + +EDKII_GPIO_PROTOCOL mGpioProtocol =3D { + GetMaxCount, + GetMode, + SetMode, + GetGpioDirection, + SetGpioDirection, + GetGpiLevel, + SetGpoLevel + }; + + +/** + Get Max GPIO count. + + @param[in] This A pointer to the EDKII_GPIO_PROTOCOL = instance. + @param[out] MaxCount Max GPIO count + + @retval EFI_SUCCESS The operation succeeded. +**/ +EFI_STATUS +EFIAPI +GetMaxCount ( + IN EDKII_GPIO_PROTOCOL *This, + OUT UINT32 *MaxCount + ) +{ + UINT8 Index; + *MaxCount =3D sizeof (mGpioPadTable)/sizeof (mGpioPadTable[0]); + DEBUG ((DEBUG_INFO, "Max PinNum is %d\n", *MaxCount)); + + for( Index =3D0; Index < *MaxCount; Index++ ) { + DEBUG ((DEBUG_INFO, "PinNum: %d, PadName: %s\n", Index, mGpioPadTable= [Index].pad_name)); + } + + return EFI_SUCCESS; +} + + +/** + Get Pad Mode. + + @param[in] This A pointer to the EDKII_GPIO_PROTOCOL = instance. + @param[in] PinNum Target GPIO. + @param[out] PadMode 0: Function 0 (GPIO mode), + 1: Function 1, 2: Function 2, 3: Func= tion 3, 4: Function 4, 5: Function 5 + + @retval EFI_SUCCESS The operation succeeded. + @retval EFI_UNSUPPORTED This function is not supported. +**/ +EFI_STATUS +EFIAPI +GetMode ( + IN EDKII_GPIO_PROTOCOL *This, + IN UINT32 PinNum, + OUT PAD_MODE *PadMode + ) +{ + BXT_CONF_PAD0 PadConfig0; + + if (PinNum>=3Dsizeof (mGpioPadTable)/sizeof (mGpioPadTable[0])) { + DEBUG ((DEBUG_INFO, "PinNum out of range.\n")); + return EFI_UNSUPPORTED; + } + + PadConfig0.padCnf0 =3D GpioPadRead (mGpioPadTable[PinNum].CommAndOffset = + BXT_GPIO_PAD_CONF0_OFFSET); + *PadMode =3D PadConfig0.r.PMode; + DEBUG ((DEBUG_INFO, "Pad Mode is %x\n", *PadMode)); + return EFI_SUCCESS; +} + + +/** + Set Pad Mode to Fn0/Fn1/Fn2/Fn3/Fn4/Fn5. + + @param[in] This A pointer to the EDKII_GPIO_PROTOCOL = instance. + @param[in] GPIO_NAME Target GPIO.=20 + @param[out] PMode GPIO mode to set. + + @retval EFI_SUCCESS The operation succeeded. + @retval EFI_UNSUPPORTED This function is not supported. +**/ +EFI_STATUS +EFIAPI +SetMode ( + IN EDKII_GPIO_PROTOCOL *This, + IN UINT32 PinNum, + IN PAD_MODE PadMode + ) +{ + BXT_CONF_PAD0 PadConfig0; + =20 + if (PinNum>=3Dsizeof (mGpioPadTable)/sizeof (mGpioPadTable[0])) { + DEBUG ((DEBUG_INFO, "PinNum out of range.\n")); + return EFI_UNSUPPORTED; + } + + PadConfig0.padCnf0 =3D GpioPadRead (mGpioPadTable[PinNum].CommAndOffset = + BXT_GPIO_PAD_CONF0_OFFSET); + PadConfig0.r.PMode =3D PadMode; + GpioPadWrite (mGpioPadTable[PinNum].CommAndOffset + BXT_GPIO_PAD_CONF0_O= FFSET, PadConfig0.padCnf0); + + DEBUG ((DEBUG_INFO, "Set GPIO Mode to %x\n", PadMode)); + return EFI_SUCCESS; +} + + +/** + Check GPIO direction. + + @param[in] This A pointer to the EDKII_GPIO_PROTOCOL = instance. + @param[in] PinNum Target GPIO. + @param[out] GpioDirection + + @retval EFI_SUCCESS The operation succeeded. + @retval EFI_UNSUPPORTED This function is not supported. +**/ +EFI_STATUS +EFIAPI +GetGpioDirection ( + IN EDKII_GPIO_PROTOCOL *This, + IN UINT32 PinNum, + OUT GPIO_DIRECTION *GpioDirection + ) +{ + BXT_CONF_PAD0 PadConfig0; + + if (PinNum>=3Dsizeof (mGpioPadTable)/sizeof (mGpioPadTable[0])) { + DEBUG ((DEBUG_INFO, "PinNum out of range.\n")); + return EFI_UNSUPPORTED; + } + + DEBUG ((DEBUG_INFO, "CommAndOffset =3D 0x%08x, PadName =3D %s\n",mGpioPa= dTable[PinNum].CommAndOffset,mGpioPadTable[PinNum].pad_name)); + // + // Check pad mode + // + PadConfig0.padCnf0 =3D GpioPadRead (mGpioPadTable[PinNum].CommAndOffset = + BXT_GPIO_PAD_CONF0_OFFSET); + + if (PadConfig0.r.PMode !=3D M0) { + DEBUG ((DEBUG_INFO, "Not GPIO mode\n")); + return EFI_UNSUPPORTED; + } else { + DEBUG ((DEBUG_INFO, "GPIO mode.")); + *GpioDirection =3D PadConfig0.r.GPIORxTxDis; + if (*GpioDirection =3D=3D GpIn) { + DEBUG ((DEBUG_INFO, "Pad direction is GPI\n")); + } else if (*GpioDirection =3D=3D GpOut) { + DEBUG ((DEBUG_INFO, "Pad direction is GPO\n")); + } else if (*GpioDirection =3D=3D GpInOut) { + DEBUG ((DEBUG_INFO, "Pad direction is GPIO\n")); + } else { + return EFI_UNSUPPORTED; + } + } + return EFI_SUCCESS; +} + + +/** + Set GPIO direction to GPI/GPO/GPIO. + + @param[in] This A pointer to the EDKII_GPIO_PROTOCOL = instance. + @param[in] PinNum Target GPIO. + @Param[in] GpioDirection + + @retval EFI_SUCCESS The operation succeeded. + @retval EFI_UNSUPPORTED This function is not supported. +**/ +EFI_STATUS +EFIAPI +SetGpioDirection ( + IN EDKII_GPIO_PROTOCOL *This, + IN UINT32 PinNum, + IN GPIO_DIRECTION GpioDirection + ) +{ + + BXT_CONF_PAD0 PadConfig0; + + if (PinNum>=3Dsizeof (mGpioPadTable)/sizeof (mGpioPadTable[0])) { + DEBUG ((DEBUG_INFO, "PinNum out of range.\n")); + return EFI_UNSUPPORTED; + } + + PadConfig0.padCnf0 =3D GpioPadRead (mGpioPadTable[PinNum].CommAndOffset = + BXT_GPIO_PAD_CONF0_OFFSET); + // + // Check pad mode + // + if (PadConfig0.r.PMode !=3D M0) { + DEBUG ((DEBUG_INFO, "Not GPIO mode\n")); + return EFI_UNSUPPORTED; + } + + PadConfig0.r.GPIORxTxDis =3D GpioDirection; //Set to GPI/GPO/GPIO + GpioPadWrite (mGpioPadTable[PinNum].CommAndOffset + BXT_GPIO_PAD_CONF0_O= FFSET, PadConfig0.padCnf0); + + PadConfig0.padCnf0 =3D GpioPadRead (mGpioPadTable[PinNum].CommAndOffset = + BXT_GPIO_PAD_CONF0_OFFSET); + DEBUG ((DEBUG_INFO, "PAD_CONF0: 0x%08x\n", PadConfig0.padCnf0)); + + return EFI_SUCCESS; +}=20 + + +/** + Check GPIO direction, if it is GPI, get input value. + + @param[in] This A pointer to the EDKII_GPIO_PROTOCOL = instance. + @param[in] PinNum Target GPIO. + @param[out] InputVal GPIO Input value + 0: InputLow, 1: InputHigh + + @retval EFI_SUCCESS The operation succeeded. + @retval EFI_UNSUPPORTED This function is not supported. +**/ +EFI_STATUS +EFIAPI +GetGpiLevel ( + IN EDKII_GPIO_PROTOCOL *This, + IN UINT32 PinNum, + OUT GPIO_LEVEL *GpiLevel + ) +{ + BXT_CONF_PAD0 PadConfig0; + + if (PinNum>=3Dsizeof (mGpioPadTable)/sizeof (mGpioPadTable[0])) { + DEBUG ((DEBUG_INFO, "PinNum out of range.\n")); + return EFI_UNSUPPORTED; + } + + PadConfig0.padCnf0 =3D GpioPadRead (mGpioPadTable[PinNum].CommAndOffset = + BXT_GPIO_PAD_CONF0_OFFSET); + // + // Check pad mode + // + if (PadConfig0.r.PMode !=3D M0) { + DEBUG ((DEBUG_INFO, "Not GPIO mode\n")); + return EFI_UNSUPPORTED; + } + + if (PadConfig0.r.GPIORxTxDis =3D=3D GPI) { + *GpiLevel =3D (PadConfig0.padCnf0 & 0x02) >> 1; + DEBUG ((DEBUG_INFO, "Pad direction is GPI, value is %x\n", *GpiLevel))= ; + } else { + DEBUG ((DEBUG_INFO, "Not GPI. Return.\n")); + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + + +/** + Check GPIO direction, if it is GPO, Set output value. + + @param[in] This A pointer to the EDKII_GPIO_PROTOCOL = instance. + @param[in] PinNum Target GPIO. + @param[in] GpoState GPO output value + 0: Low, 1: High + + @retval EFI_SUCCESS The operation succeeded. + @retval EFI_UNSUPPORTED This function is not supported. +**/ +EFI_STATUS +EFIAPI +SetGpoLevel ( + IN EDKII_GPIO_PROTOCOL *This, + IN UINT32 PinNum, + IN GPIO_LEVEL GpoLevel + ) +{ + BXT_CONF_PAD0 PadConfig0; + + if (PinNum>=3Dsizeof (mGpioPadTable)/sizeof (mGpioPadTable[0])) { + DEBUG ((DEBUG_INFO, "PinNum out of range.\n")); + return EFI_UNSUPPORTED; + } + + PadConfig0.padCnf0 =3D GpioPadRead (mGpioPadTable[PinNum].CommAndOffset = + BXT_GPIO_PAD_CONF0_OFFSET); + // + // Check pad mode + // + if (PadConfig0.r.PMode !=3D M0) { + DEBUG ((DEBUG_INFO, "Not GPIO mode\n")); + return EFI_UNSUPPORTED; + } + if ( PadConfig0.r.GPIORxTxDis =3D=3D GPO ) { + GpioSetOutputValue (mGpioPadTable[PinNum].CommAndOffset, GpoLevel); + } else { + DEBUG ((DEBUG_INFO, "Not GPO. Return.\n")); + return EFI_UNSUPPORTED; + } + + PadConfig0.padCnf0 =3D GpioPadRead (mGpioPadTable[PinNum].CommAndOffset = + BXT_GPIO_PAD_CONF0_OFFSET); + DEBUG ((DEBUG_INFO, "PAD_CONF0: 0x%08x\n", PadConfig0.padCnf0)); + return EFI_SUCCESS; +} + + +/** + Entry point of GPIO protocol. + + @param[in] ImageHandle Handle for this drivers loaded image= protocol. + @param[in] SystemTable EFI system table. + + @retval EFI_SUCCESS Succesfully installed GpioProtocol d= river. + @retval other Errors occured. + +**/ +EFI_STATUS +EFIAPI +PlatformGpioConfigEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + return gBS->InstallProtocolInterface ( + &mHandle, + &gEdkiiGpioProtocolGuid, + EFI_NATIVE_INTERFACE, + &mGpioProtocol + ); +} + diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformGp= io/PlatformGpio.h b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/Pla= tformGpio/PlatformGpio.h new file mode 100644 index 0000000..546e91f --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformGpio/Plat= formGpio.h @@ -0,0 +1,152 @@ +/** @file + Internal header file for GPIO protocol. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + + +#include + +#include +#include +#include +#include +#include +#include + + +/** + Get Max GPIO count. + + @param[in] This A pointer to the EDKII_GPIO_PROTOCOL = instance. + @param[out] MaxCount Max GPIO count + + @retval EFI_SUCCESS The operation succeeded. +**/ +EFI_STATUS +EFIAPI +GetMaxCount ( + IN EDKII_GPIO_PROTOCOL *This, + OUT UINT32 *MaxCount + ); + +/** + Get Pad Mode. + + @param[in] This A pointer to the EDKII_GPIO_PROTOCOL = instance. + @param[in] PinNum Target GPIO. + @param[out] PadMode 0: Function 0 (GPIO mode), + 1: Function 1, 2: Function 2, 3: Func= tion 3, 4: Function 4, 5: Function 5 + + @retval EFI_SUCCESS The operation succeeded. + @retval EFI_UNSUPPORTED This function is not supported. +**/ +EFI_STATUS +EFIAPI +GetMode ( + IN EDKII_GPIO_PROTOCOL *This, + IN UINT32 PinNum, + OUT PAD_MODE *PadMode + ); + +/** + Set Pad Mode to Fn0/Fn1/Fn2/Fn3/Fn4/Fn5. + + @param[in] This A pointer to the EDKII_GPIO_PROTOCOL = instance. + @param[in] GPIO_NAME Target GPIO.=20 + @param[out] PMode GPIO mode to set. + + @retval EFI_SUCCESS The operation succeeded. + @retval EFI_UNSUPPORTED This function is not supported. +**/ +EFI_STATUS +EFIAPI +SetMode ( + IN EDKII_GPIO_PROTOCOL *This, + IN UINT32 PinNum, + IN PAD_MODE PadMode + ); + +/** + Check GPIO direction. + + @param[in] This A pointer to the EDKII_GPIO_PROTOCOL = instance. + @param[in] PinNum Target GPIO. + @param[out] GpioDirection =20 + + @retval EFI_SUCCESS The operation succeeded. + @retval EFI_UNSUPPORTED This function is not supported. +**/ +EFI_STATUS +EFIAPI +GetGpioDirection ( + IN EDKII_GPIO_PROTOCOL *This, + IN UINT32 PinNum, + OUT GPIO_DIRECTION *GpioDirection + ); + +/** + Set GPIO direction to GPI/GPO/GPIO. + + @param[in] This A pointer to the EDKII_GPIO_PROTOCOL = instance. + @param[in] PinNum Target GPIO. + @Param[in] GpioDirection =20 + + @retval EFI_SUCCESS The operation succeeded. + @retval EFI_UNSUPPORTED This function is not supported. +**/ +EFI_STATUS +EFIAPI +SetGpioDirection ( + IN EDKII_GPIO_PROTOCOL *This, + IN UINT32 PinNum, + IN GPIO_DIRECTION GpioDirection + ); + +/** + Check GPIO direction, if it is GPI, get input value. + + @param[in] This A pointer to the EDKII_GPIO_PROTOCOL = instance. + @param[in] PinNum Target GPIO. + @param[out] InputVal GPIO Input value + 0: InputLow, 1: InputHigh + + @retval EFI_SUCCESS The operation succeeded. + @retval EFI_UNSUPPORTED This function is not supported. +**/ +EFI_STATUS +EFIAPI +GetGpiLevel ( + IN EDKII_GPIO_PROTOCOL *This, + IN UINT32 PinNum, + OUT GPIO_LEVEL *GpiLevel + ); + +/** + Check GPIO direction, if it is GPO, Set output value. + + @param[in] This A pointer to the EDKII_GPIO_PROTOCOL = instance. + @param[in] PinNum Target GPIO. + @param[in] GpoState GPO output value + 0: Low, 1: High + + @retval EFI_SUCCESS The operation succeeded. + @retval EFI_UNSUPPORTED This function is not supported. +**/ +EFI_STATUS +EFIAPI +SetGpoLevel ( + IN EDKII_GPIO_PROTOCOL *This, + IN UINT32 PinNum, + IN GPIO_LEVEL GpoLevel + ); + diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformGp= io/PlatformGpio.inf b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/P= latformGpio/PlatformGpio.inf new file mode 100644 index 0000000..a24907c --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformGpio/Plat= formGpio.inf @@ -0,0 +1,52 @@ +## @file +# Component description file for Gpio protocol. +# +# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformGpio + FILE_GUID =3D F6160CDD-5B92-4324-B83C-0208A5592CC5 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PlatformGpioConfigEntryPoint + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[Sources] + PlatformGpio.c + PlatformGpio.h + +[Packages] + MdePkg/MdePkg.dec + BroxtonSiPkg/BroxtonSiPkg.dec + BroxtonPlatformPkg/PlatformPkg.dec + +[LibraryClasses] + PcdLib + UefiRuntimeServicesTableLib + UefiBootServicesTableLib + UefiDriverEntryPoint + DebugLib + BaseLib + GpioLib + +[Protocols] + gEdkiiGpioProtocolGuid # PROTOCOL ALWAYS_PRODUCED + +[Depex] + TRUE diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc b/Platf= orm/BroxtonPlatformPkg/PlatformDsc/Components.dsc index 7ac8da8..6bb2a77 100644 --- a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc +++ b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc @@ -209,6 +209,7 @@ =20 $(PLATFORM_PACKAGE_COMMON)/DptfDxe/DptfDxe.inf $(PLATFORM_PACKAGE_COMMON)/PnpDxe/PnpDxe.inf + $(PLATFORM_PACKAGE_COMMON)/PlatformSettings/PlatformGpio/PlatformGpio.in= f =20 !if $(SEC_ENABLE) =3D=3D TRUE $(PLATFORM_PACKAGE_COMMON)/SeCPolicyInitDxe/SeCPolicyInitDxe.inf diff --git a/Platform/BroxtonPlatformPkg/PlatformPkg.dec b/Platform/Broxton= PlatformPkg/PlatformPkg.dec index 13eb5f9..b318b58 100644 --- a/Platform/BroxtonPlatformPkg/PlatformPkg.dec +++ b/Platform/BroxtonPlatformPkg/PlatformPkg.dec @@ -3,7 +3,7 @@ # # This package provides platform specific modules. # -# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -151,6 +151,8 @@ gEfiTrEEPlatformProtocolGuid =3D { 0x77ef4b99, 0x1186, 0x= 48ab, { 0x9d, 0x0b, 0x0b, 0x78, 0x12, 0xe5, 0xe6, 0xab }} gLegacyUsbProtocolGuid =3D { 0x2ad8e2d2, 0x2e91, 0x= 4cd1, { 0x95, 0xf5, 0xe7, 0x8f, 0xe5, 0xeb, 0xe3, 0x16 }} =20 + gEdkiiGpioProtocolGuid =3D { 0x239a4037, 0x5231, 0x44d6= , {0xa2, 0xab, 0x51, 0x74, 0xcd, 0x81, 0xff, 0x85 }} + [PcdsDynamic,PcdsDynamicEx] # 0x00000000 gMinnowModuleTokenSpaceGuid.PcdMinnowBoardDetectionRun|FALSE|BOOLEAN|0x0= 0000001 gMinnowModuleTokenSpaceGuid.PcdMinnowBoardDetected|FALSE|BOOLEAN|0x00000= 002 diff --git a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf b/Platform/Broxton= PlatformPkg/PlatformPkg.fdf index ac09ac3..4324f4f 100644 --- a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf +++ b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf @@ -576,6 +576,7 @@ APRIORI DXE { } =20 INF $(PLATFORM_PACKAGE_COMMON)/PnpDxe/PnpDxe.inf + INF $(PLATFORM_PACKAGE_COMMON)/PlatformSettings/PlatformGpio/PlatformGpi= o.inf =20 # # Secure Boot --=20 2.10.1.windows.1